GB1444228A - Data structure processor - Google Patents
Data structure processorInfo
- Publication number
- GB1444228A GB1444228A GB4549472A GB4549472A GB1444228A GB 1444228 A GB1444228 A GB 1444228A GB 4549472 A GB4549472 A GB 4549472A GB 4549472 A GB4549472 A GB 4549472A GB 1444228 A GB1444228 A GB 1444228A
- Authority
- GB
- United Kingdom
- Prior art keywords
- address
- groups
- translator
- store
- words
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Abstract
1444228 Data processing NATIONAL RESEARCH DEVELOPMENT CORP 18 Sept 1973 [3 Oct 1972] 45494/72 Heading G4A A data processing system includes an addressable primary store and an address translator including address storage means and arranged in response to an applied address to provide an associated, translated address to the primary store, the address translator being arranged to change the association between applied and translated addresses without the transfer to the address storage means of further addresses. A sixteen word primary store 13 is addressed by four bits from register 19 via translator 14. The translator, Fig. 2a, includes four groups E-H each of two single bit registers, and operates only on the two most significant bits of the address to address one of four groups A-E of words, each group containing four words. The two most significant bits are applied to a decoder which produces one out of four outputs α 0 -α 3 to gate via gates 27-34, the contents of the corresponding group of registers to the address inputs of store 13. Further gates 35-42, and 51-66 together with two groups K, L of buffer registers are provided to exchange the contents of pairs of groups of the registers E 2 - H 3 whereby the association between an address applied to the decoder and the address supplied by the translator is changed. Further address modification is provided by exclusive-ORing, at 18, a flag bit (1 or 0) with the address in register 19 to provide a modified address which is then supplied to the translator as above. Assuming block A in store 13 is addressed with an address whose two most significant bits are 0, 0 and block B by an address 0, 1, then by exclusive-ORing a flag 1 with the second address bit an applied address 0, 0 produces an address 0, 1, and an applied address 0, 1, an address 0, 0. Thus blocks A and B are effectively interchanged. A similar modification, at 17, may be performed on the least significant address bit to effectively exchange words within a group. The arrangement is said to be of use in a data processing system providing a graphical output, e.g. on a CRT. The arrangement is also of use when processing mathematical expressions in that it enables a parameter in the expressions to be changed without necessarily requiring the whole expression to be recalculated. This is achieved using so called "plexes" which are groups of four words defining an operand or an operator. The plexes are stored in respective groups of words A-C in store 13 and the system is arranged to operate on operands stored in plexes in groups A and B in accordance with an operator in a plex stored in group C. Exemplary programs are described for calculating, for adding entries to and removing entries from a list, each plex in the list referring to the next, and using circular lists; address modification being used to effectively "move" plexes within store 13 without actually having to physically move data.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4549472A GB1444228A (en) | 1972-10-03 | 1972-10-03 | Data structure processor |
DE19732349590 DE2349590A1 (en) | 1972-10-03 | 1973-10-03 | DATA PROCESSING DEVICE |
JP48111322A JPS4994239A (en) | 1972-10-03 | 1973-10-03 | |
US05/598,877 US4010451A (en) | 1972-10-03 | 1975-07-24 | Data structure processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4549472A GB1444228A (en) | 1972-10-03 | 1972-10-03 | Data structure processor |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1444228A true GB1444228A (en) | 1976-07-28 |
Family
ID=10437431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4549472A Expired GB1444228A (en) | 1972-10-03 | 1972-10-03 | Data structure processor |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS4994239A (en) |
DE (1) | DE2349590A1 (en) |
GB (1) | GB1444228A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860192A (en) * | 1985-02-22 | 1989-08-22 | Intergraph Corporation | Quadword boundary cache system |
US4884197A (en) * | 1985-02-22 | 1989-11-28 | Intergraph Corporation | Method and apparatus for addressing a cache memory |
US4899275A (en) * | 1985-02-22 | 1990-02-06 | Intergraph Corporation | Cache-MMU system |
US4933835A (en) * | 1985-02-22 | 1990-06-12 | Intergraph Corporation | Apparatus for maintaining consistency of a cache memory with a primary memory |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5255384A (en) * | 1985-02-22 | 1993-10-19 | Intergraph Corporation | Memory address translation system having modifiable and non-modifiable translation mechanisms |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5191300A (en) * | 1975-02-10 | 1976-08-10 | Sutebiosaido no seiseihoho | |
JPS5672750A (en) * | 1979-11-19 | 1981-06-17 | Nec Corp | Memory device |
-
1972
- 1972-10-03 GB GB4549472A patent/GB1444228A/en not_active Expired
-
1973
- 1973-10-03 JP JP48111322A patent/JPS4994239A/ja active Pending
- 1973-10-03 DE DE19732349590 patent/DE2349590A1/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860192A (en) * | 1985-02-22 | 1989-08-22 | Intergraph Corporation | Quadword boundary cache system |
US4884197A (en) * | 1985-02-22 | 1989-11-28 | Intergraph Corporation | Method and apparatus for addressing a cache memory |
US4899275A (en) * | 1985-02-22 | 1990-02-06 | Intergraph Corporation | Cache-MMU system |
US4933835A (en) * | 1985-02-22 | 1990-06-12 | Intergraph Corporation | Apparatus for maintaining consistency of a cache memory with a primary memory |
US5255384A (en) * | 1985-02-22 | 1993-10-19 | Intergraph Corporation | Memory address translation system having modifiable and non-modifiable translation mechanisms |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
Also Published As
Publication number | Publication date |
---|---|
JPS4994239A (en) | 1974-09-06 |
DE2349590A1 (en) | 1974-04-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |