GB1444084A - Generalized logic device - Google Patents

Generalized logic device

Info

Publication number
GB1444084A
GB1444084A GB2894072A GB2894072A GB1444084A GB 1444084 A GB1444084 A GB 1444084A GB 2894072 A GB2894072 A GB 2894072A GB 2894072 A GB2894072 A GB 2894072A GB 1444084 A GB1444084 A GB 1444084A
Authority
GB
United Kingdom
Prior art keywords
matrix
flip
gates
storage devices
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2894072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Information Systems Ltd
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Ltd
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Ltd, Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Ltd
Priority to GB2894072A priority Critical patent/GB1444084A/en
Publication of GB1444084A publication Critical patent/GB1444084A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Abstract

1444084 Logic HONEYWELL INFORMATION SYSTEMS Ltd 18 Sept 1973 [21 June 1972] 28940/72 Heading G4H A generalized logic device comprises a set of logic elements (e.g. gates, flip-flops) 10 whose inputs and outputs form rows and columns respectively of a rectangular matrix 11 of lines, gates interconnecting the row and column lines at their intersections, a corresponding matrix 14 of storage devices controlling these gates, and means for setting the storage devices to a desired combination of states. The storage devices of matrix 14 are flip-flops addressed row-wise by an address register 15 to receive signals from a data register 16 in response to information from a computer memory via an interfacing unit 19. Each flip-flop in matrix 14 controls a respective gate in matrix 11 to connect a respective column to a respective row or not. The columns of matrix 11 are fed with the device inputs 12B (as stated) the outputs from set of logic elements 10. The rows of matrix 11 provide the device outputs 13B and (as stated) the inputs to set of logic elements 10.
GB2894072A 1972-06-21 1972-06-21 Generalized logic device Expired GB1444084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2894072A GB1444084A (en) 1972-06-21 1972-06-21 Generalized logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2894072A GB1444084A (en) 1972-06-21 1972-06-21 Generalized logic device

Publications (1)

Publication Number Publication Date
GB1444084A true GB1444084A (en) 1976-07-28

Family

ID=10283655

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2894072A Expired GB1444084A (en) 1972-06-21 1972-06-21 Generalized logic device

Country Status (1)

Country Link
GB (1) GB1444084A (en)

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005847A1 (en) * 1978-06-05 1979-12-12 International Business Machines Corporation Memory circuit and its use in an electrically programmable logic array
WO1980001029A1 (en) * 1978-11-01 1980-05-15 Massachusetts Inst Technology Storage/logic array
GB2171805A (en) * 1985-03-01 1986-09-03 Simulog Ltd Hardware logic simulator
GB2195797A (en) * 1986-09-04 1988-04-13 Pilkington Micro Electronics Semiconductor integrated circuits
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5220215A (en) * 1992-05-15 1993-06-15 Micron Technology, Inc. Field programmable logic array with two or planes
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture
US5260611A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic array having local and long distance conductors
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5329470A (en) 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5371422A (en) * 1991-09-03 1994-12-06 Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5436575A (en) * 1991-09-03 1995-07-25 Altera Corporation Programmable logic array integrated circuits
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5543730A (en) * 1995-05-17 1996-08-06 Altera Corporation Techniques for programming programmable logic array devices
US5625580A (en) 1989-05-31 1997-04-29 Synopsys, Inc. Hardware modeling system and method of use
US5760607A (en) * 1995-07-10 1998-06-02 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
US5815726A (en) * 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US5841967A (en) 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5884066A (en) 1994-02-16 1999-03-16 Quickturn Design Systems, Inc. Method and apparatus for a trace buffer in an emulation system
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6181162B1 (en) 1994-04-10 2001-01-30 Altera Corporation Programmable logic device with highly routable interconnect
US6184706B1 (en) 1996-04-05 2001-02-06 Altera Corporation Logic device architecture and method of operation
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US6191611B1 (en) 1997-10-16 2001-02-20 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources
US6384630B2 (en) 1996-06-05 2002-05-07 Altera Corporation Techniques for programming programmable logic array devices
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US7171548B2 (en) 1998-11-20 2007-01-30 Altera Corporation Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources
US7219342B2 (en) 2000-08-07 2007-05-15 Altera Corporation Software-to-hardware compiler
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7379859B2 (en) 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language

Cited By (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005847A1 (en) * 1978-06-05 1979-12-12 International Business Machines Corporation Memory circuit and its use in an electrically programmable logic array
EP0020608A4 (en) * 1978-11-01 1981-03-24 Massachusetts Inst Technology Programmable storage/logic array.
EP0020608A1 (en) * 1978-11-01 1981-01-07 Massachusetts Inst Technology Programmable storage/logic array.
WO1980001029A1 (en) * 1978-11-01 1980-05-15 Massachusetts Inst Technology Storage/logic array
GB2171805A (en) * 1985-03-01 1986-09-03 Simulog Ltd Hardware logic simulator
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
GB2195797A (en) * 1986-09-04 1988-04-13 Pilkington Micro Electronics Semiconductor integrated circuits
GB2195797B (en) * 1986-09-04 1991-04-03 Pilkington Micro Electronics Semiconductor integrated circuits
US6377911B1 (en) 1988-12-02 2002-04-23 Quickturn Design Systems, Inc. Apparatus for emulation of electronic hardware system
US5329470A (en) 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5963735A (en) 1988-12-02 1999-10-05 Quickturn Design Systems, Inc. Hardware logic emulation system
US5644515A (en) 1988-12-02 1997-07-01 Quickturn Design Systems, Inc. Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation
US6842729B2 (en) 1988-12-02 2005-01-11 Quickturn Design Systems, Inc. Apparatus for emulation of electronic systems
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5625580A (en) 1989-05-31 1997-04-29 Synopsys, Inc. Hardware modeling system and method of use
US5371422A (en) * 1991-09-03 1994-12-06 Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5376844A (en) * 1991-09-03 1994-12-27 Altera Corporation Programmable logic device with multiplexer-based programmable interconnections
US5436575A (en) * 1991-09-03 1995-07-25 Altera Corporation Programmable logic array integrated circuits
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5260611A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic array having local and long distance conductors
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture
US5220215A (en) * 1992-05-15 1993-06-15 Micron Technology, Inc. Field programmable logic array with two or planes
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5884066A (en) 1994-02-16 1999-03-16 Quickturn Design Systems, Inc. Method and apparatus for a trace buffer in an emulation system
US6181162B1 (en) 1994-04-10 2001-01-30 Altera Corporation Programmable logic device with highly routable interconnect
US5815726A (en) * 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US6122720A (en) * 1994-11-04 2000-09-19 Altera Corporation Coarse-grained look-up table architecture
US6184705B1 (en) 1995-05-17 2001-02-06 Altera Corporation Techniques for programming programmable logic array devices
US5543730A (en) * 1995-05-17 1996-08-06 Altera Corporation Techniques for programming programmable logic array devices
US5680061A (en) * 1995-05-17 1997-10-21 Altera Corporation Techniques for programming programmable logic array devices
US6191608B1 (en) 1995-05-17 2001-02-20 Altera Corporation Techniques for programming programmable logic array devices
US5760607A (en) * 1995-07-10 1998-06-02 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
US6414514B1 (en) 1996-04-05 2002-07-02 Altera Corporation Logic device architecture and method of operation
US6492834B1 (en) 1996-04-05 2002-12-10 Altera Corporation Programmable logic device with highly routable interconnect
US6208162B1 (en) 1996-04-05 2001-03-27 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6294928B1 (en) 1996-04-05 2001-09-25 Altera Corporation Programmable logic device with highly routable interconnect
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6184706B1 (en) 1996-04-05 2001-02-06 Altera Corporation Logic device architecture and method of operation
US6384630B2 (en) 1996-06-05 2002-05-07 Altera Corporation Techniques for programming programmable logic array devices
US5841967A (en) 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6058492A (en) 1996-10-17 2000-05-02 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6377912B1 (en) 1997-05-30 2002-04-23 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6636070B1 (en) 1997-10-16 2003-10-21 Altera Corp Driver circuitry for programmable logic devices with hierarchical interconnection resources
US6480025B1 (en) 1997-10-16 2002-11-12 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources
US6191611B1 (en) 1997-10-16 2001-02-20 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US7171548B2 (en) 1998-11-20 2007-01-30 Altera Corporation Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources
USRE42444E1 (en) 1998-11-20 2011-06-07 Altera Corporation Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7257780B2 (en) 2000-08-07 2007-08-14 Altera Corporation Software-to-hardware compiler
US7219342B2 (en) 2000-08-07 2007-05-15 Altera Corporation Software-to-hardware compiler
US8332831B1 (en) 2000-08-07 2012-12-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US8473926B2 (en) 2000-08-07 2013-06-25 Altera Corporation Software-to-hardware compiler
US8930922B2 (en) 2000-08-07 2015-01-06 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7379859B2 (en) 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
US9449132B2 (en) 2012-02-09 2016-09-20 Altera Corporation Configuring a programmable device using high-level language
US10366189B2 (en) 2012-02-09 2019-07-30 Altera Corporation Configuring a programmable device using high-level language

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee