GB1432835A - Data storage system - Google Patents

Abstract

1432835 Data storage systems INTERNATIONAL BUSINESS MACHINES CORP 2 May 1973 [3 May 1972] 20962/73 Heading G4A In a data storage system an associative store 32 (Fig. 5), on receipt of an address for data from a central processing unit either causes read out of the required. data from a random access store 31 if it is stored therein or causes transfer of the addressed data from a sequential store 50 to the random access store 31 with subsequent read out from the latter. As described on receipt of an address on lead 34, the high order address bits are fed to associative store 32. If the address for data is held in store 31, store 32 generates a match signal to enable gate 36 and provides a seven bit address. Data read out from the store 31 is fed on lead 33 to either the main memory or high speed buffer or processor. If however the associative store generates a "mis-match" signal gate 38 is enabled and thus the high and low order address bits on lead 34 are fed to disc file 50 to cause read out of the required data to store 31, associative store 32 being simultaneously updated via lead 42. Subsequently gate 36 is enabled and the store 31 is addressed to read out the requested data on lead 33. A machine interrupt is generated on lead 43 during the transfer of data. In the embodiment of Fig. 6 (not shown) the random access store (61) is divided into two sections, a section (62A) holding leader pages, e.g. page 1, page P+ 1, page 2P+ 1 and a second section (62B) capable of holding P-1 pages. If an address signal results in associative memory (63) generating a "match" signal higher order address bits from the associative store cause read out from the leader page section (62A) of the random access store. A counter (65) which also receives the high order address bits is simultaneously incremented by 1. As data is read out from the first section (62A) a gate (70) is enabled so that the address in the counter (65) is used to access disc file (50A). This results in the next page being fed from the disc file into the second section (62B) of the random access store so that when the last word of the leader page is read from the first section the next page may be read out from the second section (62B). If however a "mis-match" signal is generated a gate (81) is enabled so that the address bits are fed to disc file (50A) to cause read out of the address data to the first section (62A) of the random access store, the associative memory being simultaneously updated so that a match signal is then generated and the system operates as above. The random access store preferably comprises an array of charge coupled memory cells 15 each comprising a semi-conductor body divided into three regions, the first having an impurity diffused or ions implanted therein, the second serving as a gate between the first and third regions and the third region functioning as a capacitor. The first region is used as the bit line and the second region as the work line, addressing being controlled by bit and word line decoders. The disc store may be replaced by a drum or tape.