GB1427622A - Transmission systems - Google Patents

Abstract

1427622 Data transmission; error correction STANDARD TELEPHONES & CABLES Ltd 8 Jan 1974 [23 Jan 1973] 3482/73 Heading H4P In an electrical data transmission system in which each packet of a message is preceded by a plural bit label including information identifying the message and the packet, where packets of a message have to pass through one or more switching centres SC1, SC2, SC3, Fig. 1, so that they have to traverse two or more inter-centre links to reach the message's destination, error detection and correction (EDC) facilities are provided separately for each of the links, and in which for the data as transmitted via the links the sizes of the error detection and connection (EDC) blocks need not be the same on all of the links, so that dependent on the relative sizes of the packets and the EDC blocks a packet is conveyed over a link as one or more EDC blocks, and so that the EDC facilities do not affect the message structure. Fig. 2 shows the sending end EDC equipment. Normally gate G101 is closed. The EDC transmit terminal contains a counter recording the number of consecutive unsuccessful retransmission cycles performed. When this counter reaches a predetermined total, the terminal signals a prolonged fault by way of EDC control to a switching centre processor. At the same time it halts the retransmission data stored at a point when the next block to emerge is the earliest chronologically held in the store. When the switching centre processor is ready to transmit over an alternative route such as from a communications processor at switching centre SC1, Fig. 1 to SC2 via SC3 rather than directly to SC2 by the faulty link the processor signals the EDC control unit. This causes gates G101, G102 and G103 to open through which the data digits held in the retransmission store, the reading of the transmit side block sequence counter and the reading of the receiver side sequence counter are supplied to the processor. Assuming the retransmission cycle is of three blocks and that each block contains "h" information digits, the sequence numbering is in a cycle of 4. If now the EDC terminal of a link signals a prolonged fault to the switching centre processor and the next block desired by the receive side of the EDC terminal would have been sequence number 2 then over another route the processor receives a special packet header announcing a continuation of the interrupted traffic and that data starts with the digits originally sent over the faulty link in a block with sequence number "4". Under these conditions the EDC transmit terminal at the remote end of the faulty link was performing a retransmission cycle with blocks numbered 4, 1, 2 (in that order) and blocks 4 and 1 were correctly received before the fault, but the acknowledgements of these blocks were corrupted in transmission. To avoid duplication of data blocks the first 2h data blocks correctly received after the special header, over the alternative route must be discarded. If the fault is corrected then can switch back to original link for remainder of message.