GB1405353A - Process and apparatus for automatic generation of mini-computer instructions for dicrete classes of applications - Google Patents
Process and apparatus for automatic generation of mini-computer instructions for dicrete classes of applicationsInfo
- Publication number
- GB1405353A GB1405353A GB3614673A GB3614673A GB1405353A GB 1405353 A GB1405353 A GB 1405353A GB 3614673 A GB3614673 A GB 3614673A GB 3614673 A GB3614673 A GB 3614673A GB 1405353 A GB1405353 A GB 1405353A
- Authority
- GB
- United Kingdom
- Prior art keywords
- code
- activity
- instructions
- file
- records
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Stored Programmes (AREA)
Abstract
1405353 Data processing BURROUGHS CORP 30 July 1973 [13 Feb 1973] 36146/73 Heading G4A A digital computer is used to generate a program of machine-level instructions for a target computer from a coded representation of the general solution to a class of problems and parameters defining a specific problem and a hardware specification of the target computer. A description of the problem structure for the class of problems considered is input, in an application Specification language ASL, to a compiler which converts the description to a structure code, segmented by activity, and a code generator, which may be a general or special purpose computer, uses the structure code and parameters to generate machine-level instructions for the target computer. Thus specific applications programs for different devices may be generated automatically, e.g. for controlling a particular mini-computer to emulate a desk calculator. Problem Specification.-The ASL comprises two basic categories of words-nouns and verbs and has provision for designating alpha or numeric literals. The nouns include names of activities (to identify a series of statements or instructions), parameter names (containing reference information to another noun or a particular numeric value), condition names and label function names (containing information necessary for addressing functions in the target machine). The verbs indicate an operation with respect to or modified by a noun. The language is such that the various activities required for the particular application and target machine can be represented in a tree structure. The ASL compiler (1) initiates all output files required (activity name, activity library and alpha-literal) and allocates space in core memory for tables; (2) scans ASL statements and generates structure code according to an ASL grammar file. For each new activity named an entry is made in an activity name file, the entry including a pointer to a location in an activity library file where a series of structure code elements (procedures or instructions) that define the activity are stored. The Specification includes details of instruction sequences used by the compiler to add records to, modify records in and generally to maintain the various files. In general terms, the compiler reads the ASL statements one by one from punched cards or magnetic tape and scans the words in each statement to select the appropriate compiler routines. The structure code includes a control identifier indicating the location of instructions in the activity library file, an OP code indicating what actions the code generator has to take to convert the instructions to target machine code, an output file indicator directing the code generator to a specific output file location; a control identifier specifying the location of information items or parameters in files or tables, and the location in the activity name file of the activity name for each group of instructions. Code generator. - Application parameter statements, e.g. specifying functions to be performed in emulating a calculator, are read, e.g. from punched cards and corresponding entries are made in a parameter-condition (Parcon) table after reference to a parameter grammar file. Conversion of the structure code to machine code involves reading activity names from the activity name file, reading the corresponding group of structure code elements from the activity library file, and processing the elements to generate the object code. Activity identifiers are entered in a memory stack preserving the order in which they occur in the tree structure, and the stacked identifiers are used to sequentially access the activity names occurring in each branch of the tree, each name being used to access the activity library file. As each structure code element is accessed, the appropriate instruction sequence for processing the element is selected, based on the OP code of the element. Selection of instruction sequences and modification of various values in the instructions are determined by the contents of the Parcon and other files. Two types of object code record are generated, code format records containing words of object code, and documentation records that contain instructions and error messages for operating the target machine. Both types of records include sort keys for use in sorting records into proper sequence. Finally, a base address table for locating object code instructions within the final object program is formed, relative addresses in the label function table are resolved into absolute addresses and a sort, based on the keys, is performed to load code format and documentation records in correct sequence into respective output files.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN2108/CAL/73A IN140085B (en) | 1973-07-30 | 1973-09-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33210173A | 1973-02-13 | 1973-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1405353A true GB1405353A (en) | 1975-09-10 |
Family
ID=23296730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3614673A Expired GB1405353A (en) | 1973-02-13 | 1973-07-30 | Process and apparatus for automatic generation of mini-computer instructions for dicrete classes of applications |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5025144A (en) |
BE (1) | BE810674A (en) |
FR (1) | FR2288351A1 (en) |
GB (1) | GB1405353A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2195479A (en) * | 1986-09-05 | 1988-04-07 | Hitachi Ltd | Planning support method and system |
CN113761045A (en) * | 2021-09-03 | 2021-12-07 | 中国人民解放军63920部队 | Spacecraft uplink control data generation method and device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631142A (en) * | 1979-08-23 | 1981-03-28 | Fujitsu Ltd | Cobol conversion processing method |
JPS5680748A (en) * | 1979-12-06 | 1981-07-02 | Fujitsu Ltd | Data processor programmable in ideographic language |
US4791558A (en) * | 1987-02-13 | 1988-12-13 | International Business Machines Corporation | System and method for generating an object module in a first format and then converting the first format into a format which is loadable into a selected computer |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3375499A (en) * | 1964-10-14 | 1968-03-26 | Bell Telephone Labor Inc | Telephone switching system control and memory apparatus organization |
-
1973
- 1973-07-30 GB GB3614673A patent/GB1405353A/en not_active Expired
-
1974
- 1974-01-30 JP JP49013593A patent/JPS5025144A/ja active Pending
- 1974-02-06 BE BE140605A patent/BE810674A/en unknown
- 1974-02-11 FR FR7404492A patent/FR2288351A1/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2195479A (en) * | 1986-09-05 | 1988-04-07 | Hitachi Ltd | Planning support method and system |
US4839803A (en) * | 1986-09-05 | 1989-06-13 | Hitachi, Ltd. | Planning support method and system |
CN113761045A (en) * | 2021-09-03 | 2021-12-07 | 中国人民解放军63920部队 | Spacecraft uplink control data generation method and device |
CN113761045B (en) * | 2021-09-03 | 2024-03-26 | 中国人民解放军63920部队 | Spacecraft uplink control data generation method and device |
Also Published As
Publication number | Publication date |
---|---|
JPS5025144A (en) | 1975-03-17 |
FR2288351A1 (en) | 1976-05-14 |
FR2288351B1 (en) | 1978-01-06 |
BE810674A (en) | 1974-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |