GB1402613A - Detection and correction of errors in information words - Google Patents
Detection and correction of errors in information wordsInfo
- Publication number
- GB1402613A GB1402613A GB3215872A GB3215872A GB1402613A GB 1402613 A GB1402613 A GB 1402613A GB 3215872 A GB3215872 A GB 3215872A GB 3215872 A GB3215872 A GB 3215872A GB 1402613 A GB1402613 A GB 1402613A
- Authority
- GB
- United Kingdom
- Prior art keywords
- error
- word
- correction
- errors
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
Abstract
1402613 Digital data error correction INTERNATIONAL BUSINESS MACHINES CORP 10 July 1972 [10 July 1971] 32158/72 Heading G4A Digital electric apparatus detects and corrects errors in information words read from a data store 1 (e.g. of monolithic semi-conductors), the words each having check bits. Each word has 16 data bits and 6 check bits (e.g. Hamming code) which bits allow the correction of single errors and the detection of double errors. A word is read out of the store and, of a double error is detected, the word is read out again, If the word has only sporadic errors it will probably be correct or only have one, correctible error when read-out again, but, if at least one error is permanent, then the or one of the permanent errors is corrected as described below using circuit KS5 and the sporadic error is later corrected in a known manner by circuit FKS3. Correction of Permanent Error.-In a first step CPU of the processor generates a first data pattern, the first bit being 1 and the rest zero, 6 check bits are generated for these, and the 22 bit word is stored in the location having a double error. Subsequently the stored word is read out and applied to error correction circuit FKS3. If a single error is detected, counter Z9 is incremented and a 1 passes to shift register 10 which is shifted once each checking step. In a second step the CPU generates a 16 bit data pattern where the second bit is 1 and the rest are 0 and the process is repeated. This continues for 16 steps (or however many data bits there are in the word), after which register 10 contains a pattern of 0's and l's (Fig. 4, not shown) used for correction in circuit FKS5 comprising n + k Exclusive OR circuits. A read only store FWS11-FWS16 generates checkbits P from the pattern in SR10 and applies them to correction circuit KS5.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19712134529 DE2134529A1 (en) | 1971-07-10 | 1971-07-10 | PROCEDURE FOR ERROR DETECTION AND CORRECTION IN INFORMATION WORDS READ OUT FROM THE MEMORY OF A PROGRAM-CONTROLLED DATA PROCESSING SYSTEM |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1402613A true GB1402613A (en) | 1975-08-13 |
Family
ID=5813290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3215872A Expired GB1402613A (en) | 1971-07-10 | 1972-07-10 | Detection and correction of errors in information words |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5428056B1 (en) |
DE (1) | DE2134529A1 (en) |
FR (1) | FR2146081A5 (en) |
GB (1) | GB1402613A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0032957B1 (en) * | 1979-07-30 | 1987-03-04 | Fujitsu Limited | Information processing system for error processing, and error processing method |
GB2476537A (en) * | 2009-12-22 | 2011-06-29 | Intel Corp | Error correction mechanisms for 8 bit memory devices to correct a single transient error or any number of permanent errors in a single device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2246023B1 (en) * | 1973-09-05 | 1976-10-01 | Honeywell Bull Soc Ind | |
US3999051A (en) * | 1974-07-05 | 1976-12-21 | Sperry Rand Corporation | Error logging in semiconductor storage units |
US3893071A (en) * | 1974-08-19 | 1975-07-01 | Ibm | Multi level error correction system for high density memory |
US4100403A (en) * | 1977-04-25 | 1978-07-11 | International Business Machines Corporation | Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays |
US4319357A (en) * | 1979-12-14 | 1982-03-09 | International Business Machines Corp. | Double error correction using single error correcting code |
US4345328A (en) * | 1980-06-30 | 1982-08-17 | Sperry Corporation | ECC Check bit generation using through checking parity bits |
-
1971
- 1971-07-10 DE DE19712134529 patent/DE2134529A1/en active Pending
-
1972
- 1972-06-28 JP JP6414072A patent/JPS5428056B1/ja active Pending
- 1972-07-10 GB GB3215872A patent/GB1402613A/en not_active Expired
- 1972-07-10 FR FR7225776A patent/FR2146081A5/fr not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0032957B1 (en) * | 1979-07-30 | 1987-03-04 | Fujitsu Limited | Information processing system for error processing, and error processing method |
GB2476537A (en) * | 2009-12-22 | 2011-06-29 | Intel Corp | Error correction mechanisms for 8 bit memory devices to correct a single transient error or any number of permanent errors in a single device |
GB2476537B (en) * | 2009-12-22 | 2012-07-04 | Intel Corp | Error correction mechanisms for 8-bit memory devices |
US8612828B2 (en) | 2009-12-22 | 2013-12-17 | Intel Corporation | Error correction mechanisms for 8-bit memory devices |
Also Published As
Publication number | Publication date |
---|---|
DE2134529A1 (en) | 1973-01-25 |
FR2146081A5 (en) | 1973-02-23 |
JPS5428056B1 (en) | 1979-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3814921A (en) | Apparatus and method for a memory partial-write of error correcting encoded data | |
GB1366013A (en) | Error checking and correcting system | |
US4296494A (en) | Error correction and detection systems | |
US4175692A (en) | Error correction and detection systems | |
US4993028A (en) | Error detection and correction coding | |
US4276646A (en) | Method and apparatus for detecting errors in a data set | |
US5418796A (en) | Synergistic multiple bit error correction for memory of array chips | |
EP0107038A2 (en) | Double error correction - triple error detection code for a memory | |
EP0339166B1 (en) | Extended errors correcting device having single package error correcting and double package error detecting codes | |
GB1511806A (en) | Error detection and correction in data processing systems | |
EP0176218B1 (en) | Error correcting system | |
GB2024472B (en) | Segmented error-correction system | |
GB1481373A (en) | Random access memory systems | |
GB1513831A (en) | Error handling apparatus | |
EP0096783A3 (en) | Method for storing data words in fault tolerant memory to recover uncorrectable errors | |
GB1326976A (en) | Error correction | |
DE3484587D1 (en) | DEVICE FOR REDUCING THE MEMORY IN DATA PROCESSING MACHINES REQUIRED FOR ERROR DETECTION AND CORRECTION. | |
KR850004675A (en) | Error correction and detection system | |
US3688265A (en) | Error-free decoding for failure-tolerant memories | |
US4236247A (en) | Apparatus for correcting multiple errors in data words read from a memory | |
JPH0728227B2 (en) | Decoding device for BCH code | |
GB1458610A (en) | Digital data handling systems | |
US3231858A (en) | Data storage interrogation error prevention system | |
GB1402613A (en) | Detection and correction of errors in information words | |
GB1287238A (en) | Error detection and correction apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |