GB1394432A - Input-output arrangement for use in a data processing system - Google Patents

Input-output arrangement for use in a data processing system

Info

Publication number
GB1394432A
GB1394432A GB2122173A GB2122173A GB1394432A GB 1394432 A GB1394432 A GB 1394432A GB 2122173 A GB2122173 A GB 2122173A GB 2122173 A GB2122173 A GB 2122173A GB 1394432 A GB1394432 A GB 1394432A
Authority
GB
United Kingdom
Prior art keywords
input
demand
input ports
input port
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2122173A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB2122173A priority Critical patent/GB1394432A/en
Publication of GB1394432A publication Critical patent/GB1394432A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

1394432 Input-output systems PLESSEY CO Ltd 16 June 1972 [24 June 1971] 21221/73 Divided out of 1394431 Heading G4A [Also in Division H4] Duplicated multi-stage switching networks α, # have cascaded stages DS, PS each of which scans a plurality of input ports and, on detection of a demand condition on an input port, passes the demand on towards a message handling device PA acting as a buffer between a data processing system CPS and the switching network. Each stage DS, PS, over which the demand is extended, appends an input port identification field to the address information of a message received from a peripheral device SCP initiating the demand each peripheral device being connected to at least one input port in each network α, #. For transmission in the opposite direction, reception of a demand by a switching stage causes it to stop scanning its input ports and to use an address field of a message to select one of the input ports for onward transmission of the remainder of the message. Each transmission path includes control, data and timing wires for each direction. In the arrangement shown, serial-paralle adapters PA have access units similar to those provided in the memory modules and peripheral units of the system described in Specification 1,394,431 and include command and status registers together with data-in and dataout register stacks to form an interface between that system and low activity peripheral devices SCP. Other features of the switching stage include (1) a register which is cycled in synchronism with the scanning of the input ports and which stores bits for controlling the acceptance of demands on the input ports, write access to the register being obtained via the input ports, (2) a pair of input port address counters whose states are compared to prevent any single fault causing an input port to be skipped. Each peripheral device has an associated access unit which includes an address recognition circuit and addressable control, status and data registers as in the peripheral access units described in the parent Specification 1,394,431. (For Figure see next page.)
GB2122173A 1971-06-24 1971-06-24 Input-output arrangement for use in a data processing system Expired GB1394432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2122173A GB1394432A (en) 1971-06-24 1971-06-24 Input-output arrangement for use in a data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2122173A GB1394432A (en) 1971-06-24 1971-06-24 Input-output arrangement for use in a data processing system

Publications (1)

Publication Number Publication Date
GB1394432A true GB1394432A (en) 1975-05-14

Family

ID=10159238

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2122173A Expired GB1394432A (en) 1971-06-24 1971-06-24 Input-output arrangement for use in a data processing system

Country Status (1)

Country Link
GB (1) GB1394432A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018755A1 (en) * 1979-05-02 1980-11-12 BURROUGHS CORPORATION (a Michigan corporation) Digital communication networks employing speed independent switches
EP0147046A2 (en) * 1983-11-14 1985-07-03 Tandem Computers Incorporated Fault-tolerant communications controlller system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018755A1 (en) * 1979-05-02 1980-11-12 BURROUGHS CORPORATION (a Michigan corporation) Digital communication networks employing speed independent switches
EP0147046A2 (en) * 1983-11-14 1985-07-03 Tandem Computers Incorporated Fault-tolerant communications controlller system
EP0147046A3 (en) * 1983-11-14 1987-07-15 Tandem Computers Incorporated Fault-tolerant communications controlller system

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee