GB1392524A - Timekeepers - Google Patents

Abstract

1392524 Time keeper CENTRE ELECTRONIQUE HORLOGER S A EN LIQUIDATION 8 March 1972 [15 Oct 1971] 10703/72 Heading G3T In a quartz crystal controlled watch wherein the pulse output of crystal controlled pulse generator 5 is divided by network 6, 8 to excite a step motor 10 energizing motion 11, corrections to the pulse output of unit 6, by blocking a single pulse when the input at D, unit 7 goes to "1", are controlled by the contents of memory 14. Input C provides for thermal compensation, or time setting. The step motor input waveform is also fed to multi-stage divider 12 whose outputs G-K are logically combined in unit 13, see also Fig. 7 (not shown), with binary digits L-P of the correction number from memory 14 to provide waveforms (Q, R), Fig. 10 (not shown), which, in unit 15 see also Fig. 9 (not shown), are processed to give the control waveform (F, Fig. 10) proportional to LMNOP read as a binary numeric. The latter is fed to AND gate 9 receiving also the step motor input waveform, the output D controlling the pulse subtraction in logic unit 7, see also Fig. 13 (not shown), which can change the mean pulse rate by a factor of up to 3.8 x 10<SP>-6</SP> in 26 digital steps. Unit 7 may be placed before the first divider 6. Alternative logic circuits, using a single, or multistage dividers and inverters, in addition to the AND and OR gates of the network of Fig. 13 (not shown), are displayed in Figs. 15 and 17 (not shown). A fourth embodiment Fig. 19 (not shown), includes also a flip-flop. Configurations of memory 14. For essentially permanent storage of correction number LMNOP, the memory may comprise, for each digit, a series pair of fusible elements (21, 22), Fig. 4 (not shown) across a supply, the input of a large current being used, to rupture any pair where it is required to store a "1". Possible non-permanent circuit memories may alternatively comprise (i) a shift register of series flip-flops (16-20) Fig. 3 (not shown), the correction number being applied to terminals (L-P) simultaneously with a control signal at (W); (ii) for each digit, a network including an MOS transistor with a nitrided layer, or floating grid reset by ultra-violet or X-radiation, enabling variation of transistor threshold, so that the supply can be changed without loss of data stored, Figs. 5, 6 (not shown), (iii) pairs of back-toback inverters, Fig. 21 (not shown), with supply (S 2 ) Fig. 22 (not shown), from a cell via a buffer capacitor or accumulator to enable change of power supply without data loss, (iv) a counter, Fig. 23 (not shown), data being introduced at input (I), digit by digit, via an access unit, Fig. 24 (not shown) receiving a seconds beat (A) to control data input (F). (v) a permanent, and non-permanent resettable, memories (97, 98), Fig. 27 (not shown) may be combined, the former providing data during supply change only. (vi) a permanent memory for coarse correction, and a non-permanent memory for fine correction may be combined, Fig. 28 (not shown).