GB1377795A - Information processing systems - Google Patents

Abstract

1377795 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE 7 April 1972 [9 April 1971] 16278/72 Heading G4A A priority dependent interrupt system, e.g. for allotting tasks of various priorities to a single processor for execution, includes a store 15 containing in zones associated with respective tasks data relating to those tasks, a store 13 arranged to store data relating to the task being executed, a register 1 and encoder 2 generating a code indicative of the highest priority task awaiting execution, a register 4 storing the priority of the current task, a comparator 5 responsive to the outputs of encoder 2 and register 4, and transfer means operable in response to each of the comparator output and a signal indicating completion of the current task to transfer the data from store 13 to the appropriate zone in store 15 and to transfer data relating to the next task from the appropriate zone of store 15 to store 13. The data transfers are performed via gates 17 and 19 under the control of address registers 12 and 14 which are in turn controlled by circuits 10 and 18 which include address counters. A priority circuit comprising latches 1 and an encoder 2 provides signals indicative of the highest priority waiting task. A subtracter 5 compares the code provided by circuit 2 with that in register 4 which is indicative of the task currently being executed. If the waiting task is of higher priority than the current task an interruption is signalled. Interrupt.-On the occurrence of a signal indicating that an interrupt may be made, e.g. which may be generated at the completion of each microinstruction in the current task, circuit 10 is energized. The data relating to the current task is then transferred to the appropriate zone in store 15 under control of the old code in register 4 which is subsequently replaced by the code, from circuit 2, of the interrupting task. Circuit 7 then computes the addresses of the corresponding data in store 15 (see below) which is transferred to store 13. The interrupting task is then executed. Normal sequencing.-If the waiting task or tasks have a lower priority than that currently being executed then no interruption is signalled. An instruction at the end of the current task enables gate 24 to transfer the code from register 4 to decoder 25 which energizes one output to reset the bi-stable 1 corresponding to the current task. The circuit 2 then produces the code for the highest priority waiting task. Circuit 10 is energized to transfer data from store 13 to store 15 under control of the old code in register 4, the new code is written into register 4 from encoder 2, and the corresponding data from store 15 is written into store 13. The waiting task then becomes the current task and is executed. Address generation.-The device 7 calculates the addresses of the required data in response to the code in register 4. The code is added to a base code to produce a result which may be used directly to address store 15. Alternatively the addresses may be read out from a stored table. Further details.-The transfer controllers 10 and 18 may, as stated, include counters. Alternatively the transfers may be made under microprogram control. The arrangement may be used to connect the highest priority requesting peripheral to a central unit, e.g. several processors requesting access to a common store, or to enable jumps to high priority sub-routines within a program on the occurrence of specific conditions.