GB1374357A - Data transmission systems - Google Patents

Abstract

1374357 Digital transmission; synchronization SIEMENS AG 25 Feb 1972 [18 March 1971 25 Jan 1972] 8870/72 Heading H4P In a synchronizing arrangement in which redundant bits are utilized, the redundant bits may also be used for synchronization of bit fault recognition. The blocks are received into a shift register having test circuits connected to individual cells which emit test signals on application of a series of timing signals if the bits in the shift register belong to the same block, there being as many trains of timing signals as possible data blocks. The outputs of the test circuits are passed to counters connected to a logic arrangement which determines which one of the timing trains are relative to the correct block. Preferably as many test circuits are provided as possible block arrangements. In a simple case each block B = 4 bits, the first and fourth being redundant bits which serve for synchronization. Trigger stages K1-K4 form a shift register having a test circuit P1-P4 connected thereto and a correct block arrangement exists when bit A1 = 0 and A4 = 1; the test circuits check bits in stages K1-K4 at different times. When correct lines h1-h4 emit Is or when incorrect this is signalled on lines g1-g4. Timing signals TB1-TB4 from LOG are supplied to terminals c of P1-P4. When inputs to half adder F are equal a O is emitted to AND gate U1 resetting counter AZ, also through inverter N1 to AND gate U2 which steps AZ forward; at max. count nAZ-# 1. Counters Z1-Z4 are stepped by signals a and reset by b ; at maximum count k a 1 is issued to LOG from which signals TA, TS, TB1-TB4 are derived. If the data bits A2, A3 have the values 0, 1, at time t3 a 1 is emitted from P3 through line h3 to Z3 thus a correct block arrangement is signalled. On the other hand incorrect blocks have no effect because counters are reset before arrival of the k counting pulse. Preferably A1, A4 are parity bits calculated from bits A2, A3 hence may be used for error correction in addition to block synchronization.