GB1364518A - Message encoding apparatus - Google Patents

Abstract

1364518 Digital transmission; cypher system CIBA-GEIGY AG 24 Aug 1971 [24 Aug 1970 22 July 1971] 39759/71 Heading H4P In a system for cyphering messages particularly where access is required by more than two participants, short access time is reconciled with long transit time by changing the transit time from a larger to a smaller value periodically in dependence on the cypher code; the transit time thus fluctuates between defined limits. The apparatus comprises a plurality of shift registers which derive a code pulse sequence from a long period sequence and a cypher code, the shift registers being interconnected by logic circuits so that the binary value of each code pulse is defined by the value of control pulses supplied earlier, each cypher pulse remaining unaffected by that part of the control pulse which occurs before the affected code pulse during the transit time, which is changed at determined intervals from a larger to a smaller value. A simple arrangement comprises two parallel sub code generators each having a controllable feedback path, e.g. 8<SP>1</SP> having a control sequence v passing in parallel through a modulo-2-mixer 47<SP>1</SP> to conductor 121. A separate 2 stage binary step down element 114<SP>1</SP> issuing data flow instructions in conjunction with AND gates 75<SP>1</SP> cause intermittent code circulation of data in shift registers 11a<SP>1</SP>, 11b<SP>1</SP>. While data flow through generator 126<SP>1</SP> is continuous, in 126<SP>11</SP> the data flow is gated by AND gates 76<SP>11</SP> alternately through shift registers 11a<SP>11</SP>, 11b<SP>11</SP>. Data flow passes through mod-2 mixers 140<SP>1</SP>, 131<SP>1</SP> and 129 to AND gate 99 in which only every nth bit is selected by slow timing source (TB) (not shown) and used. The feedback paths 8<SP>1</SP>, 8<SP>11</SP> are switched by the second inputs, i.e. 43<SP>1</SP>, 43<SP>11</SP> of AND gates 83<SP>1</SP>, 83<SP>11</SP>. Switch on time is substantially larger than the switch off time which is only long enough for incoming data to occupy store positions. A feedback path8*, controllable manually by switch 125, may be incorporated, which is also controlled by the 43* input which is interrupted at the same time as both 126<SP>1</SP>, 126<SP>11</SP> which prevent the cypher routine originating at a time position in which only feed forward is effected. The shift registers may be of different length and preferably all different prime numbers; an example specified may have 137, 211, 157, 223 stages respectively. Data flows from constantly differing time zones are combined with each other by the different lengths of the shift registers. A number of other arrangements are described in the Specification.