GB1358438A - Process for the manufacture of a semiconductor component or an integrated semiconductor circuit - Google Patents

Process for the manufacture of a semiconductor component or an integrated semiconductor circuit

Info

Publication number
GB1358438A
GB1358438A GB5585371A GB5585371A GB1358438A GB 1358438 A GB1358438 A GB 1358438A GB 5585371 A GB5585371 A GB 5585371A GB 5585371 A GB5585371 A GB 5585371A GB 1358438 A GB1358438 A GB 1358438A
Authority
GB
United Kingdom
Prior art keywords
semi
conductor
layer
mask
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5585371A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1358438A publication Critical patent/GB1358438A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1358438 Semi-conductor devices SIEMENS AG 1 Dec 1971 [1 Dec 1970] 55853/71 Heading H1K A semi-conductor layer 12 is deposited directly on an insulating substrate 2 only where it is required for a finished component or integrated circuit. The rest of the substrate surface is masked so that whereas the layer 12 deposits as monocrystalline material the semi-conductor material 13 depositing on the mask is polycrystalline and porous, allowing the mask to be subsequently removed, together with the polycrystalline material 13, by etching. The mask may be of SiO 2 , Si 3 N 4 or metal, the latter being useful in facilitating heating of the substrate by absorption of radiation when the semi-conductor material 12, 13 is to be deposited by high vacuum vaporization. In the form shown the mask comprises a layer 8 of SiO 2 overlying a layer 7 of Si 3 N 4 , the latter being retained flush with the semi-conductor material 12 in the finished structure. Other methods of depositing the semiconductor material 12, 13 are cathode sputtering and deposition from a gaseous semi-conductor compound. The semi-conductor 12, 13 may be Si, Ge or GaAs, the substrate 2 being magnesium oxide, beryllium oxide, spinel or sapphire.
GB5585371A 1970-12-01 1971-12-01 Process for the manufacture of a semiconductor component or an integrated semiconductor circuit Expired GB1358438A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702059116 DE2059116C3 (en) 1970-12-01 1970-12-01 Method for manufacturing a semiconductor component

Publications (1)

Publication Number Publication Date
GB1358438A true GB1358438A (en) 1974-07-03

Family

ID=5789659

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5585371A Expired GB1358438A (en) 1970-12-01 1971-12-01 Process for the manufacture of a semiconductor component or an integrated semiconductor circuit

Country Status (7)

Country Link
BE (1) BE775973A (en)
DE (1) DE2059116C3 (en)
FR (1) FR2116424A1 (en)
GB (1) GB1358438A (en)
IT (1) IT941388B (en)
LU (1) LU64363A1 (en)
NL (1) NL7115760A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2522695A1 (en) * 1982-01-12 1983-09-09 Rca Corp PROCESS FOR DRAWING MONOCRYSTALLINE SILICON ON A MASK-FORMING LAYER
US4482422A (en) * 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
GB2142185A (en) * 1983-06-22 1985-01-09 Rca Corp Mosfet fabrication method
US4549926A (en) * 1982-01-12 1985-10-29 Rca Corporation Method for growing monocrystalline silicon on a mask layer
US4578142A (en) * 1984-05-10 1986-03-25 Rca Corporation Method for growing monocrystalline silicon through mask layer
US4704186A (en) * 1986-02-19 1987-11-03 Rca Corporation Recessed oxide method for making a silicon-on-insulator substrate
GB2228617A (en) * 1989-02-27 1990-08-29 Philips Electronic Associated A method of manufacturing a semiconductor device having a mesa structure
US5273616A (en) * 1980-04-10 1993-12-28 Massachusetts Institute Of Technology Method of producing sheets of crystalline material and devices made therefrom
US5441012A (en) * 1990-09-21 1995-08-15 Anelva Corporation Thin film deposition method for wafer
US5690736A (en) * 1987-08-24 1997-11-25 Canon Kabushiki Kaisha Method of forming crystal

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2284981A1 (en) * 1974-09-10 1976-04-09 Radiotechnique Compelec PROCESS FOR OBTAINING AN INTEGRATED SEMICONDUCTOR CIRCUIT

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273616A (en) * 1980-04-10 1993-12-28 Massachusetts Institute Of Technology Method of producing sheets of crystalline material and devices made therefrom
FR2522695A1 (en) * 1982-01-12 1983-09-09 Rca Corp PROCESS FOR DRAWING MONOCRYSTALLINE SILICON ON A MASK-FORMING LAYER
US4549926A (en) * 1982-01-12 1985-10-29 Rca Corporation Method for growing monocrystalline silicon on a mask layer
US4482422A (en) * 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
GB2142185A (en) * 1983-06-22 1985-01-09 Rca Corp Mosfet fabrication method
US4578142A (en) * 1984-05-10 1986-03-25 Rca Corporation Method for growing monocrystalline silicon through mask layer
US4704186A (en) * 1986-02-19 1987-11-03 Rca Corporation Recessed oxide method for making a silicon-on-insulator substrate
US5690736A (en) * 1987-08-24 1997-11-25 Canon Kabushiki Kaisha Method of forming crystal
GB2228617A (en) * 1989-02-27 1990-08-29 Philips Electronic Associated A method of manufacturing a semiconductor device having a mesa structure
US5441012A (en) * 1990-09-21 1995-08-15 Anelva Corporation Thin film deposition method for wafer

Also Published As

Publication number Publication date
FR2116424A1 (en) 1972-07-13
BE775973A (en) 1972-03-16
IT941388B (en) 1973-03-01
DE2059116B2 (en) 1974-04-25
DE2059116A1 (en) 1972-07-06
DE2059116C3 (en) 1974-11-21
NL7115760A (en) 1972-06-05
LU64363A1 (en) 1972-06-19

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees