GB1354231A - Electronically controlled time-keeping device - Google Patents

Abstract

1354231 Electronic timepieces SEIKOSHA KK 17 March 1972 [20 March 1971] 12638/72 Heading G3T An electronic timepiece includes a timing pulse generator, logic circuit frequency dividers and counters and electrically activated digital time display. Fig. 1 illustrates a 12 hour cycle timepiece wherein the timing pulse generator 1b (which also incorporates a 1/n frequency divider and decoder) produces a timing pulse every time it receives a pulse from a time standard pulse generator 1a, one of which timing pulses is produced at outputs a 1 ----- an in turn. Shift registers 2, 3, 4, 5 memorize the timing pulses, each register having "n" bits of memory equal to the number of outputs of the generator 1b. Each pulse, e.g. the n<SP>th</SP>, (n + 1)<SP>th</SP> &c., from pulse generator 1b operates to shift the memory content of the shift registers 2, 3, 4, 5 to the right by one position. Halfadders 6, 7, 8, 9 count time by respectively adding the counting time signal output of each register respectively to an output signal from an OR gate 17 to produce an adding time signal. A carry register 10 memorizes temporarily a carry signal produced at an output 9d of halfadder 9 and supplies a carry signal to the halfadders when the next counting time signal is produced by the registers. A carry controller 11, operated by the outputs of the registers, controls the carry of each digit place of the time indication and produces an output comprising a carry signal stored in carry register 10 and a signal from timing pulse generator 1b. Outputs of the shift registers 2, 3, 4, 5, when decoded, cause selective illumination of display elements in a display 23. Time setting can be effected by operation of a select switch 29 which selects any terminal a 1 a 2 --- a n of the generator 1b whereby any digit of time can be reset to zero upon closure of a reset switch 26. To advance the time indication of a digit selected e. g. that corresponding to a 1 , a switch 28 is closed and an output logic "1" signal is produced and memorized in time advance circuit 27. The output of 27 is fed to input 6b of half-adder 6 where it is added to the output of shift register 2 and a time advance is achieved. An initial error preventive circuit 12 is provided to prevent errors due to spurious signals or 'noise' from a power supply source to which the timepiece may be connected and which is signified by a counting time signal from the registers of too high a value. Upon this occurrence the circuit 12 resets the registers. A 24-hour cycle timepiece is described with reference to Figs. 2A, 2B (not shown). It is stated that with two more memory bits in the shift registers the date and day may be indicated, in addition to the ten places (digits) of the time indication with the circuits described, the first place of which is units digit of the millisecond and the last the tens digit of the hours. The timepiece may also be used as a stopwatch.