GB1341025A - Data transmission over mains supplies - Google Patents

Abstract

1341025 Signalling over power circuits ENGLISH ELECTRIC CO Ltd 12 Nov 1971 [17 Nov 1970] 54700/70 Heading G4H [Also in Divisions H3-H5] In a system of signalling over power circuits by reducing the amplitude of selected half cycles of a given polarity of the supply waveform, a receiver for the signals compares each half cycle of the given polarity with the preceding half cycle and produces pulses of normal amplitude, reduced amplitude, or increased amplitude dependent on whether the current half cycle is equal to, of lesser amplitude, or of greater amplitude than the previous half cycle of that polarity. A detector then produces an output only when a reduced amplitude pulse is followed immediately by an increased amplitude pulse. Preferably the reduction of half cycle amplitude is carried out on a predetermined sequence of half cycles to call up a particular receiver and each receiver includes a pulse counting circuit producing a characteristic sequence of pulses which is compared with the incoming sequence to determine if a match exists. As described the power supply waveform is applied to terminal 15, Fig. 2, so that the positive peaks charge up capacitor C1 which slowly discharges through R1 so that each positive peak of normal amplitude results in a pulse of current of uniform amplitude flowing into capacitor C1 while a half cycle of reduced amplitude will result in little or no current flow and a succeeding half cycle of normal amplitude will cause a current pulse of double amplitude. The resulting voltage across R1 is differentiated and applied to transistor T1, which provides a signal on P1 having a pulse at the peak of every half cycle of normal or increased amplitude, and also to transistor T2 which is biased so that its output P2 comprises a pulse only on the first normal amplitude half cycle after a reduced amplitude half cycle, i.e. during the double amplitude charging pulse. An overall receiver is described with respect to the logic circuit of Fig. 4 in which block 21 represents the circuit of Fig. 2. The bi-stables Q1 and Q2 are set by the output P1 and P2 respectively of circuit 21 and reset by a timing pulse derived from the incoming waveform by K1. S1 is normally permanently set until a pulse P1 is missed, due to the occurrence of a reduced amplitude half cycle of the power waveform, allowing a clock pulse through the "and" gate to reset bi-stable S1. S1<SP>1</SP> output gates through the succeeding Q2 pulse, following the reduced amplitude half cycle, to an "exclusive-or" gate 40. If a pulse is not present on the output of gate 37 of a sequence generator the pulse from gate 22 passes through at a time determined by "and" gates 41 and 42, to reset the sequence generator counter A1-A6. Counter A subsequently counts up the clock pulses, fed through gate 43, to cause the generation of a predetermined sequence of pulses at the "or" gate 37. Only if the sequence received from the line is identical with that generated by the counter, A1-A6, will the counter complete its count without being reset, so as to generate an output on terminal A6. The interconnections between the gates 25 to 28 and 33 to 36 are adjustable to provide for generation of different sequence and in addition the connection can be adjusted after recognition of a transmitted sequences so that repetitions of the sequence will not cause a further operation but a different predetermined sequence will cause a further operation, e.g. to allow switching on and switching off of apparatus by the receiver.