GB1293964A - Improvements in and relating to digital data processing apparatus - Google Patents

Abstract

1293964 Data processing MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 2 Feb 1970 [31 Jan 1969 (2) 3 March 1969] 4949/7 0 Heading G4A A digital data processor, in response to entry of a first digit, successively sets binary data into digit positions of an auxiliary register from low order to high order so that an entry mark is set into a digit position of the auxiliary register, the binary data being obtained by successive subtraction from the contents of a decimal point position store, an input register being left-shifted for each entry before the decimal point, and the entry mark being right shifted for each entry after the decimal point. A 188-bit shift register 1 and a 4-bit shift register 4, normally forming a recirculation loop via gates 2, 5, hold 3 registers, each holding 16 binary-coded decimal digits, the registers being interleaved at decimal digit level, the first register being the auxiliary register, the second being the input register and the third being an accumulator register. The least significant digit of the second and third registers hold their respective signs. Digit keys on a keyboard 8 are used to enter the decimal point position as a digit into the least significant digit position of the auxiliary register. Subsequently, on entry of the first data digit on the keyboard, the decimal point position digit is copied from the auxiliary register via gate 29 into a recirculating loop consisting of a 4-bit shift register 31 and a full adder 33. This copy is decremented by one repeatedly (by adding 1111 with the carry feedback from 1-bit delay 36 inhibited at 37), the results being stored in respective positions of the auxiliary register. Thus, if the decimal point position digit in the least significant digit position was 0011, the auxiliary register finally holds (starting at low order: 0011, 0010, 0001, 0000, 1111, 1110 &c. The 1111 is the entry mark. Each data digit from the keyboard is entered, via code converter 18 and serializing gates 23-26, into the position of the input register corresponding to the 1111 in the auxiliary register (since the 1111 is the only position contents in the auxiliary register which does not reset a flip-flop 42 via a gate 43). The input register is left-shifted for each data digit entry before a decimal point key is pressed, by passing each digit in the register via gate 29 into the loop consisting of shift register 31 and adder 33 and retaining it there until the next digit position and then reinserting it in the main loop 1, 4 (via gate 40). After the decimal point key is pressed, each digit entry causes the entry mark 1111 to be right-shifted by one position, this being done by decrementing each digit (except the least significant) in the auxiliary register by one (done like the decrementing above). The auxiliary register is also used as a multiplierquotient register, and the input register is also used as an addend-subtrahend-multiplicanddivisor register. The most significant digit of the third (accumulator) register is used as an extension register in multiplication and division. The input register is also used as an output register (see below). Display.-The second to fifteenth digit positions, inclusive, of the input (output) register are displayed on respective Nixie tubes. Clock pulses count up a first 4-bit binary counter, and when its count equals that of a second such counter, a decimal digit of the input register is passed from the output of shift register 1 to a 4-bit output shift register from which it is decoded to select a cathode in that one of the tubes the anode of which is enabled by the decoded output of the second counter, which is decremented on each count equality (see above). Zero-suppression in the display is achieved by cutting-off the power supply to the tubes until a non-zero digit appears in the output shift -register (suppression of high-order zeros) and then again after the 0000, (which adjoins the entry mark 1111) in the auxiliary register is detected in the shift register 4 at a time of counter equality (suppression of low-order zeros).