GB1266726A - - Google Patents

Abstract

1,266,726. Automatic exchange systems. SIEMENS A.G. 22 Aug., 1969 [23 Aug., 1968], No. 41887/69. Addition to 1,200,281. Heading H4K. The path finding arrangement of the multisection, folded switching network of the parent Specification is modified by connecting the path finding wires corresponding to intersection links to one only of the two sections to which they pertain. By then modifying the path finding procedure somewhat and at the expense of an increase in the control circuit logic a reduction in the number of gates required in the path finder is effected. The path finder comprises sections KT1 ... KTs corresponding exactly to the sections of the switching network. In each section marking junctions VA, OR gates G and OR gates MG correspond to A, B and C multiswitches respectively. The break contacts indicated in the link-simulating guide-wires pertain to the link free/busy relays. Each inter-section link is represented by an AND gate KS together with an associated free/busy indicating break contact. These gates are connected via jumper frame W to the C-outlets viz. an OR gate MG corresponding to one end of the links which they represent. The control logic (not shown) can determine from the identities of the two sections involved in a call which section has its simulating outlets connected to the AND gates KS. (During path finding the availability of paths through the other section is then determined first). The determination can be made according to the wiring rules for the frame. For example if the rank numbers of the two sections are both even or both odd then the section having its simulated outlets associated with KS<SP>1</SP> gates is the lowest numbered whereas if one section is odd and the other even then it will be the highest numbered. This rule may of course be reversed. Alternatively if twice the difference of the rank numbers of the two involved sections is greater or less than the total number of sections then it would be the higher or lower numbered section respectively. Again this rule may be reversed. In order to set up a connection between a "calling" inlet to the first A switch in KT1 and a " cabled " inlet to the last A switch in KTs, in phase 1, a marking is applied to a lead wm1 which is connected to the called inlet's switch marking junction VAml as well as to corresponding junctions in other sections. It is assumed here that the central logic has determined which section has its simulated outlets associated with gates KS and that in this case it is the section containing the calling inlet. The sections are distinguished by applying another marking to a called section marking lead wm 2. Consequently, depending on the availability of links in section KTs, one or more leads MS are marked and these markings are stored in stores SP which each correspond to all those inter-section links which connect C switches of a given rank in one section with C switches of a similar rank in another section. Thereafter, in phase 2, the wm2 marking is removed and a wm1 marking corresponding to the calling inlet is applied. The gates KG are not now activated but thanks to selective markings on leads wm3 those gates KS which correspond to links between the two sections involved are opened provided they are reached by the wm1 marking extended through the section KT1 simulator. The test circuits P already contain (from phase 1) a record of the free and accessible outlets from the section KTs so that with the additional data regarding free links thereto from section KT1, some of leads AL will be marked. Central logic then selects one link, the identity of which together with those of the calling and called inlets is sufficient to uniquely determine a path through the (startype) network.