GB1265645A - - Google Patents

Abstract

1,265,645. Associative stores. INTERNATIONAL BUSINESS MACHINES CORP. 12 Feb., 1970, No. 6742/70. Heading G4C. An associative data storage system comprises two storage arrays, for holding the same information, and is such that on detection of a hard operating error in either array, one store section of the bad array is functionally isolated from the remainder of the array, the contents of the corresponding section of the other array are copied into a spare section of the bad array and the operating cycle in which the error was detected is repeated up to a predetermined number of times, then if the error still persists, the isolated store section is reconnected, a different store section is isolated, and so on as above until an error is not detected or all the store sections of the bad array have successively been isolated with error still persisting, operation of the system being stopped in the latter case. The error detection is by comparing the information read from the two arrays into their respective input/output registers. This information specifies the data to be used in the next store access and the operation to be performed, and a back-up register is connected to these two registers to permit repetition of the operation in the event of error. A chain of selector (match) triggers, connected as a shift register, is provided for each section of each array. The chains for the store sections of a given array are connected in series, except that if the section is to be isolated its chain is by-passed. This bypassing, isolation of the store section bit lines from the input/output register for the array, and power supply to the section, are controlled by a 2-bit configuration register, of which there is one per section of each array. The configuration register specifies its section as being " in use," " spare," "temporarily isolated" or " failed." The configuration registers for a given array are connected to form a single recirculating shift register. The diagnostic procedure for dealing with transient errors, and identifying the bad array in the event of hard errors, may be as in Specification 1,265,015 which is referred to. Transfer from a section of one array to a section of the other is via the two input/output registers, and uses NEXT, READ and NEXT, WRITE operations, using shift in the chains of selector triggers. A second system, identical to that above, may be provided to be loaded from the good array if the error in-the bad array still persists after all the store sections have been substituted for as above.