GB1177300A - Pulse Sequence Generator - Google Patents

Abstract

1,177,300. Pseudo random number generators. INTERNATIONAL BUSINESS MACHINES CORP. 25 Jan., 1968 [25 Jan., 1967], No. 3911/68. Heading G4D. A quasi-random sequence of binary pulses, for use in a ciphered data transmission system, comprises a feed-back shift register generator, the output of which is occasionally inhibited by a selector unit. The selector unit may comprise a circuit responsive to particular, and if required varying, sequences of bits at the register output, or may comprise a feed-back shift register. In Fig. 5b, f.b. register R generates a quasirandom sequence of bits under control of shift pulses from OR gate 49. Shift register 31 passes the bits to gate 38. If the bit sequence 10 appears in register 31 units 32, 33, 37 inhibit gate 38. They also trigger a circuit comprising gate 39 and counter 40 so that three shift pulses at four times the frequency of the shift pulses normally fed to registers R and 31 via divider 47 are applied to the registers. Gate 38 is enabled by the pulses from divider 47. Consequently the sequence 10 and the next bit are not passed on by gate 38, the gate giving an unbroken bit stream. The sequences to which units 32, 33 respond may be changed after each response, and the number of high speed shift pulses may also be varied. In a second embodiment, Fig. 6a (not shown), two f.b. registers (P, G) are fed in parallel with shift pulses, their outputs being combined in an output AND gate (50). Whenever an O-bit appears at the output of one of the registers (P) both registers are fed with an extra shift pulse. In a third embodiment, Fig. 7a, the outputs of f.b. registers G0, G1 are alternatively gated to the output OR gate 56 under the control of f.b. register P. Thus, when P outputs a 1, register G1 is shifted and feeds a pulse to gate 56; when P outputs a 0 register G0 is shifted and feeds gate 56. In a further embodiment, Fig. 8a (not shown), four f.b. registers (R1-R4) are fed in parallel with shift pulses. One pair of registers (R1, R2) feeds a first AND gate (60) which feeds an output OR gate (62), and the other pair (R3, R4) feeds a second and gate (61) connected to the OR gate.