GB1120428A - Improvements in data processing systems - Google Patents

Abstract

1,120,428. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORP. 1 Nov., 1965 [23 Dec., 1964], No. 46112/65. Heading G4A. In an electronic digital data processing system having sequences of basic operations defined by a stored micro-programme, in a sequence control unit 3, Fig. 1, the general purpose erasible store is used interchangeably with the unit 3 to control the subset decoder 4 to produce a sequence of scan, compare and address branching micro-operations for effectively testing the system under the control of the main programme which contains test words. The system uses programmed " mask " words whereby parallel groups of signals may be tested one bit at a time under the control of the programme without the use of circuit hardware for selecting the individual bits. The general purpose store 1 comprises a magnetic core matrix (60), Fig. 2 (not shown); address register (61); in/out buffer (62); instruction address register (87) and increment adder (89). The microprogramme sequence control unit 3 comprises a read-only capacitor store matrix (120), Fig. 5 (not shown), having an address selector matrix (129) address register (121) and output buffer register 124. In operation, a supervisory switch 16 is manually or automatically actuated to sequentially control the system according to the permanent sequence mode (PSM) or the supervisory test mode (STM). In (PSM) the micro-order group of decoders 4, is controlled through a group of input lines 13 from the sequence control unit 3, to produce selected signals on exclusive ones of single output lines OP 0-15 of a test subset decoder 10 or on normal groups of control lines OPj, k, l. m, n, p, of the remaining decoders. In (STM) the test subset decoder 10 is controlled by four binary bits on a group of lines 12 from the general purpose erasible store 1 to produce the control outputs on lines OP 0-15 . The test procedure involves the use of programmed binary 36 bit " mask " words each containing a selectively placed zero bit in a field which is otherwise all ones. A programme loading procedure is described whereby such words, which may contain incorrect parity bits, may be written into the erasible store. The 36 bit output from the storage data register (including four binary check bits) is supplied to a test circuit 15 having a pass/ fail output indication 19 which determines whether the system proceeds to the next test programme step or is stopped. The programmed mask words in logic OR combination with a corresponding number (32) of bits extracted in stages from the 90 bit words of the microprogramme sequence control unit 3 produce either an all 1's condition or single 0 in a 36- way AND circuit (200), Fig. 5 (not shown), of the test circuit 15. This circuit includes a binary pass/fail trigger (100) which is thereby conditioned exclusively by the scanned information in the bit position selected at the relevant stage of the programme. In a following cycle a further test word corresponding to the expected condition of the logical OR combination is scanned and the binary trigger (100) is again conditioned. With the system operating correctly the binary trigger 100 will be stopped either not at all or twice, thereby indicating a " 0 " or pass condition. With the system operating incorrectly and the OR combination word and test word not being in parity at the relevant bit the binary trigger 100 will be stepped only once indicating a " 1 " or fail condition.