GB1081815A - System for detecting changes in supervisory states of a communication system - Google Patents

System for detecting changes in supervisory states of a communication system

Info

Publication number
GB1081815A
GB1081815A GB41686/64A GB4168664A GB1081815A GB 1081815 A GB1081815 A GB 1081815A GB 41686/64 A GB41686/64 A GB 41686/64A GB 4168664 A GB4168664 A GB 4168664A GB 1081815 A GB1081815 A GB 1081815A
Authority
GB
United Kingdom
Prior art keywords
service
scanner
line
matrix
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB41686/64A
Inventor
Anton Henry Doblmaier
Randall William Downing
Michael Peter Fabisch
John Allen Harr
Harold Frederick May
John Stanley Nowak
Frank Finley Taylor
Werner Ulrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB1081815A publication Critical patent/GB1081815A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
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    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
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    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
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    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
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    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
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    • G—PHYSICS
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    • G06F11/00—Error detection; Error correction; Monitoring
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    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
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    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
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    • G—PHYSICS
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    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
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    • G06F11/16—Error detection or correction of the data by redundancy in hardware
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    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

1,081,815. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Oct. 13, 1964 [Dec. 31, 1963], No. 41686/64. Heading H4K. In a communication system communication paths are scanned in groups, the scan for one group being effected in a single action and the path states being recorded as a multi-bit word with a bit representing the state of each path, the word being compared with the word obtained from the preceding scan and being stored for comparison with the subsequent scan of the same group. The Specification concerns an aspect of the Bell System No. 1 Electronic Switching System and more particularly concerns itself with a description of a line link network scanner and the central process or work functions involved with subscriber service requests. A line load control feature is described which blocks unprivileged subscriber service requests when the switching system is faced with unusually high calling rates. Line scanner.-Although the description relates to a line scanner the same arrangement is employed in the scanning of junctor circuits and trunks and in the scanning of the strategically distributed test points by the master scanner. As seen in Figs. 20 and 21 a scanner comprises an unduplicated ferrod matrix having 64 rows of sixteen elements to monitor the onhook, off-hook conditions of 1024 lines. Control and drive circuitry for the ferrod matrix is provided in duplicate, left and right sections each comprising a control unit, to accept interrogation data from the command bus system 6406 and route the required data to central control by way of the scanner answer bus system 6600, and also comprises an 8 x 8 address matrix. In the normal mode of operation the scanner obtains and sends line states for the sixteen lines monitored by the ferrods of a chosen row of the ferrod matrix. In a test mode of operation no ferrods are interrogated but an on-hook state is signalled on all line state pairs of the scanner answer bus to the central control circuit. Each scanner is enabled by means of a central pulse distributer unipolar output signal preceded by instructions to set up a particular left or right control unit to " 0 " or " 1 " command bus configuration by means of enable and verify units EVL-1, EVL-0, and EVR-1, EVR-0. If the left control unit is to be enabled to respond to data sent on the " 1 " bus of the command system, the circuit EVL-1 is activated to produce an address window pulse to gate the address data on the " 1 " command bus to pulse stretchers 100-16 which serve as dynamic registers for the two 1-8 codes. Presence of a code triggers a 1À4 Ásec. delay circuit 100-24 and produces a start signal to pulse generator 100-18 which, by pulsing leads XAP and YAP, makes the left core matrix susceptible to the 1-8 code markings present on the pulse stretcher outputs CA0-CA15. The output winding on each core is connected in series with the corresponding winding in the right core matrix, with the interrogation windings of one row of the ferrod matrix, and with the primary winding of a transformer ASWT to generate an All Seems Well signal. Bias ensures that all cores in a matrix present low impedance to their output windings unless the matrix is gated over the XAP, YAP, wires. Coincidence of currents produced by the 1-8 codes presented on wires CA0-CA15 produces an output from one core to interrogate the selected row of ferrods. Each column of ferrods has a common output circuit with a transformer in the-set MT0-MT15. The output of an interrogated row being delivered to the scanner answer bus (at the expiry of the 1.4 Ásec. delay from 100-24, in the presence of an All Seems Well signal, and if the address code is checked valid) on the pairs RR00, R00, to RR15, R15. Both buses " 0 " and " 1 " of the answer bus system are employed to send the data. In a test mode, if EVL-0 is active for example, a test signal received on a test wire from the central pulse distributer causes the pulse stretcher circuit 100-16 to give output on lead 100-TA with the result that all the ferrod column output transformers MT0-MT15 are pulsed. All sixteen output pairs to the scanner answer bus are consequently pulsed. Bias failure results in the release of a relay such as 4A in the left core matrix. Released contacts of 4A connects an alternative source of bias but of opposite polarity so as to hold the matrix output windings in an undisturbed low impedance state. The condition of the relay 4A is monitored by the master scanner and its release operates the office audible alarm. A similar relay 5B is held by bias in the right core matrix. Call processing, line load control.-In the repetitive work functions required with scanning sequences the central processor employs combined order programs. While scanning to detect requests for service is continuous, scanning for answers, hang-ups, abandonment and dial pulses and so on, is done on a directed basis with respect to selected lines, trunks and service circuits involved with connections. The onhook to off-hook transition indicative of request for service is established by evaluating the line scanner data from the answer bus in the light of related data in the call stores. Whether a detected request for service is recognized depends on a line load control feature which enables selected groups of subscribers to be given service to the exclusion of all others so as to allow the switching system to proceed with service of a restricted nature rather than break down in the face of unusual high calling rates. Full access to the system is restored when processing capacity matches the current load. The load on the switching network is checked every three minutes and if overloading is in evidence the system is processed with restricted access for the next three minutes. Access is also restricted if a dial tone test program sequence conducted every four seconds discovers that the delay in connecting dial tone exceeds three seconds. Line load control is applied as a pattern stored in the call store where, for sixteen line groups a bit for each group records a " 1 " if all subscribers are given access without discrimination. With overload conditions those groups for which service requests are not to be recognized are recorded with a " 0 " in their bit positions. The exclusion from service may be made intermittent by circulating some " 1 " records over those bit positions recording " 0." Restoration of service to restricted line groups is done cautiously to avoid a surge of service requests, one or more of the restricted groups being readmitted at minute intervals. In response to a processor address to the call store for a set of preceding scan busy-idle conditions, those conditions are returned to a data buffer register together with the address of the next set of lines to be scanned. The identity of the scanner being addressed is held in the F register of the central control circuit of the processor while the result of the current scan is gated to the L register. The contents of buffer register and L register are gated to separate sets of inputs to the Mask and Complement circuit to send over the masked bus to the KA register bits 0-15 indicating requests for service out of the 16 line group, and bits 16-21 giving the address of the next 16 line group to be scanned. The request for service bits are then transferred to the K register and thence to the KB register while the KA register is set up with the load control pattern. By an AND function on the outputs of KA and KB the bits 0-15 record those lines requesting service and entitled in the prevailing circumstances to receive service. Homogeneity circuits detect if the request for service bits are all zero so as to proceed with the scanning sequence or, in the event that the last row of a scanner ferrod matrix has been interrogated, to break the sequence and seek a new work function. If a request for service is recognized a transfer is made to a program for recording the request in the call store. To identify the line or lines involved with the request a detect-firstone circuit generates a five digit number to record in the FR register the line position in its group of sixteen of the first such request, the identity of the scanner and the scanner row completing the identification in a general purpose program action. Further requests for service present in the same scan are similarly processed. Other features of this system are described and claimed in other Specifications of the set 1,081,811 to 1,081,817.
GB41686/64A 1963-12-31 1964-10-13 System for detecting changes in supervisory states of a communication system Expired GB1081815A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33487563A 1963-12-31 1963-12-31

Publications (1)

Publication Number Publication Date
GB1081815A true GB1081815A (en) 1967-09-06

Family

ID=23309246

Family Applications (7)

Application Number Title Priority Date Filing Date
GB41687/64A Expired GB1081816A (en) 1963-12-31 1964-10-13 Data handling system
GB41684/64A Expired GB1081813A (en) 1963-12-31 1964-10-13 Data handling system
GB41686/64A Expired GB1081815A (en) 1963-12-31 1964-10-13 System for detecting changes in supervisory states of a communication system
GB41683/64A Expired GB1081812A (en) 1963-12-31 1964-10-13 Data handling system
GB41685/64A Expired GB1081814A (en) 1963-12-31 1964-10-13 Data handling system
GB41682/64A Expired GB1081811A (en) 1963-12-31 1964-10-13 Data handling system
GB41688/64A Expired GB1081817A (en) 1963-12-31 1964-10-13 Communication switching system

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB41687/64A Expired GB1081816A (en) 1963-12-31 1964-10-13 Data handling system
GB41684/64A Expired GB1081813A (en) 1963-12-31 1964-10-13 Data handling system

Family Applications After (4)

Application Number Title Priority Date Filing Date
GB41683/64A Expired GB1081812A (en) 1963-12-31 1964-10-13 Data handling system
GB41685/64A Expired GB1081814A (en) 1963-12-31 1964-10-13 Data handling system
GB41682/64A Expired GB1081811A (en) 1963-12-31 1964-10-13 Data handling system
GB41688/64A Expired GB1081817A (en) 1963-12-31 1964-10-13 Communication switching system

Country Status (13)

Country Link
US (1) US3570008A (en)
JP (1) JPS514062B1 (en)
AT (7) AT273543B (en)
BE (7) BE654492A (en)
BR (4) BR6463327D0 (en)
CH (7) CH477140A (en)
DE (6) DE1437577B2 (en)
DK (4) DK114415B (en)
FR (7) FR1442298A (en)
GB (7) GB1081816A (en)
IL (7) IL22237A (en)
NL (8) NL6415241A (en)
SE (4) SE334392B (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723975A (en) * 1971-06-28 1973-03-27 Ibm Overdue event detector
US3737870A (en) * 1972-04-24 1973-06-05 Ibm Status switching arrangement
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Publication number Publication date
GB1081811A (en) 1967-09-06
GB1081816A (en) 1967-09-06
CH479993A (en) 1969-10-15
IL22237A (en) 1968-04-25
SE326990B (en) 1970-08-10
IL22240A (en) 1968-04-25
DE1437576A1 (en) 1969-02-27
CH476442A (en) 1969-07-31
BR6463331D0 (en) 1973-06-26
NL6415240A (en) 1965-07-02
DK136878C (en) 1978-05-16
DE1437577A1 (en) 1969-02-20
DK114415B (en) 1969-06-30
BE654494A (en) 1965-04-16
NL6415236A (en) 1965-07-02
SE334392B (en) 1971-04-26
BE654492A (en) 1965-04-16
BE657775A (en) 1965-04-16
AT274057B (en) 1969-09-10
DE1474094B (en) 1971-04-15
FR1442332A (en) 1966-06-17
AT273543B (en) 1969-08-11
NL6415238A (en) 1965-07-02
DK115124B (en) 1969-09-08
FR1426972A (en) 1966-02-04
FR1426973A (en) 1966-02-04
BE654496A (en) 1965-04-16
BR6463330D0 (en) 1973-06-26
GB1081817A (en) 1967-09-06
CH479992A (en) 1969-10-15
US3570008A (en) 1971-03-09
JPS514062B1 (en) 1976-02-07
BR6463327D0 (en) 1973-06-26
IL22242A (en) 1968-04-25
BE654493A (en) 1965-04-16
FR1426971A (en) 1966-02-04
DK136878B (en) 1977-12-05
DE1437577B2 (en) 1971-11-25
FR1446309A (en) 1966-07-22
DE1437576C3 (en) 1972-03-16
SE319926B (en) 1970-01-26
NL6415237A (en) 1965-07-02
AT274056B (en) 1969-09-10
AT271950B (en) 1969-06-25
DE1474096A1 (en) 1970-07-09
AT269518B (en) 1969-03-25
NL6415239A (en) 1965-07-02
GB1081814A (en) 1967-09-06
DE1437576B2 (en) 1971-08-12
IL22239A (en) 1968-04-25
NL137733C (en)
AT271951B (en) 1969-06-25
DK136007B (en) 1977-07-25
DE1474093B2 (en) 1972-09-07
NL6415235A (en) 1965-07-02
BR6463328D0 (en) 1973-06-26
DE1474093A1 (en) 1970-07-09
CH479991A (en) 1969-10-15
GB1081813A (en) 1967-09-06
CH476441A (en) 1969-07-31
GB1081812A (en) 1967-09-06
IL22243A (en) 1968-04-25
CH479990A (en) 1969-10-15
BE654497A (en) 1965-04-16
FR1426970A (en) 1966-02-04
CH477140A (en) 1969-08-15
NL140351B (en) 1973-11-15
IL22241A (en) 1968-04-25
SE312940B (en) 1969-07-28
DE1474095B1 (en) 1970-08-20
DK136007C (en) 1978-01-09
NL6415241A (en) 1965-07-02
FR1442298A (en) 1966-06-17
BE654495A (en) 1965-04-16
IL22238A (en) 1968-04-25
NL145065B (en) 1975-02-17
AT272712B (en) 1969-07-25

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