FR3104354B1 - Method and System for Accessing an Embedded Server - Google Patents

Method and System for Accessing an Embedded Server Download PDF

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Publication number
FR3104354B1
FR3104354B1 FR1914047A FR1914047A FR3104354B1 FR 3104354 B1 FR3104354 B1 FR 3104354B1 FR 1914047 A FR1914047 A FR 1914047A FR 1914047 A FR1914047 A FR 1914047A FR 3104354 B1 FR3104354 B1 FR 3104354B1
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France
Prior art keywords
information data
sets
identified
memory space
accessing
Prior art date
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FR1914047A
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French (fr)
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FR3104354A1 (en
Inventor
Serge Berenger
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Latelec
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Latelec
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Priority to FR1914047A priority Critical patent/FR3104354B1/en
Publication of FR3104354A1 publication Critical patent/FR3104354A1/en
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Publication of FR3104354B1 publication Critical patent/FR3104354B1/en
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/2866Architectures; Arrangements
    • H04L67/30Profiles
    • H04L67/306User profiles
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • H04L67/12Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/50Network services
    • H04L67/56Provisioning of proxy services
    • H04L67/568Storing data temporarily at an intermediate stage, e.g. caching
    • H04L67/5681Pre-fetching or pre-delivering data based on network characteristics

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Information Transfer Between Computers (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L’invention concerne un serveur embarqué (12) comportant une mémoire cache (44) de stockage de données d’informations, une unité de communication (42) configurée pour : communiquer directement avec un réseau global d’informations (14) comportant des ensembles (26, 28, 30, 32, 34) de données d’informations partagés avec des terminaux de communication (16, 18, 20, 22, 24); identifier les ensembles (26, 28, 30, 32) de données d’informations (X1, X2, X3, X4) comportant chacun un identifiant d’accès au serveur embarqué (12); estimer un volume de données d’informations (X1, X2, X3, X4) sur la base d’un temps de transport prédéterminé, pour chaque ensemble (26, 28, 30, 32) de données d’informations identifié, déterminer pour chaque ensemble (26, 28, 30, 32) de données d’informations identifié, un espace mémoire (46, 48, 50, 52) selon le nombre d’ensembles (26, 28, 30, 32) de données d’informations identifiés, selon le volume estimé de données d’informations (X1, X2, X3, X4) et selon l’espace mémoire global de la mémoire cache (44) disponible ; et pour attribuer à chacun des ensembles (26, 28, 30, 32) de données d’informations identifiés l’espace mémoire (46, 48, 50, 52) déterminé. Figure pour l’abrégé : Figure 1An onboard server (12) having a cache memory (44) for storing information data, a communication unit (42) configured to: communicate directly with a global information network (14) comprising sets of (26, 28, 30, 32, 34) information data shared with communication terminals (16, 18, 20, 22, 24); identifying the sets (26, 28, 30, 32) of information data (X1, X2, X3, X4) each comprising an access identifier for the on-board server (12); estimating an information data volume (X1, X2, X3, X4) based on a predetermined transport time, for each identified information data set (26, 28, 30, 32), determining for each identified information data set (26, 28, 30, 32), a memory space (46, 48, 50, 52) according to the number of identified information data sets (26, 28, 30, 32) , according to the estimated volume of information data (X1, X2, X3, X4) and according to the overall memory space of the cache memory (44) available; and to allocate to each of the identified sets (26, 28, 30, 32) of information data the determined memory space (46, 48, 50, 52). Figure for abstract: Figure 1

FR1914047A 2019-12-10 2019-12-10 Method and System for Accessing an Embedded Server Active FR3104354B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1914047A FR3104354B1 (en) 2019-12-10 2019-12-10 Method and System for Accessing an Embedded Server

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1914047A FR3104354B1 (en) 2019-12-10 2019-12-10 Method and System for Accessing an Embedded Server
FR1914047 2019-12-10

Publications (2)

Publication Number Publication Date
FR3104354A1 FR3104354A1 (en) 2021-06-11
FR3104354B1 true FR3104354B1 (en) 2021-12-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR1914047A Active FR3104354B1 (en) 2019-12-10 2019-12-10 Method and System for Accessing an Embedded Server

Country Status (1)

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FR (1) FR3104354B1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6801927B1 (en) * 1999-09-24 2004-10-05 Akamba Corporation Network adaptor card with reverse proxy and cache and method implemented therewith
JP2005339198A (en) * 2004-05-27 2005-12-08 Internatl Business Mach Corp <Ibm> Caching hit ratio estimation system, caching hit ratio estimation method, program therefor, and recording medium therefor
US7945726B2 (en) * 2006-05-08 2011-05-17 Emc Corporation Pre-allocation and hierarchical mapping of data blocks distributed from a first processor to a second processor for use in a file system

Also Published As

Publication number Publication date
FR3104354A1 (en) 2021-06-11

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