FR3060809A1 - METHOD OF ENCRYPTION BY MASSIVELY PARALLEL CALCULATION - Google Patents

Abstract

The encryption system includes a master processor and a plurality of slave processors operating in parallel. The master processor has the message to be encrypted and the encryption key. It divides the message to be encrypted into blocks of useful data. It also generates decoy messages and divides them into decoy data blocks. Similarly, it generates pseudo-random decoy keys. At each time interval, the master processor allocates to each of the slave processors a block of data and a key, at most one of these data blocks being a block of useful data and at most one of these keys being the encryption key. Encryption instructions are performed synchronously by the slave processors so as to make physical correlation attacks (CPA) very difficult.

Description

DESCRIPTION

TECHNICAL AREA

The present invention relates generally to the field of cryptography and more particularly that of encryption methods resistant to physical attacks.

PRIOR STATE OF THE ART

Encryption methods protect data in electronic, computer or telecommunications systems. There are typically two types of cryptographic systems, symmetric systems where the same private key is used for encryption and decryption, and asymmetric systems using a couple of distinct keys, a private key being used for decryption (or signature) and a public key for encryption (or signature verification).

Among the symmetric encryption methods, a distinction is made between block encryption methods and stream encryption methods. In a block encryption method, the message to be encrypted is divided into blocks and these blocks are encrypted independently or chained, generally one after the other. In stream encryption methods, however, the message is continuously encrypted by a stream of key (key streom).

An essential quality criterion of an encryption method is its robustness to cryptanalysis techniques, that is to say to all of the techniques which an attacker can use to find data in clear without having the encryption key.

A distinction is made between classical (or theoretical) cryptanalysis and cryptanalysis by physical attacks. Classical cryptanalysis consists of observing encrypted data and trying to ascend by clear or algebraic analysis to clear data. Physical attacks are all the techniques exploiting the operation of the encryption circuit to go back to the data in clear. Unlike conventional cryptanalysis, physical attacks are not aimed at attacking the encryption algorithm per se but its software or hardware implementation.

Physical attacks can be hardware or software (Trojan horse for example). There are generally two main families of physical physical attacks, namely attacks by observation (or by auxiliary channels) and attacks by injection of faults. Observation or Side Channel Analysis (SCA) attacks are based on observing the circuit while performing encryption calculations. This observation is translated in practice by physical measurements (current consumption, electromagnetic trace, calculation time, etc.). Fault Injection Attack (FIA) attacks exploit the effect of an intentional disturbance on the functioning of the circuit, in particular to bypass protections or reduce the mathematical complexity of decryption.

US Pat. No. 7,500,112 describes an encryption method using at least two processors, namely a CPU and at least one coprocessor, making it possible to protect the cryptographic calculation against attacks by hidden channels and more particularly against an attack by analysis. consumption differential or DPA (Differential Power Analysis). More precisely, while one of the two processors operates on the data useful to encrypt, the other operates on decoy data. The allocation of the useful data to be encrypted and of the decoy data is carried out in a pseudo-random manner between the two processors, and the encrypted stream is reconstituted while keeping only the useful data. It is thus possible to drown the electromagnetic trace and / or the trace of current consumption in the noise produced by the encryption of the decoy data.

This encryption method has good robustness to attacks by DPA but is nevertheless vulnerable to attacks such as CPA (Correlation Power Analysis). The latter allows, thanks to the correlation with a consumption model, to differentiate in the traces of consumption

The aim of the present invention is therefore to propose an encryption system / method which is more robust to attacks by auxiliary channels, and more particularly to CPA attacks, than the encryption systems / methods of the prior art. .

STATEMENT OF THE INVENTION

The present invention is defined by a system for encrypting a message by means of an encryption key, said system comprising a control module and a plurality of identical processors operating in parallel, in which:

- the control module allocates to each time interval and to each processor:

• either a data block of said message, said useful data block, as well as an elementary encryption key obtained from said encryption key, for encrypting said useful data block;

• either a decoy data block of the same size as the useful block as well as a decoy encryption key, for encrypting the decoy data block;

the control module allocating at most one block of useful data and one elementary encryption key per time interval;

the processors are clocked by the same clock and are initialized by the control module at the same instant, the processors executing identical instructions at all times, except for the data and the encryption keys.

Advantageously, the control module divides the message into useful data blocks and generates the decoy data blocks at random, the useful data blocks and the decoy data blocks being transmitted to the processors to which they are allocated.

In addition, the control module generates the elementary encryption keys from the encryption key and generates the decoy encryption keys in a pseudo-random manner, the elementary encryption keys and the decoy encryption keys being transmitted to the processors to which they are allocated. .

According to a first exemplary embodiment, the encryption is carried out by stream of key and that the elementary keys are obtained as consecutive portions of the encryption key.

According to a second exemplary embodiment, the encryption is an AES encryption and that the elementary keys are chained or identical keys.

The encryption system can be implemented in the form of a graphics card or a GP-GPU graphics integrated circuit.

Alternatively, it can be implemented in the form of a network of MPPA type processors.

The invention also relates to a method of encrypting a message using an encryption key, said method using a plurality of identical processors operating in parallel, in which:

- we allocate to each time interval and each processor:

• either a data block of said message, said useful data block, as well as an elementary encryption key obtained from said encryption key, for encrypting said useful data block;

• either a decoy data block of the same size as the useful block as well as a decoy encryption key, for encrypting the decoy data block;

at most one block of useful data and one elementary encryption key being allocated per time interval;

- The processors are clocked by the same clock and the processors are initialized in the same instant, said processors executing identical instructions at all times, except for the data and the encryption keys.

Advantageously, the message is divided into useful data blocks and the decoy data blocks are generated randomly, the useful data blocks and the decoy data blocks being transmitted to the processors to which they are allocated.

In addition, the elementary encryption keys are generated from the encryption key and the decoy encryption keys are generated in a pseudo-random manner, the elementary encryption keys and the decoy encryption keys being transmitted to the processors to which they are allocated.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention will appear on reading a preferred embodiment of the invention, made with reference to the attached figures among which:

Fig. 1 schematically represents the architecture of an encryption system according to an embodiment of the invention;

Fig. 2A schematically represents a first variant timing diagram of the encryption operations performed by the various processors of FIG. 1;

Fig. 2B schematically represents a second variant of timing diagram 10 of the encryption operations performed by the various processors of FIG. 1;

Fig. 3 represents an example of traces of current consumption of two processors of FIG. 1.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

The idea underlying the invention is to use an encryption system comprising a plurality of identical processors. By identical, it is meant that these processors have the same hardware architecture and that the software stored in these processors is identical. All the processors are clocked by a single clock and the cryptographic calculations executed by these processors start at the same instant, so that at

0 at any given time any two processors of said plurality execute the same instruction, with the possible difference near the data to be encrypted and the encryption key to which it relates. However, in a given instant, at most one processor operates on useful data, the other processors operating on decoy data. The fact that the instructions are identical (with the only difference near the encryption key and the

5 data to be encrypted to which these instructions relate) and that these are executed strictly simultaneously makes a CPA attack particularly difficult.

Fig. 1 schematically represents the architecture of an encryption system according to an embodiment of the invention.

This encryption system comprises a control module, 100, denoted MP, for example a master processor.

It further comprises a plurality N (N> 2) of identical processors, 110, denoted Ρυ _χ , ..., Ρϋ _N , acting as slave processors.

These processors can for example be generic processors containing in their ROM memory the same encryption software or programmable logic circuits of FGPA type, programmed to execute the same encryption algorithm, or calculation units present in a GPU (Grophicol Processing Unit ) as explained below.

Each PU _n processor has its own local memory, designated by

MEM _n . In other words, the memories MEM _i of the processors PU _n are not shared. These memories store the data to be encrypted (useful or decoys) and the encryption keys.

The processors PU _X , ..., PU _N are connected by a bus or several buses to the control module 100. They are clocked by the same CLK clock and are initialized by the same sync synchronization signal. This signal can be a physical signal or even a message transmitted by the control module.

The MP control module can be a processor of the same type as the processors PU _X , ..., PU _N or else a specific processor. The role of the control module MP is to transmit the data to be encrypted and the encryption keys to the processors.

0 More specifically, it pseudo-randomly allocates the useful data to one of the processors and decoy data to the other.

It should be noted that this allocation can be carried out dynamically, by time interval. In other words, at each time interval, the control module MP can modify the allocation and load a processor different from the

5 encryption of useful data. According to a particular variant, the control module can, during certain time intervals, allocate to the processors only decoy data and no useful data.

Finally, the control module is responsible for recovering the data encrypted by the processors PU _n η = Ι,.,., Ν, eliminating the decoy data (encrypted) and reconstructing the flow of encrypted useful data. This processing can be carried out at the end of each time interval or else at the end of the encryption process.

Fig. 2A schematically represents a first variant of timing diagram 5 of the encryption operations performed by the various processors of FIG. 1.

We suppose that we have to encrypt a message M _it called useful message, constituted by data to be encrypted (useful data). This message can be divided into successive blocks denoted M _t B _k where k = Ι,.,., Κ is a time index. The useful message is embedded in a plurality N of messages, M _jt j = Ι,.,., Ν, the Nl messages M _jt j ψ i, being made up of decoy data and, for this reason, called decoy messages . The decoy messages, M _jt j Ψί, are also divided into successive blocks, 47, ¾, of the same size as the blocks M _t B _k .

K each time interval k, the control module allocates the data blocks 47, ¾. j = l, ..., N, to the processors PU _n , n = l, ..., N and transmits encryption keys to them to encrypt these blocks respectively, ie Ω ,. .

J

The encryption can be symmetric stream encryption. In this case, the encryption keys Ω _{ι λ} constitute a stream of key Ω, = {Ω _ι1 , Ω _{ι 2} , .., Ω _{ι ΛΓ} }.

Alternatively, the encryption performed by the encryption system can be, for example, symmetric block encryption such as AES encryption. In that case,

0 the encryption keys Ω _ιλ are keys which can all be identical or chained depending on the mode of operation envisaged.

Whatever the type of encryption, the keys Ω _λ jïi are decoy encryption keys, generated for example in a pseudo-random manner by the control module.

According to a variant, the set of keys Ω _{> λ} , j = 1, ..., N, k = i, ..., K may have been stored in the various memories MEM, n = l, ..., N at the initialization of the encryption process.

Similarly, all the blocks Μ F., j = Ι,.,., Ν, k = Ι,.,., Κ, may have been loaded into the memories MEM _n , n = l, ..., N , during the initialization step of the encryption process. In this case, only the message indices j = l, ..., N are then communicated at each time interval to the various processors, each processor using a counter to increment the index k at each time interval.

Whatever the variant envisaged, the control module allocates the data blocks / message indices in a pseudo-random manner, thus increasing the spatial dispersion of the encryption of the useful message M _t .

Hereinafter, CF denotes an encryption operation. Thus, during 10 the time interval k, the processor n having been allocated a data block Μ .B, and

JR an encryption key Ω _λ performs the encryption operation CF (M _j B _k , El _jk ). The instructions carried out by the various processors to carry out this operation during the time interval k are strictly synchronized and differ only in the data MjB _k and the keys Ω _{λ to} which they apply.

Thus, in the example shown in FIG. 2A, the useful data blocks have been shown in white and the decoy data blocks have been shown in gray. The successive blocks of the useful message M _t are encrypted by the processor PU ₃ during the time interval k = l, the processor PU _N during the time interval k = 2, the processor PU ₃ during the interval time k = 3, etc.

0 The control module recovers the encrypted data at the end of each encryption interval or else at the end of the encryption process. The entire encryption process lasts KT where T is the duration of a time interval. The encrypted useful data are extracted from the encrypted data CF (m _} B _k , Ω. _Jk ) to reconstruct the encrypted useful data CF (M _i B _k , Q. _Ik ), k = l, ..., K.

Fig. 2B schematically represents a second variant of the encryption operations performed by the various processors of FIG. 1.

In this variant, unlike the first, the control module does not necessarily allocate to each time interval k a block of the useful message M _t to one of the processors PU _n , n = l, ..., NOT . In other words, if we designate by 47.7 /, k = 1, ..., K the blocks of the useful message M _jt the complete encryption of this message is carried out over a duration

QT> KT. Thus, the blocks of the useful message, M _t B _k , k = Ι,.,., Κ, are distributed in a pseudo-random manner, not only spatially, between the different processors but also temporally between the different time intervals. The allocation, however, respects the order of the blocks and allocates at most one of these blocks per time interval to one of the processors. In other words, if we take the time interval q and the useful message block M _t B _k is the last block to have been allocated, the master processor can either allocate the block M _t B _{k + 1} to one of the processors PU _n , n = 1, ..., N either allocate only blocks of decoy messages to the processors in question.

In the example shown in Fig. 2B, the useful data blocks have been shown in white and the decoy data blocks have been shown in gray.

The processor PU ₂ encrypts the first block of useful data, Μβ ^, during the time interval k = 1. The processors encrypt only blocks of decoy data during the time interval k = 2. The processor PU ₃ encrypts the second block of useful data, Μβ ₂ during the time interval k = 3, etc.

0 Fig. 3 shows an example of traces of the current consumed over time by two processors of FIG. 1. It should be noted that traces of the intensity of electromagnetic radiation from the various processors could be used alternately.

Traces 310 and 320 correspond respectively to the consumption in

5 running during a time interval T of two processors, the trace 310 corresponding to the AES encryption of a useful data block and the trace 320 to the decryption of decoy data.

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We note that these traces are perfectly superimposable on the time axis. The only difference appearing in 330 comes from the fact that the data to be encrypted as well as the encryption keys are different.

In fact, identical instructions (apart from the encryption keys and data) are executed in synchronization by the different processors. These instructions being identical, starting at the same start time and ending at the same end time, we understand that their time traces are almost identical. A correlation between the different traces will therefore not make it possible to discriminate the different calculation steps and therefore to discriminate the consumption induced by the calculation on the sensitive data from the consumption induced by the calculation on the decoy data.

The encryption system can be implemented by means of a graphics card or a graphics integrated circuit, of GP-GPU (General Purpose computing on Graphics Processing Units) type. Such an implementation allows heavy calculations which traditionally were carried out by a CPU to be carried out by a graphics card or a graphic integrated circuit, benefiting from their massively parallel architecture. Several GP-GPU programming libraries are available to execute these calculations while ignoring the underlying graphics primitives, notably the OpenCL language.

The OpenCL language distinguishes the central processor CPU (that is to say the master processor MP in the case of the encryption system described above) and the peripheral processors responsible for intensive calculations (in our case, the processors PU _n , n = 1, ..., N, loaded in encryption operations). The OpenCL language makes it possible to take advantage of the parallel architecture in two forms: SPMD (Single Program Multiple Data) and SIMD (Single Instruction Multiple Dota). The parallelism of the tasks and the instructions guarantees a perfect temporal superposition between the instructions executed by the different processors. More precisely, the different message blocks Μ .B, (useful data or decoy data) are considered to be “work items” grouped in “work-groups”, mapped into processors in the OpenCL language. Each “work-group” performs the same cryptographic operation on data (Μ .B,) and

JK of keys (Ω _{/ Ζ} ) different. This type of implementation also offers the advantage of prohibiting an attacker from accessing the internal memories of the various processors containing sensitive information.

The encryption system according to the present invention can alternatively be implemented using a massively parallel processor network or MPPA (Mossively Parallel Processor Arroy). Such a network is an integrated circuit comprising several hundreds to several thousand processors (or cores) operating in parallel. A dedicated core (group core) or even an external processor plays the role of control module. It has the message M _t useful data and a key Ω, encryption (composed of the keys Ω _{ΐ (} ,). In addition, it generates the N-1 decoy messages M _jt j = l, ..., N , j Fi. It divides the useful message M j = l, ..., N into blocks Λ /, β, and allocates them to different cores over time. The group core sends an interrupt to the different cores to perform a encryption operation. Each core then goes into non-interruptible mode and performs the operation in question on the block and with the key which were previously supplied to it by the group core. Each core signals the end of its calculation and returns to mode The group core can then again send an interrupt to the different cores to launch a new encryption operation.

Claims (10)

1. A system for encrypting a message by means of an encryption key, said system comprising a control module and a plurality of identical processors operating in parallel, characterized in that: - the control module allocates to each time interval and to each processor: • either a data block of said message, said useful data block, as well as an elementary encryption key obtained from said encryption key, for encrypting said useful data block; • either a decoy data block of the same size as the useful block as well as a decoy encryption key, for encrypting the decoy data block; the control module allocating at most one block of useful data and one elementary encryption key per time interval; the processors are clocked by the same clock and are initialized by the control module at the same instant, the processors executing identical instructions at all times, except for the data and the encryption keys. 2. Encryption system according to claim 1, characterized in that the control module divides the message into useful data blocks and generates the decoy data blocks randomly, the useful data blocks and the decoy data blocks being transmitted to the processors to which they are allocated. 3. Encryption system according to claim 1 or 2, characterized in that the control module generates the elementary encryption keys from the encryption key and generates the decoy encryption keys in a pseudo-random manner, the encryption keys elements and the decoy encryption keys being transmitted to the processors to which they are allocated. 4. Encryption system according to claim 3, characterized in that the encryption is carried out by key flow and that the elementary keys are obtained as consecutive portions of the encryption key. 5. Encryption system according to claim 3, characterized in that the encryption is an AES encryption and that the elementary keys are chained or identical keys. 6. Encryption system according to one of the preceding claims, characterized in that it is implemented in the form of a graphics card or a graphics integrated circuit of GP-GPU type. 7. Encryption system according to one of claims 1 to 5, characterized in that it is implemented in the form of a network of MPPA type processors. 8. Method for encrypting a message using an encryption key, said method using a plurality of identical processors operating in parallel, characterized in that: - we allocate to each time interval and each processor: • either a data block of said message, said useful data block, as well as an elementary encryption key obtained from said encryption key, for encrypting said useful data block; • either a decoy data block of the same size as the useful block as well as a decoy encryption key, for encrypting the decoy data block; at most one block of useful data and one elementary encryption key being allocated per time interval; - The processors are clocked by the same clock and the processors are initialized in the same instant, said processors executing identical instructions at all times, except for the data and the encryption keys. 9. Encryption method according to claim 8, characterized in that the message is divided into useful data blocks and the decoy data blocks are generated randomly, the useful data blocks and the decoy data blocks being passed to the processors to which they are allocated. 10. The encryption method according to claim 8 or 9, characterized in that the elementary encryption keys are generated from the encryption key and the decoy encryption keys are generated in a pseudo-random manner, the keys encryption keys and decoy encryption keys being transmitted to processors to which 10 they are allocated. CLK FiÉLl CFÇMîB ^, Qî _N )