FR2968834A1 - Method for making three-dimensional integrated structures, involves thinning substrates of integrated circuits by holding resin layer, and forming electrically conductive through-connection in thinned substrates - Google Patents

Method for making three-dimensional integrated structures, involves thinning substrates of integrated circuits by holding resin layer, and forming electrically conductive through-connection in thinned substrates Download PDF

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Publication number
FR2968834A1
FR2968834A1 FR1060344A FR1060344A FR2968834A1 FR 2968834 A1 FR2968834 A1 FR 2968834A1 FR 1060344 A FR1060344 A FR 1060344A FR 1060344 A FR1060344 A FR 1060344A FR 2968834 A1 FR2968834 A1 FR 2968834A1
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France
Prior art keywords
integrated circuits
integrated
substrates
resin layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR1060344A
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French (fr)
Inventor
Laurent-Luc Chapelon
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Priority to FR1060344A priority Critical patent/FR2968834A1/en
Publication of FR2968834A1 publication Critical patent/FR2968834A1/en
Pending legal-status Critical Current

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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

The method involves assembling a set of integrated circuits (IC1) in a semiconductor wafer of another set of integrated circuit (IC2), and depositing a resin layer (RES) encapsulating the latter set of integrated circuits for filling spaces between the integrated circuits. Substrates of the integrated circuits are thinned by holding the resin layer or the substrate (SUB) of the former set of integrated circuits, and an electrically conductive through-connection is formed in the thinned substrates. The assembly of the integrated circuits is cut to form three-dimensional integrated structures.

Description

B10-4263FR 1 B10-4263EN 1

Procédé de réalisation de structures intégrées tridimensionnelles Method for producing three-dimensional integrated structures

L'invention concerne les circuits intégrés et plus particulièrement les assemblages de deux circuits intégrés réalisés indépendamment, de façon à réaliser des structures tridimensionnelles intégrées. Les structures intégrées tridimensionnelles comprennent généralement au moins deux circuits intégrés fabriqués indépendamment puis liés l'un à l'autre par un ensemble de liaisons électriques disposées entre les deux circuits intégrés. Lors de la fabrication de ces assemblages, des liaisons traversantes électriquement conductrices (connues également sous la dénomination anglo-saxonne TSV : « Through Silicon Via ») peuvent également être réalisées au sein d'au moins l'un des circuits intégrés. Ainsi, lors de la fabrication d'un assemblage de la face avant d'un circuit intégré contre la face arrière d'un autre circuit intégré, dit « face to back », les liaisons traversantes relient électriquement les lignes métalliques du réseau d'interconnexion (« BEOL » : Back End Of Line) d'un circuit intégré et les éléments de connexion électrique disposés entre les deux circuits intégrés, par exemple des piliers de cuivre. Dans le cas d'un assemblage dit « face to face », c'est-à-dire de la face avant d'un circuit intégré contre la face avant d'un autre circuit intégré, les liaisons traversantes permettent de relier le réseau d'interconnexion de l'un des circuits intégrés à sa face arrière en vue d'un couplage électrique avec un circuit imprimé ou un boîtier (packaging), selon un procédé bien connu de l'homme du métier sous le nom de « flip chip ». Afin de réaliser ces liaisons traversantes, les substrats de silicium des circuits intégrés sont généralement amincis. Des étapes de polissage mécanique et mécano chimique sont mises en oeuvre afin d'amincir les substrats d'une épaisseur initiale par exemple de l'ordre de 700 micromètres jusqu'à une épaisseur finale de l'ordre de la centaine de micromètres. De manière classique, lors de la fabrication d'un assemblage dit « face to face », plusieurs circuits intégrés déjà découpés sont assemblés sur plusieurs circuits intégrés réalisés au sein d'une plaque semi conductrice. Afin d'amincir cette plaque semi-conductrice, un substrat formant une poignée de maintien, couramment appelé « carrier » en langue anglaise, est collé sur la face arrière des circuits intégrés découpés. The invention relates to integrated circuits and more particularly to assemblies of two integrated circuits made independently, so as to produce integrated three-dimensional structures. The integrated three-dimensional structures generally comprise at least two integrated circuits manufactured independently and then linked to one another by a set of electrical connections arranged between the two integrated circuits. During the manufacture of these assemblies, electrically conductive through connections (also known by the name TSV: Through Silicon Via) can also be made within at least one of the integrated circuits. Thus, during the manufacture of an assembly of the front face of an integrated circuit against the rear face of another integrated circuit, called "face to back", the through connections electrically connect the metal lines of the interconnection network. ("BEOL": Back End Of Line) of an integrated circuit and the electrical connection elements arranged between the two integrated circuits, for example copper pillars. In the case of a so-called "face to face" assembly, that is to say of the front face of an integrated circuit against the front face of another integrated circuit, the through connections make it possible to connect the network of interconnection of one of the integrated circuits to its rear face for electrical coupling with a printed circuit or a package (packaging), according to a method well known to those skilled in the art under the name of "flip chip" . In order to achieve these through connections, the silicon substrates of the integrated circuits are generally thinned. Mechanical and mechano-chemical polishing steps are implemented in order to thin the substrates with an initial thickness, for example of the order of 700 microns to a final thickness of the order of one hundred micrometers. Conventionally, during the manufacture of a so-called "face to face" assembly, several integrated circuits already cut are assembled on several integrated circuits made within a semiconductor plate. In order to thin this semiconductor plate, a substrate forming a holding handle, commonly called "carrier" in English, is stuck on the rear face of the integrated circuits cut.

Un assemblage classique utilisant un substrat formant une poignée de maintien a été représenté sur la figure 1. Sur cette figure, on a représenté de manière schématique un assemblage de deux premiers circuits intégrés IC1 d'une plaque semi conductrice, sur la face avant desquels des circuits intégrés IC2 ont été assemblés. Des composants, par exemple des transistors TR ont été réalisés au sein des substrats des circuits intégrés IC1 et IC2. Un réseau d'interconnexion entre les composants des circuits intégrés communément désigné sous le vocable anglo-saxon « Back End Of Line » (« BEOL ») a été réalisé entre les composants des circuits intégrés. Ce réseau comprend de manière classique des lignes métalliques LM et ainsi qu'un ensemble de liaisons traversantes (ou vias). A conventional assembly using a substrate forming a holding handle has been shown in FIG. 1. This figure schematically shows an assembly of two first integrated circuits IC1 of a semiconductor plate, on the front face of which IC2 integrated circuits have been assembled. Components, for example transistors TR have been made within the substrates of IC1 and IC2 integrated circuits. An interconnection network between the components of the integrated circuits commonly referred to as the "Back End Of Line" ("BEOL") has been made between the components of the integrated circuits. This network conventionally comprises LM metal lines and a set of through connections (or vias).

Des éléments de connexion électrique entre les circuits intégrés IC1 et IC2 comprennent de manière classique des piliers de cuivre PCU soudés au moyen d'un alliage à basse température de fusion SAC. Les piliers de cuivres PCU sont obtenus au moyen d'un dépôt électrochimique sur une couche d'accroche et barrière UBM. Cette couche UBM forme l'ensemble appelé par l'homme du métier en langue anglaise « Under Bump Metallisation ». Une première couche de résine WLUF est ensuite déposée sur les circuits IC2 avant leur singularisation et leur assemblage avec les circuits intégrés ICI. Cette couche de résine est couramment désignée sous le vocable anglo-saxon de « Wafer Level Under-Fill ». Afin de combler les espaces latéraux entre les circuits intégrés IC2 après leur assemblage avec les circuits intégrés ICl, une couche de résine RES est déposée de manière à encapsuler les circuits intégrés IC2. Une couche de colle CO est ensuite déposée sur la résine RES et les circuits intégrés IC2 après une étape d'aplanissement de la résine RES afin de coller un substrat formant une poignée de maintien PM. Le substrat des circuits intégrés ICl est aminci de manière à pouvoir former des liaisons traversantes TSV débouchant sur la face arrière des circuits intégrés ICl. Les liaisons traversantes TSV relient électriquement des lignes métalliques LM à des piliers de cuivres PCU2 apte à raccorder les assemblages de circuits intégrés à des circuits imprimés ou à des boîtiers (packaging), par exemple lors d'assemblages « flip chip ». Le collage du substrat formant une poignée de maintien présente notamment pour inconvénient de rajouter un certain nombre d'étapes lors de la fabrication des assemblages de circuits intégrés. En outre, au dessus d'une température de l'ordre de 200°C, la couche de colle CO ne solidarise plus la poignée de maintien à l'assemblage. Les dépôts des différentes couches nécessaires par exemple à la fabrication des liaisons traversantes, normalement réalisés sous des températures de l'ordre de 400°C, ne sont donc pas réalisés dans des conditions favorables (puisque la température est de 200°C seulement) et peuvent donc présenter des problèmes de continuité et de conformité. Electrical connection elements between the IC1 and IC2 integrated circuits conventionally comprise PCU copper abutments welded using a low melting alloy SAC. The PCU brass pillars are obtained by means of an electrochemical deposit on a UBM bonding layer and barrier. This UBM layer forms the assembly called by the skilled person in the English language "Under Bump Metallization". A first layer of WLUF resin is then deposited on the circuits IC2 before their singularization and their assembly with ICI integrated circuits. This layer of resin is commonly referred to as the Anglo-Saxon "Wafer Level Under-Fill". In order to fill the lateral spaces between the integrated circuits IC2 after their assembly with the integrated circuits IC1, a resin layer RES is deposited so as to encapsulate the integrated circuits IC2. A CO adhesive layer is then deposited on the resin RES and the integrated circuits IC2 after a step of flattening the resin RES to bond a substrate forming a holding handle PM. The integrated circuits IC1 substrate is thinned so as to form through connections TSV opening on the rear face of ICl integrated circuits. The TSV through-links electrically connect LM metal lines to PCU2 brass pillars suitable for connecting the integrated circuit assemblies to printed circuits or to housings (packaging), for example during "flip chip" assemblies. The bonding of the substrate forming a holding handle has the disadvantage of adding a number of steps during the manufacture of assemblies of integrated circuits. In addition, above a temperature of the order of 200 ° C, the CO adhesive layer no longer solidifies the holding handle assembly. The deposits of the various layers necessary, for example for the production of through-connections, normally produced at temperatures of the order of 400.degree. C., are therefore not produced under favorable conditions (since the temperature is only 200.degree. C.) and therefore may have continuity and compliance issues.

Selon un mode de mise en oeuvre, il est proposé de simplifier la réalisation de structures intégrées tridimensionnelles. Selon un aspect, il est proposé un procédé de réalisation de structures intégrées tridimensionnelles comprenant : a) un assemblage sur plusieurs premiers circuits intégrés réalisés au sein d'une plaque semi-conductrice de plusieurs deuxièmes circuits intégrés ; b) un dépôt d'une couche de résine encapsulant les deuxièmes circuits intégrés et comblant les espaces latéraux entre les deuxièmes circuits intégrés ; c) un amincissement des substrats des premiers ou des deuxièmes circuits intégrés en utilisant comme poignée de maintien la couche de résine ou le substrat des premiers circuits intégrés ; d) une réalisation d'au moins une liaison traversante électriquement conductrice dans le substrat de chaque circuit intégré aminci ; et e) une découpe des assemblages des premiers et deuxièmes circuits intégrés de manière à former les structures intégrées tridimensionnelles. Ainsi, en utilisant comme poignée de maintien la couche de résine ou le substrat des premiers circuits intégrés, il n'est pas nécessaire de coller un substrat supplémentaire formant une poignée de maintien. According to one embodiment, it is proposed to simplify the production of three-dimensional integrated structures. In one aspect, there is provided a method for producing three-dimensional integrated structures comprising: a) an assembly on a plurality of first integrated circuits formed within a semiconductor plate of a plurality of second integrated circuits; b) a deposit of a resin layer encapsulating the second integrated circuits and filling the lateral spaces between the second integrated circuits; c) a thinning of the substrates of the first or second integrated circuits using as a holding handle the resin layer or the substrate of the first integrated circuits; d) an embodiment of at least one electrically conductive through connection in the substrate of each thinned integrated circuit; and e) cutting the assemblies of the first and second integrated circuits so as to form the integrated three-dimensional structures. Thus, by using as a holding handle the resin layer or the substrate of the first integrated circuits, it is not necessary to bond an additional substrate forming a holding handle.

On peut amincir le substrat des premiers circuits intégrés en utilisant comme poignée de maintien la couche de résine. En variante, on peut amincir le substrat des deuxièmes circuits intégrés en utilisant comme poignée de maintien le substrat des premiers circuits intégrés. The substrate of the first integrated circuits can be thinned by using the resin layer as a holding handle. As a variant, the second integrated circuit substrate can be thinned by using the substrate of the first integrated circuits as a holding handle.

Avantageusement, on peut répéter au moins une fois les étapes a) à e) pour l'assemblage des structures intégrées tridimensionnelles obtenues à l'étape e) sur une plaque semi-conductrice contenant plusieurs circuits intégrés supplémentaires, lesdites structures intégrées tridimensionnelles formant lesdits deuxièmes circuits intégrés. D'autres avantages et caractéristiques de l'invention apparaîtront à l'étude de la description détaillée de modes de mise en oeuvre, pris à titre d'exemples non limitatifs et illustrés par les dessins annexés sur lesquels - la figure 1, déjà décrite, illustre schématiquement un assemblage de circuits intégrés selon l'art antérieur, et - les figures 2 à 10 illustrent différents modes de mise en oeuvre de l'invention. Advantageously, steps a) to e) can be repeated at least once for the assembly of the three-dimensional integrated structures obtained in step e) on a semiconductor plate containing a plurality of additional integrated circuits, said integrated three-dimensional structures forming said second integrated circuits. Other advantages and characteristics of the invention will become apparent upon studying the detailed description of embodiments, taken by way of nonlimiting examples and illustrated by the appended drawings in which - FIG. 1, already described, schematically illustrates an assembly of integrated circuits according to the prior art, and - Figures 2 to 10 illustrate different embodiments of the invention.

Sur la figure 2, on a représenté des circuits intégrés ICI réalisés au sein d'une plaque semi-conductrice formant un substrat de silicium SUB. Les circuits intégrés ICI comprennent de manière classique des transistors TR et des lignes métalliques LM d'un réseau d'interconnexion (« BEOL »). Les circuits intégrés IC1 sont destinés à être assemblés avec des circuits intégrés IC2 qui comportent également des transistors TR et des lignes métalliques LM d'un réseau d'interconnexions. Afin de relier électriquement les circuits intégrés ICI et IC2 dans un assemblage « face to face », des piliers de cuivre PCU ont été réalisés sur les faces avant des circuits intégrés IC1 et IC2. Les piliers de cuivre PCU on été réalisés par exemple au moyen d'un dépôt électrochimique sur une couche d'accroche et barrière UBM. Les piliers de cuivre PCU des circuits intégrés IC2 sont recouverts d'une couche d'un alliage à basse température de fusion SAC. Une couche de résine WLUF a également été déposée sur les circuits intégrés IC2 afin de combler l'espace entre les circuits intégrés IC1 et IC2. Sur la figure 3, on a représenté les circuits intégrés ICI et IC2 assemblés. Après cet assemblage, les circuits intégrés IC2 sont amincis une première fois par exemple lors d'un polissage mécanique. L'alliage SAC permet, de manière classique, de relier électriquement les piliers de cuivre CPU des circuits intégrés ICI et IC2. Afin de combler les espaces latéraux entre les circuits intégrés IC2, une couche de résine RES a été déposée de manière à encapsuler ces circuits intégrés IC2. FIG. 2 shows ICI integrated circuits formed within a semiconductor plate forming a SUB silicon substrate. The ICI integrated circuits conventionally comprise transistors TR and metal lines LM of an interconnection network ("BEOL"). Integrated circuits IC1 are intended to be assembled with integrated circuits IC2 which also include transistors TR and metal lines LM of an interconnection network. In order to electrically connect the ICI and IC2 integrated circuits in a "face to face" assembly, PCU copper pillars have been made on the front faces of the IC1 and IC2 integrated circuits. The PCU copper abutments have been made for example by means of electrochemical deposition on a UBM bonding layer and barrier. The PCU copper pillars of the IC2 integrated circuits are coated with a layer of a low melting alloy SAC. A layer of WLUF resin has also been deposited on the integrated circuits IC2 in order to fill the space between the integrated circuits IC1 and IC2. FIG. 3 shows the integrated circuits IC1 and IC2 assembled. After this assembly, the IC2 integrated circuits are thinned a first time for example during mechanical polishing. The SAC alloy conventionally makes it possible to electrically connect the CPU copper pillars of the ICI and IC2 integrated circuits. In order to fill the lateral spaces between the integrated circuits IC2, a resin layer RES has been deposited so as to encapsulate these integrated circuits IC2.

Outre le fait de combler les espaces latéraux entre les circuits intégrés IC2, la couche de résine RES recouvre les faces arrière des circuits intégrés IC2 et a une épaisseur de l'ordre de 80 micromètres. Cette résine RES est ensuite amincie (figure 4), par exemple au moyen d'un polissage mécanique de manière à laisser au moins un micromètre de résine RES sur les circuits intégrés IC2. Sur la figure 5, on a représenté les assemblages des circuits intégrés ICl et IC2 après une deuxième étape d'amincissement du substrat des circuits intégrés IC2. Lors de cette étape, le substrat SUB des circuits intégrés ICl forme une poignée de maintien suffisamment rigide. Cet amincissement peut être réalisé au moyen d'étapes de polissages mécaniques ou mécano chimiques. Le substrat SUB des circuits intégrés ICl, d'une épaisseur par exemple de l'ordre de 700 micromètres, est suffisamment épais pour permettre de manipuler les assemblages des circuits intégrés ICl et IC2, et ce, même après une étape d'amincissement du substrat des circuits intégrés IC2. Cette deuxième étape d'amincissement permet de réaliser des connexions électriques sur la face arrière des circuits intégrés IC2 (figure 6). Des liaisons traversantes électriquement conductrices TSV ont ainsi été réalisées au sein des circuits intégrés IC2. La deuxième étape d'amincissement permet en outre de contrôler la hauteur et le facteur de forme des liaisons traversantes électriquement conductrices TSV. Ainsi, des liaisons traversantes TSV d'une hauteur de 60 micromètres pour une largeur de 30 micromètres peuvent être envisagées pour un facteur de forme de l'ordre de deux. On peut ainsi relâcher le facteur de forme c'est-à-dire obtenir un facteur de forme inférieur ou égal à deux. Les liaisons traversantes TSV relient des lignes métalliques LM à des piliers de cuivre PCU2 réalisés sur la face arrière des circuits intégrés IC2. En outre, une couche d'un alliage à basse température de fusion SAC a été déposée sur les piliers de cuivre PCU2. In addition to filling the lateral spaces between the integrated circuits IC2, the resin layer RES covers the rear faces of the integrated circuits IC2 and has a thickness of the order of 80 microns. This RES resin is then thinned (Figure 4), for example by means of a mechanical polishing so as to leave at least one resin micrometer RES on integrated circuits IC2. FIG. 5 shows the assemblies of the integrated circuits IC1 and IC2 after a second step of thinning the IC2 integrated circuit substrate. During this step, the substrate SUB of the integrated circuits IC1 forms a sufficiently rigid holding handle. This thinning can be achieved by means of mechanical or mechano-chemical polishing steps. The SUB substrate ICl integrated circuits, a thickness for example of the order of 700 micrometers, is thick enough to handle the assemblies of integrated circuits IC1 and IC2, and even after a stage of thinning of the substrate integrated circuits IC2. This second thinning step makes it possible to make electrical connections on the rear face of integrated circuits IC2 (FIG. 6). TSV electrically conductive through connections have thus been made within IC2 integrated circuits. The second thinning step also makes it possible to control the height and the form factor of the electrically conductive through connections TSV. Thus, TSV through-links of a height of 60 micrometers for a width of 30 microns can be envisaged for a form factor of the order of two. It is thus possible to release the form factor, that is to say to obtain a form factor less than or equal to two. TSV through connections connect LM metal lines to copper pillars PCU2 made on the rear face of IC2 integrated circuits. In addition, a layer of a low-melting SAC alloy was deposited on the PCU2 copper abutments.

Les assemblages des circuits intégrés IC1 et IC2 peuvent ensuite être découpés (figure 7) afin d'obtenir des structures intégrées tridimensionnelles. On va maintenant décrire plus en détails en se référant plus particulièrement aux figures 8 à 10, une variante de l'invention. Sur la figure 8, on a représenté les assemblages des circuits intégrés IC1 et IC2 après une étape de dépôt de résine RES et après des étapes d'amincissement du substrat des circuits intégrés IC1. Lors de cette étape, on utilise cette fois ci la couche de résine RES comme poignée de maintien afin d'amincir le substrat des circuits intégrés IC1 jusqu'à une épaisseur de l'ordre de plusieurs centaines de micromètres, par exemple 200 micromètres. Afin de former une poignée de maintien, la résine RES peut avoir une épaisseur de l'ordre de plusieurs centaines de micromètres. The assemblies of the integrated circuits IC1 and IC2 can then be cut (FIG. 7) in order to obtain integrated three-dimensional structures. We will now describe in more detail with particular reference to Figures 8 to 10, a variant of the invention. FIG. 8 shows the assemblies of the integrated circuits IC1 and IC2 after a resin deposition step RES and after stages of thinning the substrate of the integrated circuits IC1. During this step, this time the RES resin layer is used as a holding handle in order to thin the IC1 integrated circuit substrate to a thickness of the order of several hundred micrometers, for example 200 micrometers. In order to form a holding handle, the resin RES may have a thickness of the order of several hundred micrometers.

Ainsi, comme représenté sur la figure 9, des liaisons traversantes électriquement conductrices TSV peuvent être réalisées sur la face arrière des circuits intégrés IC1, ainsi que des piliers de cuivre PCU2. Sur la figure 10, on a représenté les assemblages des circuits intégrés IC1 et IC2 après une étape de découpe permettant d'obtenir des structures intégrées tridimensionnelles. On notera que les structures tridimensionnelles obtenues selon les deux variantes (résine comme poignée de maintien ou substrat des circuits intégrés ICI comme poignée de maintien) peuvent être assemblées sur une plaque semi-conductrice de plusieurs circuits intégrés supplémentaires. A cet égard, la plaque semi-conductrice des premiers circuits intégrés IC1 illustrée ci avant forme ladite plaque de circuits intégrés supplémentaires et les deuxièmes circuits intégrés IC2 illustrés ci avant sont remplacés par lesdites structures tridimensionnelles. Selon un aspect de l'invention, on obtient un procédé de réalisation de structures intégrées tridimensionnelles dit « face to face » ne nécessitant pas de substrat supplémentaire collé afin de former une poignée de maintien. Thus, as shown in FIG. 9, electrically conductive through connections TSV can be formed on the rear face of integrated circuits IC1, as well as copper pillars PCU2. FIG. 10 shows the assemblies of the integrated circuits IC1 and IC2 after a cutting step making it possible to obtain three-dimensional integrated structures. It will be noted that the three-dimensional structures obtained according to the two variants (resin as holding handle or ICI integrated circuit substrate as holding handle) can be assembled on a semiconductor plate of several additional integrated circuits. In this regard, the semiconductor plate of the first integrated circuits IC1 illustrated above forms said additional integrated circuit board and the second integrated circuits IC2 illustrated above are replaced by said three-dimensional structures. According to one aspect of the invention, there is obtained a method of producing three-dimensional integrated structures called "face to face" does not require additional substrate bonded to form a holding handle.

En outre, la réalisation de structures intégrées tridimensionnelles est facilitée et comprend un nombre réduit d'étapes. Par ailleurs, les étapes de réalisation des liaisons traversantes sont facilitées et peuvent être mises en oeuvre à des températures plus élevées. In addition, the realization of three-dimensional integrated structures is facilitated and comprises a reduced number of steps. Furthermore, the steps of forming the through connections are facilitated and can be implemented at higher temperatures.

Claims (4)

REVENDICATIONS1. Procédé de réalisation de structures intégrées tridimensionnelles comprenant : a) un assemblage sur plusieurs premiers circuits intégrés (IC1) réalisés au sein d'une plaque semi-conductrice de plusieurs deuxièmes circuits intégrés (IC2) ; b) un dépôt d'une couche de résine (RES) encapsulant les deuxièmes circuits intégrés (IC2) et comblant les espaces latéraux entre les deuxièmes circuits intégrés (IC2) ; c) un amincissement des substrats des premiers (IC1) ou des deuxièmes circuits intégrés (IC2) en utilisant comme poignée de maintien la couche de résine (RES) ou le substrat (SUB) des premiers circuits intégrés ; d) une réalisation d'au moins une liaison traversante électriquement conductrice (TSV) dans le substrat de chaque circuit intégré aminci ; et e) une découpe des assemblages des premiers (IC1) et deuxièmes circuits intégrés (IC2) de manière à former les structures intégrées tridimensionnelles. REVENDICATIONS1. A method for producing three-dimensional integrated structures comprising: a) an assembly on a plurality of first integrated circuits (IC1) made within a semiconductor plate of a plurality of second integrated circuits (IC2); b) a deposit of a resin layer (RES) encapsulating the second integrated circuits (IC2) and filling the lateral spaces between the second integrated circuits (IC2); c) a thinning of the substrates of the first (IC1) or second integrated circuits (IC2) using as a holding handle the resin layer (RES) or the substrate (SUB) of the first integrated circuits; d) an embodiment of at least one electrically conductive through connection (TSV) in the substrate of each thinned integrated circuit; and e) cutting the assemblies of the first (IC1) and second integrated circuits (IC2) so as to form the integrated three-dimensional structures. 2. Procédé selon la revendication 1, dans lequel on amincit le substrat des premiers circuits intégrés (IC1) en utilisant comme poignée de maintien la couche de résine (RES). 2. Method according to claim 1, wherein the substrate is thinned first integrated circuits (IC1) using as a holding handle the resin layer (RES). 3. Procédé selon la revendication 1, dans lequel on amincit le substrat des deuxièmes circuits intégrés (IC2) en utilisant comme poignée de maintien le substrat (SUB) des premiers circuits intégrés. 3. The method of claim 1, wherein the second integrated circuits (IC2) substrate is thinned using the substrate (SUB) of the first integrated circuits as a holding handle. 4. Procédé selon l'une quelconque des revendications précédentes, dans lequel on répète au moins une fois les étapes a) à e) pour l'assemblage des structures intégrées tridimensionnelles obtenues à l'étape e) sur une plaque semi-conductrice contenant plusieurs circuits intégrés supplémentaires, lesdites structures intégrées tridimensionnelles formant lesdits deuxièmes circuits intégrés (IC2). 4. Method according to any one of the preceding claims, wherein the steps a) to e) are repeated at least once for the assembly of the three-dimensional integrated structures obtained in step e) on a semiconductor plate containing several additional integrated circuits, said integrated three-dimensional structures forming said second integrated circuits (IC2).
FR1060344A 2010-12-10 2010-12-10 Method for making three-dimensional integrated structures, involves thinning substrates of integrated circuits by holding resin layer, and forming electrically conductive through-connection in thinned substrates Pending FR2968834A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3437133A4 (en) * 2016-04-01 2019-11-27 INTEL Corporation Techniques for die stacking and associated configurations

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040115867A1 (en) * 2001-11-01 2004-06-17 Kazutaka Shibata Semiconductor device and method for manufacturing same
EP1801866A2 (en) * 2002-11-05 2007-06-27 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20080308946A1 (en) * 2007-06-15 2008-12-18 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US20100117226A1 (en) * 2008-11-07 2010-05-13 Ku-Feng Yang Structure and method for stacked wafer fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040115867A1 (en) * 2001-11-01 2004-06-17 Kazutaka Shibata Semiconductor device and method for manufacturing same
EP1801866A2 (en) * 2002-11-05 2007-06-27 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20080308946A1 (en) * 2007-06-15 2008-12-18 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US20100117226A1 (en) * 2008-11-07 2010-05-13 Ku-Feng Yang Structure and method for stacked wafer fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3437133A4 (en) * 2016-04-01 2019-11-27 INTEL Corporation Techniques for die stacking and associated configurations
US11222863B2 (en) 2016-04-01 2022-01-11 Intel Corporation Techniques for die stacking and associated configurations

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