FR2874104B1 - METHOD FOR IDENTIFYING MULTIDIMENSIONAL LOGIC SPACE - Google Patents
METHOD FOR IDENTIFYING MULTIDIMENSIONAL LOGIC SPACEInfo
- Publication number
- FR2874104B1 FR2874104B1 FR0451771A FR0451771A FR2874104B1 FR 2874104 B1 FR2874104 B1 FR 2874104B1 FR 0451771 A FR0451771 A FR 0451771A FR 0451771 A FR0451771 A FR 0451771A FR 2874104 B1 FR2874104 B1 FR 2874104B1
- Authority
- FR
- France
- Prior art keywords
- logic space
- identifying multidimensional
- identifying
- multidimensional logic
- space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0451771A FR2874104B1 (en) | 2004-08-03 | 2004-08-03 | METHOD FOR IDENTIFYING MULTIDIMENSIONAL LOGIC SPACE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0451771A FR2874104B1 (en) | 2004-08-03 | 2004-08-03 | METHOD FOR IDENTIFYING MULTIDIMENSIONAL LOGIC SPACE |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2874104A1 FR2874104A1 (en) | 2006-02-10 |
FR2874104B1 true FR2874104B1 (en) | 2006-12-08 |
Family
ID=34948640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0451771A Expired - Fee Related FR2874104B1 (en) | 2004-08-03 | 2004-08-03 | METHOD FOR IDENTIFYING MULTIDIMENSIONAL LOGIC SPACE |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2874104B1 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1182571B1 (en) * | 2000-08-21 | 2011-01-26 | Texas Instruments Incorporated | TLB operations based on shared bit |
-
2004
- 2004-08-03 FR FR0451771A patent/FR2874104B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2874104A1 (en) | 2006-02-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name | ||
ST | Notification of lapse |
Effective date: 20100430 |