FR2871965B1 - METHOD AND DEVICE FOR DECODING ERROR CORRECTING CODES AND SYSTEMS EMPLOYING THEM - Google Patents
METHOD AND DEVICE FOR DECODING ERROR CORRECTING CODES AND SYSTEMS EMPLOYING THEMInfo
- Publication number
- FR2871965B1 FR2871965B1 FR0406687A FR0406687A FR2871965B1 FR 2871965 B1 FR2871965 B1 FR 2871965B1 FR 0406687 A FR0406687 A FR 0406687A FR 0406687 A FR0406687 A FR 0406687A FR 2871965 B1 FR2871965 B1 FR 2871965B1
- Authority
- FR
- France
- Prior art keywords
- error correcting
- systems employing
- decoding error
- correcting codes
- codes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0406687A FR2871965B1 (en) | 2004-06-17 | 2004-06-17 | METHOD AND DEVICE FOR DECODING ERROR CORRECTING CODES AND SYSTEMS EMPLOYING THEM |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0406687A FR2871965B1 (en) | 2004-06-17 | 2004-06-17 | METHOD AND DEVICE FOR DECODING ERROR CORRECTING CODES AND SYSTEMS EMPLOYING THEM |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2871965A1 FR2871965A1 (en) | 2005-12-23 |
FR2871965B1 true FR2871965B1 (en) | 2006-09-01 |
Family
ID=34946899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0406687A Expired - Fee Related FR2871965B1 (en) | 2004-06-17 | 2004-06-17 | METHOD AND DEVICE FOR DECODING ERROR CORRECTING CODES AND SYSTEMS EMPLOYING THEM |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2871965B1 (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7000168B2 (en) * | 2001-06-06 | 2006-02-14 | Seagate Technology Llc | Method and coding apparatus using low density parity check codes for data storage or data transmission |
US6633856B2 (en) * | 2001-06-15 | 2003-10-14 | Flarion Technologies, Inc. | Methods and apparatus for decoding LDPC codes |
US6938196B2 (en) * | 2001-06-15 | 2005-08-30 | Flarion Technologies, Inc. | Node processors for use in parity check decoders |
WO2003021440A1 (en) * | 2001-09-01 | 2003-03-13 | Bermai, Inc. | Decoding architecture for low density parity check codes |
-
2004
- 2004-06-17 FR FR0406687A patent/FR2871965B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2871965A1 (en) | 2005-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 13 |
|
PLFP | Fee payment |
Year of fee payment: 14 |
|
PLFP | Fee payment |
Year of fee payment: 15 |
|
ST | Notification of lapse |
Effective date: 20200206 |