FR2811830A1 - Multifunction circuit, uses multiple gates and interconnection switches to allow configuration of circuit to provide different functions - Google Patents

Abstract

The multifunction circuit has a set of gates (400, 401-415) connected in series. In addition connecting switches (418-420, 422-424, 426, 428, 429, 432, 434, 435) are incorporated into the integrated circuit to allow configuration of the circuit to obtain one of an error detection circuit, a counter, or a shift register.

Description

MULTIFUNCTIONAL CIRCUIT

  The subject of the invention is a multifunction circuit for an integrated circuit which performs error detection and / or offset detection functions in a register and / or counting. The invention is particularly advantageous for integrated circuits for memory cards, or more generally for any integrated circuit which receives and / or

transmits data.

  An integrated circuit for contactless cards generally receives energy, a synchronization signal, data, instructions, etc., via a modulated signal transmitted by a reader. Transmission can take place with or without direct contact between the reader and the card. Data detection and demodulation circuits extract the received data, which notably include digital data, instructions, addresses, etc. The data are generally transmitted in the form of blocks (also called frames) of P * N bits transmitted in series, each frame being followed by a number (also called key) of N bits deduced from the frame of P * N bits transmitted by the following modulo 2 polynomial arithmetic operation. If we consider that a frame of P * N bits is equivalent to a polynomial of degree P * N-11, and if this polynomial is divided by a reference polynomial (also called generator polynomial), then the key is a number of N bits equivalent to the remainder of the division, the remainder being a polynomial of degree N-1. The generator polynomials used are defined by the standards

ISO 14443 and ISO 15693.

  The integrated circuit can also include an error detection circuit which checks the good reception of each bit frame using the key which it receives at the end of the transmission of each bit frame. The data is then stored or used

otherwise.

  The integrated circuit of a card can also include one or more binary counters, which are used for example as time measurement circuits, to determine programming or erasing times of a memory, or synchronization times or flipping an antenna

  transmission / reception of the detection circuit.

  Finally, the integrated circuit can also include a shift register, used for example to temporarily store a key resulting from an error detection calculation before the transmission of data in

direction of the reader.

  IS A recurring problem of integrated circuits is

  their size, in terms of silicon surface used.

  They must be integrated into increasingly smaller objects such as cards or electronic labels. However, increasing the number of their functionalities most often leads to an increase

of size.

  Another recurring problem is the energy consumption of integrated circuits, which most often increases with the number of their functionalities and their size. However, in the case of contactless cards in particular, the energy received by the card is limited and it is therefore essential to limit the consumption of each

element of the integrated circuit.

  To limit the size, in terms of silicon surface area, and the overall energy consumption of the integrated circuit, the invention proposes to delete the error detection circuit and / or the shift register and / or the counting circuit usually used. and replace them with a single circuit

  3S multifunction smaller and consuming less energy.

  With these objectives in view, the invention relates to a multifunction circuit comprising a set of flip-flops connected in series, the circuit being characterized in that it also comprises connection means for configuring the multifunction circuit and thus obtaining at least two of the following three circuits: error detection circuit, counting circuit, or shift register. The idea of the invention appeared after the following observations: - the error detection circuit, the counter and / or the shift register are never used simultaneously in time, and - they each use a set of flip-flops approximately the same size, connected together in series, directly or through doors

  logical, as will be better understood later.

  The invention thus proposes to use the same set of flip-flops to produce a single circuit for implementing at least two of the following three functions: error detection, shift in a register or counting. Of course, according to one embodiment of a multifunction circuit according to the invention, the same set of flip-flops is used to implement the three

functions in the same circuit.

  Before describing the invention and its embodiments more fully, it is necessary to describe known embodiments of an error detection circuit, of a pseudo-random number generator and

  of a shift register, as well as their operation.

  The error detection circuit of FIG. 1 allows the verification of all the keys of N - 16 bits received during the transmission of data frames of size P * N, according to the standards ISO 14443 and ISO 15693. The circuit of FIG. 1 makes it possible to divide a polynomial of degree P * N-1 (in polynomial arithmetic modulo 2), equivalent to DATA data of P * N bits, by

  the generator polynomial PGD (X) = X16 + X12 + X5 + 1.

  The error detection circuit of FIG. 1 comprises N flip-flops 100 to 115 and three logic gates 120, 122, 124. Each flip-flop 100 to 115 comprises a data input D, a clock input CP and a data output Q. All flip-flops are the same, flip-flop 115 has simply been enlarged to make it easier for the reader to understand. Each door

  logic includes two inputs and one output.

  The D data input of flip-flops 100 to 102 is connected to the Q data output of flip-flops 101 to 103. The D data input of flip-flops 104 to 109 is connected to the Q data output of flip-flops 105 to 110. The data input D of flip-flops 111 to 114 is connected to the output Q of flip-flops 112 to 115. The clock inputs CP of all the flip-flops are connected together to receive the same clock signal SCP (connections not shown in Figure 1), used to clock the operation of the detection circuit. Gate 120 is of the OUEXCLUSIF type with two inputs, one of its inputs is connected to the output of flip-flop 100 and its other input is connected to an input terminal 126 for receiving DATA data in series. The output of gate 120 is connected to the input

of scale 115.

  The gate 122 is of the OU-EXCLUSIVE type, its inputs are connected respectively to the output of the gate 120 and to the output Q of the flip-flop 104. Finally, the gate 124 is of the OU-EXCLUSIVE type, its inputs are connected respectively to exit from gate 120 and exit

Flip-flop Q 111.

  The circuit of Figure 1 operates as follows. On reception, the DATA data, then the corresponding key, are transmitted in series to the

  error detection, on the data entry terminal 126.

  If the transmission of the data was carried out correctly, then the contents of flip-flops 100 to 115 is equal to 0 at the end of the transmission. Conversely, on transmission, the DATA data is transmitted in series to the error detection circuit followed by N zeros. At the end, flip-flops 100 to 115 contain the key associated with the DATA data, which is transmitted to the reader afterwards.

Datas.

  (0 The error detection circuit of FIG. 1 is used in particular when the DATA data is transmitted in series in the form of P words of N bits, the most significant bit being loaded first, with N = 16 , and that the key associated with a data frame of P * N bits is a number coded on N = 16 bits, the least significant bit of the key being loaded first, after loading the most significant bit weak of

DATA data.

  However, circuits other than the circuit of FIG. 1 can be used and are also known for error detection by key. For example, the key can have N = 2, 12, 16 or 32 bits, we use in this case a set of N = 2, 12, 16 or 32 flip-flops. It is also possible to load the DATA data, or the key, in series starting with the least significant bit. It is also possible to use other generator polynomials, depending on the type of

  data to be transmitted for example.

  In general, all these circuits are o similar to the circuit of FIG. 1: they include a set of N flip-flops, N being the size of the generator polynomial used, N also being the size of the key transmitted after data of P * N bits. The N flip-flops are associated in series via: - a first logic gate, for example of the OU-EXCLUSIVE type, comprising an input connected to the data input terminal to receive the DATA data in series, a connected input at the Q output of the 1 "flip-flop or at the Q output of the Nth flip-flop, and an output connected to the data input D of the NIe 'flip-flop or to the data input of the 1st flip-flop, - a second door of the OU- EXCLUSIVE type, comprising an input connected to the output of the door, an input connected to the output Q of the flip-flop and an output connected to the input of a flip-flop adjacent to the i-th flip-flop, that is to say at the exit of the (i-1) Ime flip-flop or at the exit of the (i + l) flip-flop, i being a number between 1 and N-1 (i = 4 and the ie flip-flop is flip-flop 103 in the example of figure 1), - possibly one (for example in the case of the circuit of figure 1) or more Their other OU-EXCLUSIVE gates The total number of OU-EXCLUSIVE gates to be used depends on the number of monomials in the generator polynomial. Thus, if we consider a circuit A comprising first and second doors, and possibly one or more other doors, and if circuit A is associated with a set of N flip-flops according to a diagram similar to that of FIG. 1, then l 'assembly forms an error detection circuit; it is used to check the transmission of any data frame associated with

  a size key less than or equal to the size (i.e.

  i.e. the number of flip-flops) of the flip-flop set.

  A generator of pseudo-random numbers of M bits is a circuit which, at each cycle i of a clock signal, supplies a series of numbers Xi such that the series is periodic, and such that the same number is supplied only one times over a period, randomly. A generator of pseudo-random numbers of M bits can therefore easily replace a counter of M bits, by simply identifying the rank i of each number Xi supplied by the generator. The properties of pseudo-random number generators and their operation are detailed in particular in the document Dl (Design of integrated circuits MOS, CNET - ENST,

Ed. Eyrolles).

  FIG. 2 shows an exemplary embodiment of a known generator of pseudo-random numbers of M bits, associated with the generator polynomial PGC (X) = 1 + X + X15. This polynomial has a maximum period of 2M - 1, that is to say that it provides over a period all the numbers of M bits between 1 and 2M - 1. In addition, this polynomial includes a reduced number of monomials , which makes it very simple to implement since the number of logic gates to be used is a function of the number of monomials of the

associated polynomial.

  The polynomial is generally chosen so that the associated generator has the greatest possible period (2M - 1) and that it requires the smallest number of components (gates, flip-flops). Since, in the example of figure 2, the associated polynomial is of degree 15, then it is necessary M = 15 rockers to carry out the

corresponding circuit.

  The circuit of FIG. 2 comprises 15 flip-flops 201 to 215, identical to flip-flop 115, each comprising a data input D, a clock input CP, an initialization input ST and a data output Q. The input D of the flip-flops 201 to 213 is connected respectively to the Q output of the flip-flops 202 to Jo 214. The D input of the flip-flop 215 is connected to the Q output of the flip-flop 201. The clock inputs CP of all the flip-flops 201 to 215 are connected together to receive the same SCP synchronization signal (connections not shown in FIG. 1). Similarly, the initialization inputs of all the flip-flops are connected together to receive the same SST initialization signal (connections not shown on the

figure 1).

  The pseudo-random number generator includes

  also a door 220, preferably of type OU-

  EXCLUSIVE, comprising two inputs and one output, connected respectively to the output of flip-flop 201, to the output of flip-flop 215 and to the input of flip-flop 214. Optionally, the circuit also includes a parallel output terminal (not shown in Figure 2) consisting of all the outputs D of the flip-flops

201 to 215.

  It should be noted that the value "0" is a stable value for the circuit of FIG. 2; indeed, if X0,

  the initial value of the pseudo- number generator

  random, is zero, so all Xi are zero. It is therefore essential to initialize at "1" at least one of the flip-flops 201 to 215, in order to bypass this zero value. In the example of FIG. 2, the initialization inputs ST of all the flip-flops are connected together to receive the same signal SST, all the flip-flops are thus initialized to "1". It should also be noted that the value "1" can be a stable value for other generators similar to that of FIG. 1, for example generators having a different characteristic polynomial or generators produced from logic gates of different type . In that case,

  care will be taken to initialize such a generator to "0".

  In general, the generators of pseudo-random numbers are similar to the circuit of FIG. 2: they include a set of M flip-flops, M being the size of the associated generator polynomial. The M scales are associated in series through:

  - a logic gate, for example of type OU-

  EXCLUSIVE, comprising an input connected to the output of the first flip-flop, an input connected to the output of the jth flip-flop and an output connected to the data input D of a flip-flop adjacent to the jlem flip-flop, i.e. - say at the exit of the (jl) th flip-flop or at the exit of the (j + l) th flip-flop, j being a number between 1 and M-1 (in the example of Figure 1, j = 214 ), - possibly one or more other gates OR- EXCLUSIVE if the generator polynomial includes a number of

monomials higher than 3.

  Thus, if we consider a circuit B comprising a logic gate and if circuit B is associated with a set of M flip-flops according to a diagram similar to that of FIG. 2, then the whole forms a generator of pseudo-random numbers, which can easily be used as a counter. The pseudo-random number generator also has the advantage of being simpler to perform

than a conventional counter.

  According to a known embodiment, a simple shift register of size N comprises, in accordance with FIG. 3, a set of N flip-flops 300 to 315, identical to flip-flop 115 and each comprising a data input D, an input of CP clock, an initialization input ST and a data output Q. The flip-flops are associated in series, the data input D of the first to N-th flip-flops being connected respectively to the data output Q of the second to Nieme flip-flops . N is in practice equal to the size of the data words to be processed. The clock inputs CP of all the flip-flops are connected together to receive the same synchronization and timing signal SCP (connections not shown in FIG. 3). In the example of Figure 3, the shift register also includes a data input 320 and / or a data output 321 for entering and / or outputting data in series in the register. The register can also include, if necessary, a parallel data output (not shown), consisting of the serial outputs of all

scales 300 to 315.

  Thus, if we consider a circuit C possibly including a data output terminal, and if circuit C is associated with the set of N flip-flops according to a diagram similar to that of FIG. 3, then the set

  forms an N-bit shift register.

  The connection means of the invention preferably comprise at least two of the following three circuits A, B, C: - a circuit A comprising a data input terminal, a first logic gate, a first input of which is connected to the terminal data input, and a second gate, - a circuit B comprising a third logic gate, - a circuit C, the connection means also comprise connection means for selectively connecting the set of flip-flops to circuit A to make the circuit error detection, to circuit B to realize the counting circuit or to circuit C to realize the shift register. According to one embodiment of the invention, the linking means associate, as a function of a selection signal, the set of flip-flops either to circuit A to form the error detection circuit or to circuit B to form the circuit count. For this, the multifunction circuit of the invention comprises circuit A and circuit B, and the connection means comprise: - a fourth door comprising an output connected to a data input of the Nlme flip-flop or to a data input of the 1st flip-flop, s - a fifth door comprising an output connected to a first input of the second and fourth doors, and comprising two inputs connected respectively to a first selection input terminal via an inverter and to the output of the first door, the second input of the first door being connected to an output of the 1st flip-flop or to an output of the N-th flip-flop, an output of the second door being connected to a data input of the i-th flip-flop, a input of the second door being connected to the output of a flip-flop adjacent to the second flip-flop, i being a number between 1 and N-1, an output of the third door while connected to a data input of the jieme flip-flop, an input of the third gate being connected to the output of a flip-flop adjacent to the j th flip-flop, j being a number between 1 and N-1, - a sixth gate comprising two inputs connected respectively to the selection input terminal and to the output of the kieme flip-flop, and an output connected to a second input of the fourth door and to a second input of the third door, k being a number between 1 and N. According to another embodiment, the connection means associate, as a function of the selection signal, the set of flip-flops either to circuit A to form the error detection circuit, or to circuit C - to form the shift register. In this case, the multifunction circuit according to the invention comprises circuit A and circuit C, and the connection means comprise o30 first and second multiplexers comprising a selection input connected to a second selection input terminal on which is applied a second selection signal, the first multiplexer also comprising a data output connected to the data input of the i "em" flip-flop, a first data input connected to the output of the second gate and a second data input connected to the output of a flip-flop adjacent to the second scale and to a first input of the second door, a second input of the second door being connected to the output of the first door, the inputs of the first door being connected respectively at the data input terminal and at the output of the first or the Nth flip-flop, i being an integer between 1 and N -1, and the second multiplexer also comprising a data output connected to the data input of the Nieme or 1st flip-flop, a first data input connected to the output of either the 1st flip-flop or the Nth flip-flop and a second input data connected to

the exit of the first door.

  According to another embodiment, the connection means associate, as a function of the selection signal, the set of flip-flops either to circuit B to form the counting circuit or to circuit C to form the shift register. In this case, the multifunction circuit of the invention comprises circuit B and circuit C, and in that the connection means comprise: - the sixth door comprising a first input connected to the selection input terminal by the through an inverter, and a second input

  connected to the output of the kth flip-flop, -

  the second multiplexer comprising two data inputs connected respectively to the output of the sixth gate and to the data output of the first flip-flop or of the Nth flip-flop, a selection input connected to the selection input terminal to receive the selection signal, and a data output connected to the data input of the N'èm & flip-flop or to the data input of the 1st flip-flop, - a third multiplexer comprising a data output connected to the data input of the j1em flip-flop, a first data input connected to the output of the third gate and a second data input connected to the output of a flip-flop adjacent to the jLe-flip-flop and to a first input of the third door, a second entrance to the third door being

  connected to the output of the sixth door.

  Finally, according to another embodiment, the connection means associate, as a function of two selection signals, the set of flip-flops either to circuit A to form the detection circuit, or to circuit B to form the counting circuit or either to circuit C to form the shift register. The multifunction circuit according to the invention in this case comprises circuits A, B and C, and the connection means comprise: - the fourth door, - the fifth door comprising two inputs connected respectively to the selection input terminal by l intermediate of the inverter and at the output of the first door, the second input of the first door being connected to the output of the 1st scale or to the output of the Nth scale, - the sixth door, the inputs of which are connected respectively at the output of the flip-flop kime and at the selection input terminal, and the output of which is connected to the first input of the fourth door and to

  the second entrance of the third door, -

  the first multiplexer, its data output being connected to the output of the flip-flop, its first data input being connected to the output 0 of a flip-flop adjacent to the ith flip-flop and to the input of the second gate , its second data input being connected to the output of the second door, - the third multiplexer, its data output being connected to the output of the j th scale, its first data input being connected to the output of a scale adjacent to the output of a flip-flop adjacent to the jieme flip-flop and the first input of the third door, its second data input being connected to the output of the third door, and - the second multiplexer, its output being connected to the data input of the Nleme flip-flop or to the data input of the 1st flip-flop, its first data input being connected to the output of the 1st flip-flop or to the output of the Nth flip-flop, its second data input being connected to the output of the fourth gate, the selection inputs of all the multiplexers being connected together to the second input terminal of

  selection to receive the second selection signal.

  Preferably, the set of flip-flops comprises N flip-flops, with N a number equal for example to 12, 16 or 32. The multifunction circuit of the invention can then be used when the data is transmitted in the form of a frame of P words of 12, 16 or 32 bits and / or when the key corresponding to a frame is 12, 16 or

32 bit.

  The invention also relates to an integrated circuit card, characterized in that the integrated circuit comprises a multifunction circuit as described above. The invention will be better understood and other characteristics and advantages will appear on reading

  of the description which follows of an example no

  limitation of a multifunction circuit, description

  referring to the appended drawings in which: - Figure 1 is a diagram of a known error detector, - Figure 2 is a diagram of a pseudo-random number generator, - Figure 3 is a diagram of a register at S35 known offset, - Figure 4 is a diagram of a circuit

multifunctional according to the invention.

  Figures 1 to 3 having been described previously and constituting the state of the art, they will not be

not described in more detail.

  The multifunction circuit of FIG. 4 can be used as an error detector, as a counter or as a shift register, for data of N = 16 bits, the selection of one of the three functions being

  made via two control signals.

  The multifunction circuit includes N = 16 flip-flops 400 to 415 of type D, identical to flip-flop 115 of FIG. 1, two selection input terminals 418, 419 to which RD, P signals are applied, an input terminal 420 to receive external DATA, an inverter 423, seven logic gates 422, 424, 426, 428, 430, 432 and 434 and four

multiplexers 429, 431, 433, 435.

  The flip-flops 400 to 415 are identical to the flip-flop 115, they each comprise a data input D, a data output Q, an initialization input ST and a clock input CP. The initialization inputs ST of all flip-flops 400 to 415 are connected together to an input terminal 416 to receive the same initialization signal SST. Similarly, the clock inputs CP of all flip-flops 40-0 to 415 are connected together to an input terminal 417 for

  receive the same SCP clock signal.

  The flip-flops 400 to 402 have their data input D () connected respectively to the data output Q of the flip-flops 401 to 403. The flip-flops 404 to 409 have their data input D respectively connected to the data output of flip-flops 405 to 410 Finally, flip-flops 411 to 413 have their data input D connected respectively to the data output of flip-flops 412 to 414. The logic gates include two inputs and one output. The multiplexers include two data inputs, a select input and a data output. In the example, door 422 is of type OU-

  EXCLUSIVE, its data inputs are respectively connected to the data input terminal 420 to receive DATA data from the outside, and to the

output Q of flip-flop 400.

  The gate 424 is here of the AND type, its two data inputs are respectively connected to the input terminal 419 via the inverter 423, and to

  the data output of logic gate 422.

  Gate 426 is of the ET type; its two inputs are respectively connected to the Q output of flip-flop 401

and at input terminal 419.

  Gate 428 is of the EXCLUSIVE type, its two data inputs are connected respectively to the output of gate 424 and to the Q data output of flip-flop 404. The two data inputs of multiplexer 429 are respectively connected to the output of gate 428 and to output Q of flip-flop 404. The output of multiplexer 429 is connected to input D of the

scale 403.

  The gate 430 is of the OU-EXCLUSIVE type, its data inputs are connected respectively to the output of the gate 424 and to the data output Q- of the flip-flop 411. The two data inputs of the multiplexer 431 are connected to the output from gate 430 and at output Q of flip-flop 411 and the output of multiplexer 431 is

  connected to input D of flip-flop 410.

  Gate 432 is of the EXCLUSIVE type, its data inputs are connected respectively to the output of gate 426 and to the data output D of the flip-flop 415. The data inputs of multiplexer 433 are connected to the output of the gate 432 and at the output Q of the flip-flop 415. The output of the multiplexer 433 is

  connected to the data input D of the flip-flop 414.

  Gate 434 is of the OR type, its two inputs are connected respectively to the output of gate 426 and to the output of gate 424. The two data inputs of multiplexer 435 are connected to the output of

  gate 434 and at the data output Q of the flip-flop 400.

  The output of multiplexer 435 is connected to the input of

data D of flip-flop 415.

  Finally, the selection inputs of all the multiplexers 429, 431, 433, 435 are connected together to the input terminal 418 to receive the same validation signal RD. When RD is equal to "0", the input of flip-flops 403, 410, 414 and 415 is connected respectively to the output of doors 428, 430, 432 and 434. Conversely, when RD is equal to "1", then l the data input D of flip-flops 403, 410, 414 and 415 is connected respectively to the output of flip-flops 404, 411, 415 and 400. Optionally, but not necessarily, the circuit of FIG. 4 may additionally include an output terminal 421 series connected to the output of the first flip-flop 400 to output data contained in flip-flops 400 to 415 in series. The circuit of FIG. 4 can also include a parallel data output terminal consisting of the N outputs of the N flip-flops 400 to 415. The overall functioning of the multifunction circuit

of Figure 4 is as follows.

  Case where RD = "0" and P = "0" Since RD is zero, the inputs of flip-flops 403, 410, 414 and 415 are respectively connected to the outputs

doors 428, 430, 432 and 434.

  In addition, since P is equal to "0", the door 424 is transparent and is equivalent to a wire connected between the outlet of the door 422 and the inlet of the doors 428, 430, 434. Similarly, the outlet of the door 426 is equal to "0", door 434 is therefore transparent and is equivalent to a wire connected between the output of the door

  426 and the data entry D of the Nleme flip-flop 415.

  Finally, since P is equal to "0", gate 432 receives a "0" on one of its terminals, it is therefore transparent and equivalent to a wire connected between the output of flip-flop 415 and the data input D of the

scale 414.

  Thus, when RD and P are zero, the circuit of FIG. 4 is equivalent to a known error detection circuit such as that of FIG. 1, and it

works similarly.

  Case RD = "0" and P = "1" Since RD is zero, the inputs of flip-flops 403, 410, 414 and 415 are connected to the outputs of the doors

428, 430, 432 and 434.

  In addition, since P is equal to "1", the door 426 is therefore transparent and equivalent to a wire connected between

  the entry of the door 434 and the exit of the rocker 401.

  The output of door 424 is kept equal to "0", door 434 is equivalent to a wire, the output of flip-flop 401 is therefore connected to the data input flip-flop 415. For the same reasons, doors 428 and 430 are equivalent to a wire and the data input of flip-flops 403, 410 is connected to the output of flip-flops 404, 411. Thus, when P "1" and RD = "0", then the

  circuit is equivalent to a pseudo- number generator

  random like the one in figure 2 and it works

identically.

  Case RD = "1" and P = "0" When RD is equal to "1", the inputs of flip-flops 403, 410, 414 are connected directly to the outputs of flip-flops 404, 411 and 415. Doors 422 to 432 are in this case unused. The circuit is then equivalent to a

  shift register like the one in figure 3.

  The circuit of Figure 4 is of course only an example of implementation of the invention, other circuits can be envisaged, without departing from the scope of the invention. For example, it is possible to replace doors 424, 426 with NAND doors, and door 434 with a NAND door. In this case, it is necessary to connect the inputs of doors 428, 430, 432 to negative / Q outputs of flip-flops 404, 411, 415 instead of connecting them to their positive Q outputs. Such a modified circuit works identically to that of Figure 4. This is possible thanks to the simple equivalences between the different logical functions of

binary algebra.

  Similarly, to carry out the error detection function with the circuit of FIG. 4, the DATA data are entered in series on an input of the gate 422, the other input of which is connected to the output Q of the 1st flip-flop 400; one speaks in this case of a mode of loading by the least significant bit. It is however possible to use a circuit in which the DATA data is

  inputs in series on an input of an OU type door

  EXCLUSIVE, the other input of which is connected to the Q output of the NI "does not switch 415 (loading mode - by the most significant bit). To obtain such a circuit, it is of course necessary to modify the elements of logic (choice and location of doors in particular) of the

3.0 Figure 4.

  The circuit of figure 4 is used for data of size N = 16 and it is associated with the polynomial PGD (X) = X16 + X 2 + X5 + 1 for the error detection function and with the polynomial PGC (X) = 1 + X + X'5 for the 3S counting function (or generation of random numbers). Other polynomials can of course be implemented in multifunction circuits according to the invention. In this case, the number of flip-flops used will be adapted to the size of the data (for example N = 12 or 32) and to the degree of the polynomials chosen, the number and the position of the gates (428, 430, 432, 434) and of the multiplexers (429, 431, 433, 435)

  associates will also be adapted.

  In the example of FIG. 4 again, the initialization inputs ST of all the flip-flops 400 to 415 are connected together to receive the same initialization signal SST; it is indeed a question of not initializing at 0 the set of rockers so that the circuit of generation of pseudo-random numbers can function correctly. It is however possible to apply the signal SST to the input ST of a single flip-flop, this is sufficient to avoid the value 0. Of course, if in another example of implementation, the value "1" is a stable value, then at least one toggle

will be initialized to "0".

  In the example of FIG. 4, the counting function (or generation of pseudo-random numbers) is carried out with flip-flops 401 to 415 because it is sufficient to use 15 flip-flops to perform such a function; However, this function can also be performed with flip-flops 400 to 414. It suffices for this to move the gate 432 and the multiplexer 433 between the flip-flop 413 and the flip-flop 414, to connect the output of the multiplexer 433 to the input of the flip-flop 413, and connect one of the inputs of the multiplexer 433 and one of the inputs of the gate 432 to the output of the flip-flop (0 414. The input of flip-flop 414 is of course in this case directly connected to the output of flip-flop 415. It is also possible to use a number of flip-flops less than 15 to perform the counter function, by choosing for example a different generator polynomial

from the one chosen in the example.

  Finally, the link between the input of the first flip-flop 400 and the Nth flip-flop 415 is not essential and can be deleted, we will also delete the

multiplexer 435 in this case.

  The circuit of FIG. 4 makes it possible to perform counting, error detection and register shift functions with a single circuit, by selecting one of the three functions by means of two selection signals RD, P. It is however possible to simplify the circuit of Figure 4 to achieve a circuit implementing only two of the three functions, if the third function is not necessary. For example, if only the IS error detection and register offset functions are required, a

  only selection signal is essential, the RD signal.

  The doors 424, 426, 434, the inverter 423, the input terminal 419, the doors 430, 432 and the associated multiplexers 431, 433 are unnecessary and can in this case be deleted, as well as all the links associated with these elements. The circuit is finally completed by directly connecting the output of flip-flop 415 to the input of flip-flop 414, and the output of gate 422 directly to the inputs of gates 428, 430, 432. In this case, when RD is equal to "0", then the circuit is

  equivalent to an error detection circuit.

  Conversely, if RD is equal to "1", then the circuit is

  equivalent to a shift register.

  Similarly, if only the error detection and counting functions are necessary, only one signal is essential, the P signal. Multiplexers 429, 431, 433, 435, the input terminal 418, the link between in this case, the output of flip-flop 400 and the input of flip-flop 415 are deleted, as are all the links associated with these elements. The circuit is finally completed by directly connecting the output of doors 428, 430, 432 434 respectively to the input of flip-flops 403, 410, 414, 415. In this case, when P is equal to "0", then the circuit is equivalent to an error detection circuit. Conversely, when P is equal to "1", then the circuit is equivalent to a pseudo-random number generator, which can

  in particular be used as a counter.

  Finally, if only the register shift and counting functions are necessary, a single signal is essential, for example the signal RD. The doors 422, 424, 428, 430, the terminal 419, the inverter 423, and the multiplexers 429, 431 are in this case deleted, as well as all the links associated with these elements. The circuit is finally completed by directly connecting the output of flip-flops 404, 411, respectively to the input of flip-flops 403, 410, and by connecting the output of gate 426 to the input of multiplexer 435. In addition, the input of gate 426 is no longer connected to terminal 419 to receive the signal P, but to terminal 418 via the inverter 423 to receive the signal / RD. In this case, when RD is equal to "0", then the circuit is equivalent to a pseudo-random number generator. Conversely, when RD is equal to "1", then the circuit is equivalent to a register with

offset.

Claims (10)

  1. Multifunction circuit comprising a set of rockers (400, 401 to 415) connected in series, the circuit being characterized in that it also comprises connection means (418, 419, 420, 421, 422, 423, 424, 426, 428, 429, 432, 433, 434, 435) to configure the multifunction circuit and thus obtain at least two of the following three circuits: error detection circuit,   counting circuit, or shift register.   2. Multifunction circuit according to claim 1, characterized in that the connection means comprise at least two of the following three circuits A, B, C: - a circuit A comprising a data input terminal (420), a first door logic (422), a first input of which is connected to the data input terminal (423), and a second gate (428), - a circuit B comprising a third logic gate (432), - a circuit C, and in this the connection means also comprises connection means (418, 419, 423, 424, 426, 429, 433, 434, 435) for selectively connecting the set of flip-flops to circuit A to carry out the error detection circuit, to circuit B to carry out the counting circuit or to circuit C to carry out the shift register. 3. The circuit as claimed in claim 1, characterized in that the circuit receives data on the data input terminal (420) in the form of an N-bit word frame and in that the set of flip-flops comprises   first (400) to N th (415) flip-flops associated in series.   4. Circuit according to claim 1, characterized in that at least one flip-flop of the flip-flop set comprises an initialization input (ST) at "1", for receiving a initialization signal (SST).   5. Circuit according to claim 1, characterized in that all the flip-flops in the flip-flop set include a clock input (CP) and in that the clock inputs of all the flip-flops are connected together   to receive the same clock signal (CCP).   6. Circuit according to claim 1, characterized in that it comprises circuit A and circuit B, and in that the connection means comprise: - a fourth door (434) comprising an output connected to a data input ( D) of the Nth scale (415) or to a data entry (D) of the 1st scale (400)   - a fifth door (424) comprising an output connected to a first input of the second (428) and fourth (434) doors, and comprising two inputs connected respectively to a first selection input terminal (419) via d '' an inverter (423) and at the output of the first door (422), the second input of the first door (422) being connected to an output (Q) of the 1st scale (400) or to an output of the N 6th (415) flip-flop, an output of the second door (428) being connected to a data input (D) of the i th flip-flop, o30 an input of the second door (428) being connected to the output of a flip-flop adjacent to the inaeó flip-flop, i being a number between 1 and Nl, an output of the third (432) door being connected to a data input (D) of the ji4m flip-flop,) 5 an input of the third door (432 ) being connected to the output of a flip-flop adjacent to the jlme flip-flop, j being a name bre comprised between 1 and N-1, - a sixth door (426) comprising two inputs connected respectively to the selection input terminal (419) and to the output of the scale km (401), and an output connected to a second entry of the fourth door (434) and a second entry of the third door (432), k being a number between 1 and N. 7. Circuit according to claim 1, characterized in that it comprises circuit A and circuit C, and in that the connection means comprise first and second multiplexers (429, 435) comprising a selection input connected to a second selection input terminal (418) to which a second selection signal (RD) is applied, the first multiplexer (429) also comprising a data output connected to the data input of the i-th flip-flop (403) , a first data input connected to the output of the second gate (428) and a second data input connected to the output (Q) of a flip-flop adjacent to the i-th flip-flop (403) and to a first input of the second door (428), a second input of the second door (428) being connected to the output of the first door (422), the inputs of the first door (422) being respectively connected to the data input terminal (420 ) and at the s nettle of the first (400) or the Nlème (415) flip-flop, i being an integer between 1 and Nl, and the second multiplexer (435) also comprising a data output connected to the data input of the Nth (415) or 1st (400) flip-flop, a first data input connected to the output of either the 1'e "(400) flip-flop or of the Nlème (415) flip-flop and a second data input connected to the output of the first door (422).   8. Circuit according to claim 1, characterized in that it comprises circuit B and circuit C, and in that the connecting means comprise: - the sixth door (426) comprising a first input connected to the terminal selection input (418) via an inverter, and a second input connected to the output of the kth flip-flop (401), - the second multiplexer (435) comprising two data inputs connected respectively to the output of the sixth gate (426) and at the data output (Q) of the first (400) flip-flop or of the Ni6me flip-flop (415), a selection input connected to the selection input terminal (418) to receive the signal RD, and a data output connected to the data input (D) of the Nth flip-flop (415) or to the data input (D) of the 1st flip-flop (400), - a third multiplexer (433) comprising a data output connected to the data input (D) of the jth flip-flop (414) , a first data input connected to the output of the third gate (432) and a second data input connected to the output (Q) of a flip-flop adjacent to the jth flip-flop (414) and to a first input of the third door (432), a second input of the third door (432) being connected to the exit from the sixth door (426).   9. Circuit according to claim 1, characterized in that it comprises circuits A, B and C, and in that the connecting means comprise: - the fourth door (434), - the fifth door (424) comprising two inputs connected respectively to the selection input terminal (419) via the inverter (423) and to the output of the first door (422), the second input of the first door (422) being connected to the output of the 1st flip-flop (400) or at the output of the Nlein flip-flop (415), - the sixth door (426) whose inputs are connected respectively to the output (Q) of the ki n "flip-flop (401) and the selection input terminal (419), and the output of which is connected to the first input of the fourth door (434) and to the second input of the third door (432), - the first multiplexer (429), its data output being connected to the output (Q) of the iieI (403) toggles, its first data input being conn ected at the output (Q) of a flip-flop adjacent to the i mó flip-flop (403) and at the input of the second door (428), its second data input being connected to the output of the second door (428) , - the third multiplexer (433), its data output being connected to the output (Q) of the jth flip-flop (410), its first data input being connected to the output (Q) of a flip-flop adjacent to the output (Q) of a flip-flop adjacent to the jieme flip-flop (410) and to the first input of the third door (432), its second data input being connected to the output of the third door (432), and - the second (435) multiplexer, its output being connected to the data input of the Nth flip-flop (415) or to the data input of the 1st flip-flop, its first data input being connected to the output of the 1t flip-flop (400 ) or at the output of the Nieme flip-flop (415), its second data input being connected to the output tie of o30 the fourth door (434), the selection inputs of all the multiplexers being connected together to the second selection input terminal (418) to receive   the second selection signal (RD).   10. Chip card, characterized in that it comprises a multifunction circuit according to one of claims 1 to 9.