FR2724792A1 - DATA COMPRESSION METHOD USING REVERSIBLE IMPLANTED ELEMENTARY WAVES - Google Patents

Abstract

The invention relates to a method for encoding and decoding data. The method produces transformed signals in response to input data (101). The transformed signals are obtained using a reversible elementary wave transformation (102). The decomposition of the input data is carried out using a non-minimum length reversible filter (103). This filter includes several one-dimensional filters.

Description

The present invention relates to compression and

  data decompression; more particularly, the invention relates to a method and apparatus for encoding and decoding data with or without loss in a

  compression and decompression system.

  Data compression is an extremely useful tool for recording and transmitting large amounts of data. For example, greatly reduces the time required for the transmission of an image, for example the transmission of a document in fax, when using a compression

  to reduce the number of bits needed to re-create imagc.

  There are many different techniques of data compression. Compression techniques fall into two broad categories, lossy coding and coding and lossless. Lossy coding means coding that causes loss of information, so there is no guarantee that the original data can be reconstructed perfectly. In lossy compression, the goal is that changes to the original data are not detrimental or detectable. In lossless compression, all the information is kept and the data is compressed in a way that

allows a perfect reconstruction.

  In lossless compression, intensity data or input symbols are converted into output codewords. The input signals may include image data, audio data, one-dimensional data (e.g. spatially and temporally varying data), two-dimensional data (e.g., data that varies in two directions space or in a direction of space and time), or multidimensional and / or multispectral data. If the compression is successful, the coded words are represented using fewer bits than the number necessary to form the uncoded input symbols (or the intensity data). Lossless coding methods include coding dictionary methods (eg Lempel-Ziv), memory point length coding, enumerative coding, and entropy coding. In lossless image compression, compression is based on predictions or contexts, plus coding. The JBIG compression standard for fax machines and DPCM (differential pulse code modulation, which is an option of the JPEG standard) for continuous-tone images are examples of lossless compression applied to images. In lossy compression, input symbols or intensity data are quantized before conversion to output codewords. Quantification aims at preserving the desired characteristics of the data while eliminating the unimportant characteristics. Before quantization, the lossy compression system often involves a transformation that achieves some compaction of energy. The JPEG standard is an example of a lossy encoding method for image data. Recent advances in the processing of image signals continue to focus on the need for effective forms and

  accurate for data compression coding.

  Various forms of pyramidal or signal transformation treatments have been proposed, which include multiresolution pyramidal processing and elemental wave pyramidal processing (also known as "Wavelet" treatment). These forms are also related to subband processing and hierarchical processing. Elemental wave pyramid processing of image data is a particular type of multiresolution pyramidal processing that can use quadrature mirror filters (QMF) to produce subband decomposition of an initial image. It is noted that there are other types of non-QMF elementary waves. For further infmatio on elemental wave processing, see Antonini, M., et al. , "Image Coding Using Wavelet Transform", IEEE Transactions on Image Processing vol. 1, No. 2, April 1992; and Shapiro, J., "An Embedded Hierarchical Image Coder Using Zerotrees of Wavelet Coefficients", Proc. IEEE Data

  Compression Conference. p. 214-223, 1993.

  A problem encountered in most prior art elementary wave processing is that a large memory is required to record all data during processing. In other words, in order to perform elemental wave processing, all the parameters must be examined before the encoding is applied to the data. In such a case, no data is delivered until all the data has been processed at least once. In fact, elemental wave processing typically involves several passes of the data. Because of this, a large memory is often needed. It would be desirable to be able to use elemental wave processing while avoiding having to use a large memory. In addition, it would be desirable to be able to carry out the treatment by elementary waves

  using only one pass of the data.

  Many implementations of transformations by elementary waves or subbands require filters under a particular canonical fome. For example, the low-pass and high-pass filters must be the same length, the sum of the squares of the coefficients equal to 1, and the high-pass filter must be the inverse of the low-pass filter. time and frequency, etc. (see U.S. Patent No. 5,014,134 issued May, 1991). It would be desirable to have a wider class of filters. More precisely, it would be desirable to implement implementations of elementary wave or subband transformations using low-pass and high-pass filters which do not have the same length, whose sum of the squares of the coefficients are not necessarily equal to 1, the high-pass filter need not necessarily be the inverse of the low-pass filter in time and frequency, etc. The invention provides lossy or lossy compression that utilizes a conversion that provides good energy compaction. The invention also allows data modeling in the space / frequency joint domain (the domain of elementary wave transformation), which allows efficient compression. It is also permissible a transmission being carried out as and with a speed or a rate of distortion left to the choice of the user, after the coding. There is described a method and apparatus for encoding and decoding data. The invention includes a method and apparatus for producing transformed signals in response to input data. According to one embodiment, the transformed signals are produced using a reversible elementary wave transformation. The invention also includes a method and apparatus for compressing the transformed signals into data representing a compressed, lossless version of the input data. According to one embodiment, the invention decomposes the input data using a reversible filter of non-minimum length. The decomposition can be carried out at

  using multiple one-dimensional filters.

  The invention also includes a method and apparatus for performing implantation encoding (also known as embedded coding) of the transformed signals. The implantation coding according to the invention comprises arranging the series of coefficients and performing an implementation of the degree of significance (generally corresponding to the

  weight) of the bits on the transformed signals.

  The invention also includes a method and apparatus for decompressing the version of the compressed input data without loss of transformed signals. The invention also allows a compression of the signals

  lossy input, by truncation of compressed data without losses.

  The invention also includes a method and apparatus for producing the input data from the transformed signals by putting them in the form of a reconstructed version of the input data, using a transformation by

  reversible elementary waves.

  The following description, designed as an illustration of the invention, aims to

  to give a better understanding of its features and benefits; it is based on the accompanying drawings, among which: Figure IA is a block diagram of an embodiment of the coding part of the coding system according to the invention; FIG. 1B is a block diagram of one embodiment of the implementation of bit significance, according to the invention;

  FIG. 2A is a block diagram showing a system of analysis-

  elementary wave synthesis; FIG. 2B illustrates direct and inverse representations of transformation systems applying to the filtering by reversible filters of minimum length without overlap; Figures 3A to 3D illustrate the results of performing a four-level decomposition; Fig. 4A is a block diagram showing a three-level pyramidal transformation; Fig. 4B is a block diagram showing a two-dimensional two-dimensional transformation; Fig. 4C is a block diagram showing two-dimensional filters performing multiresolution type decompression; Fig. 4D is a block diagram showing a system that uses the reversible elementary waves of the invention; FIG. 4E shows functional diagrams of an improvement and analysis system using the reversible elementary waves of the invention; Figure 5 illustrates a branched structure of elementary wave coefficients; Figs. 6A and 6A (continued) show a flowchart of an embodiment of the single-list zero-zerotic ("zerot") modeling for performing the coding according to the invention; Fig. 6B and 6B (continued) show a flowchart of an embodiment of the single-list zero-branch modeling that performs the coding according to the invention using a reduced flag memory; FIG. 6C is a flowchart of an embodiment of the zero-list single-lane modeling for decoding according to the invention; Fig. 6D is a flowchart of an embodiment of the single-list zero-branch modeling which performs the decoding according to the invention using reduced flag memory; Fig. 7A is a flowchart of an embodiment of the horizon type modeling for performing the coding according to the invention; Fig. 7B is a flowchart of an embodiment of the horizon type modeling that performs the coding according to the invention using a reduced flag memory; Figure 7C is a flowchart of the horizon type modeling for performing the decoding according to the invention; Fig. 7D is a flowchart of horizon type modeling which performs decoding according to the invention using reduced flag memory; Fig. 8A is a flowchart of a pass B embodiment for performing the coding according to the invention; Fig. 8B is a flowchart of a pass B embodiment which performs the coding according to the invention using a reduced flag memory; Fig. 9A is a flowchart of a pass B embodiment for performing the decoding according to the invention; Fig. 9B is a flowchart of a pass B embodiment which performs decoding according to the invention using a reduced flag memory; FIG. 10 is an embodiment of the direct type elementary wave filter according to the invention; Fig. 11 is a block diagram showing an embodiment of an inverse type elementary wave filter according to the invention; Fig. 12 shows an image and coefficients placed in a line buffer in the case of a four-level pyramidal decomposition; Fig. 13 is a block diagram of an elementary wave filtering embodiment using a filter control unit; Fig. 14 is a block diagram of another embodiment of elementary wave filtering using a filter control unit; Figure 15 illustrates the assignment of memory groups providing horizontal and vertical accesses; Fig. 16 illustrates the filtering operation associated with a two-level decomposition; Figure 17 is a block diagram of one embodiment of the context model according to the invention; Fig. 18 is a block diagram of an embodiment of the sign / amplitude formatting unit according to the invention; Fig. 19 is a block diagram of an embodiment of the amplitude storage unit according to the invention; Fig. 20 is a block diagram of one embodiment of the degree of significance detection unit according to the invention; Fig. 21 is a block diagram of an embodiment of the branch storage unit according to the invention; Fig. 22 is a block diagram of one embodiment of the coefficient shift unit according to the invention; Fig. 23 is a block diagram of another embodiment of the degree of significance detection unit according to the invention, which uses an alignment of 1.5; Fig. 24 illustrates the dynamic assignment of the coded data memory for single-pass operation; Figs. 25A and 25B show a flowchart of one embodiment of the encoding process according to the invention; Figs. 26A and 26B show a flowchart of an embodiment of the decoding process according to the invention; Figs. 27A and 27B show a flowchart of one embodiment of the process of modeling each coefficient for both the encoding and decoding processes according to the invention; Figs. 28A and 28B show a flowchart of another embodiment of the encoding process according to the invention; Figs. 29A and 29B show a flowchart of another embodiment of the decoding process according to the invention; Figs. 30A and 30B show a flow chart of another embodiment of the process of modeling each coefficient in the encoding and decoding processes according to the invention; and FIG. 31 is an embodiment of the multipliers associated with the frequency band serving for the alignment of the coefficients according to the invention. We will now describe a method and apparatus for compression and

  decompression. In the following detailed description of the invention,

  many particular details are specified, such as types of encoders, numbers of bits, signal names, etc., so as to give a complete understanding of the invention. Those skilled in the art will understand, however, that the invention can be practically implemented without these particular details. In other cases, well known structures and devices are presented in the form of functional diagrams, and not in detail, so as to avoid complicating the

description of the invention.

  Parts of the following detailed description are

  presented in the form of algorithms and symbolic representations of operations performed on data bits within a memory

  computer. These descriptions and representations based on algorithms are the

  means used by those skilled in the data processing business to communicate in the most effective manner, to other specialists, the substance of their work. Here, as is generally the case, an algorithm is designed as a coherent sequence of operations leading to a desired result. These operations are operations requiring physical manipulations of material quantities. Ordinarily, although not necessary, these quantities take the form of electrical or magnetic signals that can be recorded, transferred, combined, compared, and processed in a variety of ways. It has sometimes proved convenient, mainly for reasons of common use, to refer to these signals as bits, values, elements, symbols, characters, expressions, numbers, and so on. It must be borne in mind, however, that all these terms and other similar terms must be associated with material quantities.

  and are only convenient labels applied to these quantities.

  Unless specifically stated otherwise, as will become evident in the following discussion, it will be understood that throughout the invention discussions using terms such as "processing", "calculation", "determination", "display", or others, refers to the action and processes of a computer system, or similar electronic computing device, which within computer system registers and memories manipulate data representing (electronic) material quantities and transform them into other data similarly representing material quantities, within the memories and registers, or other means of recording information,

  transmission or display devices of the computer system.

  The invention also relates to an apparatus for carrying out the indicated operations. Such an apparatus may be specially constructed for the purpose intended, or it may be constituted by a computer of universal type specially

  activated or reconfigured by a computer program stored in the computer.

  The algorithms and displays presented here are not intrinsically related to any particular computer or device. Universal type machines may be used in connection with programs according to the teachings presented herein, or it may be convenient to construct a more specialized apparatus for performing the desired process operations. The

  structure needed for this variety of machine will appear in the description

  next. In addition, the invention is not described in connection with a particular programming language. It will be understood that a variety of programming languages can be used to implement the teachings of

  the invention, as described below.

  SUMMARY OF THE INVENTION The invention relates to a compression / decompression system having a coding portion and a decoding portion. The coding portion is responsible for coding input data, which is intended to create compressed data, while the decoding portion is responsible for decoding previously coded data, which is intended to produce a reconstructed version of the initial input data. . The input data can include a variety of data types, for example images (still or video), audio signals, and so on. In one embodiment, the data is digital data data; however, digitized analog data, text data formats, and other formats are possible. With respect to the coding portion and, or the decoding portion, the data source may be a

  memory or a transmission channel.

  According to the invention, elements of the coding part and / or the decoding part can be implemented in the form of hardware circuits or

  in the form of software, as it is used in a computer system.

  The invention provides a lossless compression / decompression system.

  The invention can also be configured to perform a

  compression / decompression with losses.

  Fig. 1A is a block diagram of one embodiment of the coding part of the system. It is noted that the decoding part of the system exerts

  the same action in reverse order, with respect to the flow of data.

  As can be seen in FIG. 1A, input image data 101 is received by an elementary wave transformation block 102 ("wavelets"). The output of the elementary wave transformation block 102 is coupled to an "embedded coding" block 103 of the bit significance level. In response to the output signal of the elementary wave transformation block 102, the bit significance level implementation block 103 produces at least one bit stream that is received by an entropy encoder 104. In response to the input signal provided by the block 103 of implementation of the degree of significance of the bits, the

  entropy encoder 104 produces a coded signal stream 107.

  In one embodiment, the bit significance level implementation block 103 comprises a sign / amplitude formatting unit 109, a frequency-based context model 105, and a context model 106 based on together on the geometric space and the frequency, as shown in FIG. 1B. In one embodiment, the space-based and frequency-based context model 106 includes a horizon type context model. In some embodiments, the block 105 associated with the frequency-based context model includes a pattern

  Zero branching (also known as the "zerotree" model).

  In another embodiment, the frequency based context model 105 includes a branch pattern according to the degree of significance. The sign / amplitude formatting unit 109, the frequency-based context model 105, and the space-based and frequency-based context model 106 (SF) I perform an implementation encoding of the significance level of the signals. bits according to the invention. The input of the sign / amplitude formatting unit 109 is coupled to the output of the elementary wave transform coding block 102. The output of the sign / amplitude formatting unit 109 is coupled to a switch 108. The switch 108 is coupled to provide the output signal of the sign / amplitude format unit 109 to the input. the frequency-based modeling block 105 or the space-based and frequency-based modeling block 106. The outputs of the frequency-based coding block 105 and the horizon-order coding block 106 are coupled to the entropy encoder 104 input. The entropy coder 104 produces the

  encoded output signal stream 107.

  Return to Figure 1A. According to the invention, the image data 101 is received and encoded by transformation using reversible elementary waves in the elementary wave transformation block 102, as defined hereinafter, so as to produce a series of coefficients. representing a decomposition of the multiresolution type of the image. These coefficients are received by block 103

  implementation of the degree of significance of the bits.

  The block 103 for setting the degree of significance of the bits orders the coefficients and converts them to the sign / amplitude format, and then, depending on their degree of significance (as described below), the coefficients thus formatted are

  subjected to the combination of different methods of modeling by implantation.

  According to the invention, the formatted coefficients are subjected to one or the other of two methods of modeling by implantation (for example modeling

  based on frequency and JSF modeling.

  In one embodiment, formatted coefficients are subjected to frequency-based modeling or space-based and frequency-based modeling. When the input data comprises image data having a plurality of memory arrays, according to the invention, a number of memory arrays are encoded according to the frequency-based modeling, while the remaining memory arrays are encoded according to the JSF modeling. . The decision which process is used and on which memory planes is used can be linked to a user parameter. In one embodiment, the higher order memory arrays of the coefficients are ordered and encoded using frequency-based modeling according to the invention. In the frequency-based context model method, according to the invention, the prediction of the degree of significance of the bits of the coefficients is associated with the pyramidal structure of the elementary wave. The lower order memory banks of the coefficients are ordered and encoded using the context model based jointly on space and frequency, according to the invention. JSF modeling, for example horizon type modeling, offers advantages over frequency-based coding for memory schemes that are in a lesser

  correlation with frequency relationships of the domain of the frequency.

  The results of implantation coding of the degree of significance of the

  bits are decisions (or symbols) to be encoded using the entropy encoder.

  In one embodiment, all decisions are sent to a single encoder. In another embodiment, the decisions are labeled according to the degree of significance, and for each degree of significance the decisious are

  processed by multiple coders of different coders (hardware or virtual).

  The bit streams resulting from block 105 of the frequency-based context template and block 106 of the JSF context template are encoded, using the entropy encoder 104, in the order of the degrees of significance. In one embodiment, the entropy encoder 104 may comprise a binary entropy encoder. In one embodiment, the entropy encoder 104 comprises an encoder Q, an encoder B, as defined in US Pat. No. 5,272,478, or an encoder as described in the United States patent application. United States No. 08/016035, entitled 'Method and Apparatus for Parallel Decoding and Encoding of Data', and filed on February 10, 1993. For more information on the Q-encoder, see Pennebaker, WB, et al., "An Overview of the Basic Principles of the Q-coder Adaptive Binary

  Arithmetic, "IBM Journal of Research and Development Vol 32, pp. 717-26, 1988.

  In one embodiment, a single encoder produces a single output coded signal stream. In another embodiment, multiple encoders (hardware or virtual) produce multiple data streams (hardware or virtual). Elementary Wave Decomposition The invention initially decomposes an image (in the form of image data) or another data signal using reversible elementary waves. According to the invention, a reversible elementary wave transformation comprises the implementation of an exact reconstruction system formulated in integer arithmetic, so that a signal with integer coefficients can be reconstructed without losses. Because it uses reversible elementary waves, the invention is able to achieve lossless compression using finite precision arithmetic. The results obtained by applying the reversible elementary wave transformation to the image data consist of a series of coefficients. In one embodiment of the invention, the reversible elementary wave transformation is implemented using a set of filters. In one embodiment, the filters are respectively a low pass filter with two intermediate taps and a high pass filter with six intermediate taps. In one embodiment, these filters are implemented using only addition and subtraction operations (plus a bit offset by hardwired means). In addition, according to the invention, the high-pass filter produces its output signal using the results of the low-pass filter. The resulting high-pass coefficients are only a few bits higher than the resolution of the pixels and the low-pass coefficients have the same resolution as the pixels. Since only the low-pass coefficients are repeatedly filtered in a pyramid decomposition, the resolution does not increase

  in multi-level decompositions.

  An elementary wave transformation system is defined by a pair of finite impulse response analysis filters ho (n), hl (n), and a pair of finite impulse response synthesis filters go (n), gl (n). ). According to the invention, h0 and go are low-pass filters and h1 and g are high-pass filters. A block diagram of the elementary wave transformation system is shown in Figure 2A. As can be seen in FIG. 2A, for an input signal x (n), the analysis filters h0 and h1 are applied and the output signals are subjected to a "decimation" of factor 2 (are sub- critically sampled) so as to produce the transformed signals yo (n) and yl (n), which will be referred to here as low-pass and high-pass filtered coefficients, respectively: the analysis filters and the decimation blocks, or subsampling, which they are associated with, form the analysis part of the elementary wave transformation system The coding / decoding device contains all the programs and processing logic that execute in the transformed domain (by example, prediction, quantization, coding, etc.) The elementary wave transformation system shown in FIG. 2A also includes a synthesis part in which the transformed signals are oversampled by a factor of 2 (for example insert a zero after each term), then go into synthesis filters, go (n) and gl (n). The low-pass filtered coefficients yo (n) are sent in the low-pass synthesis filter go and the high-pass filtered coefficients (yl) n are sent in the high-pass filter gl. The output signals of the filters go (n) and

  gl (n) are combined to produce x (n).

  While under-sampling and oversampling are performed in some embodiments, in others, filters are used so as not to perform calculations rendered unnecessary by downsampling and oversampling. The elementary wave transformation system can be described as a function of the transformation Z, where X (Z), X (Z) are respectively the input and output signals, Y0 (Z), Y1 (Z) are the signals low-pass and high-pass filtered transforms, H0 (Z), H1 (Z) are the high-pass and low-pass analysis filters, and finally Go (Z), G1 (Z) are the synthesis filters low pass and high pass. If there is no alteration or quantization in the transformation domain, the output signal X (Z) of Figure 2A is given by: X (Z) = 1 [H0 (Z) G, (Z) + H (Z) G (Z)] X (Z) +

  12 [Ho (-Z) Go (Z) + H1 (-Z) G1 (Z)] X (-Z).

  According to the invention, the second term of X (Z), which will be called the term "spectrum folding", is canceled because the synthesis filters are defined as being the quadrature mirrors of the analysis filters. , that is to say:

{G0 (Z) = H1 (-Z)

G1 (Z) = -H0O (-Z)

  which gives, for the coefficients of the filters, go (n) = (-1) nhl (n)

g l (n) = - (- 1) nh0 (n).

  Thus, for pairs of filters which are respectively their quadrature mirrors, the following output signal is obtained after substitution:

  X (z) = 2 [H0 (Z) H1 (-Z) -HI (Z) HO (-Z)] X (Z).

  Therefore, in the quadrature mirror system according to the invention, the output signal is defined according to the only analysis filters. The elementary wave transformation is recursively applied to the transformed signals in which the output signals produced by the filters are used as input signals of the filters, directly or indirectly. In the embodiment described, only the filtered low-pass filtered component yO (n) is recursively transformed so that the system is pyramidal. A

  example of such a pyramid system is shown in Figure 4A.

  The Z transformation is a convenient notation for expressing the action of hardware and / or software over the data. Multiplication by Z-m forms a delay model of m clock cycles in hardware equipment and matrix access to the same previous element in software. Such implementations in the form of hardware equipment involve memories, communication channel stages, offset devices, registers, and so on. According to the invention, the signals x (n) and x (n) are identical to a multiplicative constant and a delay term after, that is to say in the transformation terms Z,

X (Z) = cZ-X (Z).

  This is what is called an exact reconstruction system. Thus, in one embodiment of the invention, the transformation by elementary waves

  initially applied to the input data is reconstructible exactly.

  An embodiment of the invention using the Hadamard transformation is an exact reconstruction system which, in standardized form, has the following representation in the Z domain:

1

Ho H (Z) - = l (+ Zi)

H1 (Z) = 2 (1Z-1)

  After substitution, the output signal is

X (Z) = Z-IX (Z)

  which is obviously an exact reconstruction. For more information on the transformation of Hadamard, see Anil K Jain,

  Fundamentals of Image Processing, p. 155.

  A reversible version of the transformation of Hadamard will here be called the transformation S. For more information on the transformation S, we will refer to Said, A. and Pearlman, W. "Reversible Image Compression via Multiresolution Representation and Predictive Coding," Dept. of Electrical, Computer and Systems Engineering, Renssealacr Polytechnic Institute, Troy, NY, USA. 1993. Since the Hadamard transformation is an exact reconstructed transformation, the following non-normalized version (which differs from the Hadamard transformation by constant factors) is also an exact reconstruction transformation: I ho (Z) = 1 (1+ Z-) hl (Z) = lZ-1 Given the samples of the input signal such that xo, xl, the transformation S is a reversible implementation of this system in the form: YO (O) = L (x (O) + x (1)) / 2 Y1 (O) = x (O) - x (1)

  The notation. J means a rounding down, or a section

  cation, and corresponds to what is sometimes called a "floor function." Similarly, the ceiling function F.1 means a rounding up to

the next integer.

  The proof that this implementation is reversible stems from the fact that the only information lost during the approximation is the least significant bit of x (O) + x (1). Since the least significant bits of x (0) + (x1) and x (O) -x (1) are identical, they can be reconstructed from the high-pass output signal Y1 (0). In other words, X (0) = Yo (O) + [(Yl (O) + 1) / 2j x (1) = Yo (O) - [(Yl (O) -l) / 21 The transformation S is a non-overlapping transformation that uses reversible filters of minimum length. Filters of minimum length are formed of a pair of filters, the two filters having two intermediate taps. The minimal length transformations do not give a good energy compaction. Minimal length filters produce a non-overlapping transformation since the length of the filters is equal to the number of filters. Overlap transformations use at least one filter that has a length greater than the number of filters. Overlapping transformations that use longer filters (not having

  the minimum length) can give better compaction of energy.

  The invention provides reversible filters of non-minimal length that allow

  a transformation without overlap.

  Another example of an exact reconstruction system is the two / six (CS) transformation, which has, in the Z domain, the definition: t H (Z) => 22 (1 + Z-1)

{H (Z) = (-1-Z-1 + 8Z-2-8Z-3 + Z4 + Z-5) -

  After substitution, the output signal is:

X (Z) = 2Z-3X (Z),

  which is an exact reconstruction transformation.

  A rational non-standard version of the IS transformation includes: f h (Z) = (1 + Z-1) hl (Z) = 8 (- Z-1 + 8Z-2-8Z-3 + Z-4 + Z -5) If x (O), x (1), ... x (5) are six samples of the signal, then the first three low-pass filtered coefficients yo (O), yO (1), yo (2) and the first high-pass filtered coefficient Yl (O) are given by: yo (O) = L (x (0) + x (1)) / 2J yo (1) = L (x (2) + x (3) )) / 2J yo (2) = L (x (4) + x (5)) / 2J

  y, (o) = L (- (x (0) + x (1))) + 8 (x (2) - x (3)) + (x (4) + x: (5)) / 8J.

  However, the simple direct implementation of the rational non-standard version of the TS transformation is not reversible. The following example shows that this implementation is not reversible locally. A longer sequence can be constructed as an example of the general case. Since - (x (O) + x (1)) + (x (4) + x (5)) "- yo (O) + yo (2) because of the rounding involved in the calculation of yo (0) ) and yo (2), this transformation is not reversible when

uses local information.

  For example, if x (0) = 1, x (1) = 1, x (2) = 3, x (3) = 1, x (4) = 1, x (5) = 1, then: y0 ( O) = L (1+ 1) / 2J = 1 yo (1) = L (3 + 1) / 2J = 2 yo (2) = L (1 + 1) / 2j = 1 y, (O) = [ L [- (+ +1) +8 (3-1) + (1 + 1)] / 8J = L (-2 + 16 + 2) / 8J = 2 and if x (0) = 1, x (1 ) = 2, x (2) = 4, x (3) = 1, x (4) = 1, x (5) = 1, then yo (O) = [(1 + 2) / 2J = 1 y0 ( 1) = L (4 + 1) / 2j = 2 y0 (2) = L (1+ 1) / 2J = 1 y (O) = L [[- (1 + 2) +8 (41) + (1) +1)] J / 8 = L (-3 + 24 + 2) / 8J = L [23 / 8J = 2 Since yo (O), yo (1), yo (2) and yl (O) are the same for two different groups of input signals x (0), ... x (5), the transform is not reversible, since, given yO (0), ... Yl (0), we can not do not determine, from this local information, which of the two groups was applied as input. (Note that it can be proved that the transformation is not reversible using global information for all the coefficients.) We will now consider a reversible transformation TS, which we

  will call here an RTS transformation, which performs a pass filtering operation.

different top.

  If x (0), x (1), x (2), x (3), x (4), x (5) are 6 samples of the signal, then the first three low-pass filtered coefficients y 0 (0), y0 (1), y0 (2) and the first high-pass filtered coefficient Yl (0) are respectively given by: y o0 (O) = L (x (o) + x (1)) / 2j yo (o) = L (x (2) + x (3)) / 2J yo (2) = L (x (4) + x (5)) / 2J yi (O) = L (-L (x (O) + x (1)) / 2j + 4 (x (2) - x (3)) + L (x (4) + x (5)) / 2j) / 4j

  = L (-yo (O) + 4 (x (2) - x (3)) + y O (2)) / 4j-

  since x (2) -x (3) = y, (O) -L- (yo (0) + y0 (2)) / 4J then x (2) -x (3) is perfectly well known. Since yo (1) = Kx (2) + x (3), x (2) -X (3) and x (2) -x (3) are defined above, we can reconstruct x (2) and x (3) since the bits

  the least significant of x (0) + x (1) and x (O) -x (1) are identical.

  In particular, let d (O) = x (2) - x (3) = y, (o) - L (-y0 (o) + yo (2) / 4) J x (2) = y0 (1) ) + [(d (O) + 1) / 2J x (3) = yo (1) + (d (O) -1) / 21, An embodiment of the direct filter associated with the RTS transformation is represented in FIG. Appendix A, which is implemented using the language of

"C" programming.

  It is noted that, from the mathematical point of view, the equation: ## EQU1 ## and the equation 4 (2 (-1 Z1) + 4 ( Z-2 Z-3) + (Z + Z-s5))

  are the same when executed in finite-precision arithmetic.

  The reason that the second equation represents a reversible filter is obvious when it is physically used in integer arithmetic. Examples of hardware-type implementation for the low-pass filter

  and the high-pass filter are presented in connection with FIGS. 10 and 11.

  It is noted that in the transformation S as well as in the transformation RIS, the low-pass filter is implemented so that the input signal x (n) has the same interval as the output signal y0 (n) . For example, if the signal is an 8-bit image, the output signal of the low-pass filter is also 8-bit. This is an important property for a pyramidal system in which the low-pass filter is repeatedly applied, since in the prior art systems the output signal range is larger than that of the input signal, which makes it difficult to successively apply the filter. In addition, the low-pass filter has only two intermediate taps, which make it a non-overlapping filter. This property is important for implementation in form

  material, as will be explained below.

  In one embodiment, in connection with the RIS transformation, the low-pass filter and the high-pass filter are defined by: hi (Z) = (1 + Z-1) + 4 (Z2 Z3) (Z4 Thus, the results from the low-pass filter can be used twice (in the first and third term) in the high-pass filter.

  only two more additions to arrive at the results of the pass filter.

  above. Many non-overlapping non-minimal length reversible filters can be used in the invention. Direct and inverse representations of the transformation system providing filtering using reversible filters of minimum length without overlap are shown in Figure 2B. For example, filters of the following class may be used in the invention. For an integer L> z, d (O) = x (2 (LL / 2j + 1)) - x (2 ([L / 2J + 1) + 1), yo (O) = L (x (o) + x (l)) / 2J y (1) = L (x (2) + x (3)) / 2J yo (L - 1) = L (x (2L (L - 1) / 2J) + x (2L (L-1) / 2j + 1)) / 2] and L'42J Ll úE aiyo (i) + bd (O) + lcyo (j) Y (O) = = o i _ = - L / 2J. 2 k The length of the high-pass filter is 2L If L is odd, the filter can get closer to a symmetrical filter. If ai, b, ci and k are integers and k <b, then the filter is reversible. If ai, b, ci and k are powers of two (or the negation or the complement of a power of two), then we can simplify the implementation of the filter. If k = b (independently of the values of ai and dc ci), alois, we minimize the interval of the output signal of the low-pass filter Yl- For each ai, if there exists exactly a value cj for which aj = - c, then the high-pass filter will have no response for a constant input signal. If ai = -cj when j- (L, -1) = i, then the filter can move closer to a symmetric filter. Another useful property is: i [(as) (2i) "+ (ai) (2i + 1) m] + (b) (2 (L / 2J + 1)) 1 = 0 - (b) (2 ( L / 2J + 1) + '[c. (2j) + c1 (21 + 1) m] = O

= LL / ZJ.2

  This causes the high-pass filter to have no response to a linearly varying input signal when m = 1 and has a quadratically varying input signal when m = 2, etc., om is the state of moment. This property is the reason of principle that the RTS transformation has a better energy compaction than the transformation S. While filters must satisfy a minimum of constraints to be reversible, with regard to different applications, one can use filters that do not satisfy any of the other properties, some of the other properties, or any other properties. In some embodiments, one of the following exemplary high pass filters is used. The filters are indicated in a notation that simply enumerates the integer coefficients of the version

  rational filter, because it is necessary to avoid complicating the description of the invention.

1 1-4 -4 16-164 4-1-1

1 1-3-3 8-8 3 3-1-1

-1-1 0 0 16-160 0 1 1

  -1 -1 4 4 -16 -16 256 -256 16 16 -4 -4 1 1

3-22-2 128-128 22-2-3-3.

  The last filter is referred to here as the IT filter (two / ten) and has the property of not having a response to a function that grows cubically. Note that since 22 = 16 + 2x3 and 3 = 2 + 1, this filter can be set

  using seven additions and subtractions in total.

  The strict reversibility requirements of filters can be relaxed by noting the following. The high-pass coefficients are coded and decoded in the same order. The pixel values corresponding to previously decoded high-pass coefficients are accurately known, so that they can be used in the current high-pass filtering. For example, we can use the filter

  next when using a dithering order.

  H1 (M) = '[-' (I + Z-) J + [(8 (Z2-z-) + (Z- + z-5)) The use of a single fixed high-pass filter n ' is not necessary. Adaptive filters or multiple filters can be used. The data used to adapt filters or to make the selection among the multiple filters must be limited to the data that is available in the decoder.

special inverse filtering.

  One way to use multiple filters is to process the

  high-pass coefficients in a progressive way. Other filtering operations

  high (Y1 (0), yl (2), Y1 (4), ..) can be processed first using a reversible filter such as the high-pass filter RTS. The further processing (y1), Y1 (3), Y1 (5), ...) uses a non-reversible filter of up to 6 intermediate taps, since the exact values of the input signals applied to the overlapping part of the filter are known. For example, any of the following filters may be used:

-1 3 -3 1

-1 4 -4 1

-3 8 -8 3

1 -5 10 -10 5 -1

1 -4 8-8 4-1-

  In some embodiments, the pass filter can be replaced.

  up by a prediction / interpolation operation. A prediction / interpolation device can predict the difference between a pair of input signals using any data that is available in the decoder before a particular prediction / interpolation operation. The predicted difference is then subtracted from the actual difference of the input signals and is delivered. In one embodiment, prior art prediction methods, which are employed in the DPCM, are used.

coding in the spatial domain.

  By using the low pass and high pass filters according to the invention, a multiresolution type decomposition is carried out. The number of decomposition levels is variable and can be any. However, the number of

  levels of decomposition is commonly equal to two, three, four or five.

  For example, if we apply recursively to an image reversible elementary waves transformation, the first level of decomposition acts on the detail, or resolution, the finer. At the first level of

  decomposition, the image is decomposed into four sub-images (for example sub-images

  bands). Each subband represents a spatial frequency band. The first level subbands are designated as 1IO, LHO, HL0 and HHO. The process of decomposition of the initial image involves sub-scaling, by a factor of 2, in both the horizontal dimension and the vertical dimension, so that the first level sub-bands LL0, LHo, HL0 and HH0 each have four times less coefficients than the input signal has pixels (or coefficients) of the image, as shown for example in FIG. 3A. The sub-band LLO simultaneously contains the horizontal information of low frequency and low frequency vertical information. Typically, a large part of the image energy is concentrated in this sub-band. The sub-band LH0 contains the low frequency horizontal information and the high frequency vertical information (for example the information associated with the horizontal edges). The HLO sub-band contains the high frequency horizontal information and the low frequency vertical information (for example the information associated with the vertical edges). HHio0 subband contains high frequency horizontal information and high vertical information

  Frequency (eg information about diagonals or textures).

  Each of the second, third and fourth successive lower levels of decomposition is generated by decomposing the low frequency subband LL of the previous level. This first-level LLO0 sub-band is decomposed to produce second-level LL1, LH1, HL1, and HH1 sub-bands associated with moderate details. Similarly, sub-band LL1 is decomposed to produce LL2, LH2, HL2 and HH2 sub-bands of the third level for coarse detail. The LL2 sub-band is decomposed to produce third level LL3, LHI3 HL3 and HH3 sub-bands for the coarser details as shown in FIG. 3D. Because of the factor 2 subsampling, each subband of the second level has a size corresponding to 1/16 of the size of the initial image. Each sample (for example pixel) of this level represents the moderate detail of the initial image for the same location. Likewise, each sub-band of the third level has a size equal to 1/64 of the size of the initial image. Every pixel of this level

  is the relatively coarse detail of the original image for the same location.

  In addition, each subband of the fourth level has a size equal to 1/256 of the

size of the initial image.

  Since the decomposed images are materially smaller than the initial images due to downsampling, the same memory can be used to record all decomposed subbands.

  served to memorize the initial image. In other words, the initial image and the sub-

  decomposed bands L.O and LL1 are rejected and are not recorded in a

decomposition at three levels.

  There is a parent-child relationship between a sub-component

  a band representative of the coarse detail and a corresponding subband component associated with the finer level of detail immediately

after.

  While only four subband levels of decomposition have been shown, higher levels may be possible depending on the requirements of a particular system. In addition, with other transformations, for example DCT or linearly separated subbands, relationships can be defined.

parent-child different.

  The multiresolution type decomposition process may be a filtering system as described in connection with FIG. 4A. An input signal representing a one-dimensional signal of length L is low-pass and high-pass filtered by filter units 401 and 402 before being downsampled by a factor of 2 in units 403 and 404. A subsampled output signal from the unit 403 is low-pass and high-pass filtered by filter units 405 and 406 before being downsampled by a factor of 2 in respective units 407 and 406. 408. L and H subband components appear on the respective outputs of the units 407 and 408. Similarly, the output signal of the unit 405 is low-pass and high-pass filtered by units 409 and 409. 410 before being downsampled by respective units 411 and 412. Subband components L and H appear on the respective outputs of the units 411 and 412. As described above, the filters of one embodiment of the invention which are used in the subband decomposition are digital filters forming quadrature mirrors used to separate horizontal and vertical frequency bands in high frequency and low frequency bands. Figure 4B illustrates a two-dimensional two-dimensional transformation. FIG. 4C also illustrates a two-dimensional two-dimensional transformation, implemented using one-dimensional filters, such as those shown in FIGS. 10 and 11. The two-dimensional filters are applied to a

  position out of two, so as to avoid unnecessary calculations by the sub-

  sampling. In one embodiment, the unidimensional filters are

  share calculations between low-pass and high-pass calculations.

  Thus, the invention provides a compression and decompression system in which reversible filters with non-minimal length overlap are used. Figure 4D is a block diagram of an embodiment of such a system. As shown in FIG. 4D, a hierarchical decomposition is initially performed. The results of the decomposition

  hierarchical are sent to a compression device to be compressed.

  The compression performed may include vector quantization, scalar quantization, counting of memory point lengths, Huffman coding, etc. At the output of the compression device, there is data

  compressed which represent a compressed version of the initial input data.

  A decompression device can receive the data at some point in the future and decompress them. The invention then performs an inverse decomposition using reversible filters with non-overlapping lengths.

  minimum to produce a reconstructed version of the original data.

  The reversible elementary wave filters according to the invention can also be used in analysis and improvement systems, as shown in FIG. 4E. As can be seen in Figure 4E, a hierarchical decomposition is applied to input data using

  Reversible, overlapping elementary waves of non-minimal length.

  The analysis unit receives the coefficients produced by the filters and classifies them into decisions, for example, rather than coding the coefficients completely, the important information being extracted alone. For example, in a document filing system, blank pages can be recognized using only the lowest single-pass sub-band. Another example would be to use only the high-pass information from a particular sub-band for

  distinguish between the image of a text and images representing natural scenes.

  Hierarchical decomposition can be used to record multiple images, so that coarse recording is first done using coarse subbands. In another embodiment, the coefficients are subjected to an improvement or a filtering, which is followed by an inverse decomposition. We can achieve a better dive, an improvement of

  edges, a noise control, etc., using a hierarchical decomposition.

  Thus, the invention provides an elementary wave transformation which will be used in analysis and filtering / enhancement systems in the field of

  frequency and in the joint time / space domain.

  Coding by implementation of the degree of significance of the bits According to the invention, the coefficients produced as a result of the elementary wave decomposition are subjected to entropy coding. According to the invention, the coefficients initially undergo an implantation coding in which the coefficients are ordered according to a visually significant order or, more generally, ordered with respect to a certain error metric (for example a distortion metric). An error or distortion metric has a peak error and a mean squared error (MSE). In addition, the ordering can be done to favor the spatial position of significance (or weight) of the bits, because it is better adapted to the interrogation of a database, or according to a directional criterion ( vertically, horizontally, diagonally, etc.). The invention uses multiple implantation coding techniques, where part of the coefficients, having a certain degree of significance, are coded using a technique of

  coding, while the remaining coefficients are coded with other techniques.

  Frequency-based modeling and space-based and frequency-based modeling are two different implementation coding schemes used to code the coefficients produced using the elementary wave transformation according to the present invention. invention. Frequency-based modeling involves the prediction of a number of coefficients at a higher frequency than when encoding a coefficient at a lower frequency. Space-based and frequency-based modeling takes advantage of both known frequency bands and neighboring pixels (or data). One embodiment of space and frequency-based modeling, to which reference is made here, is horizon-type modeling. The data is initially put in the sign / plitu format, where the data are sorted according to their degree of significance. After the data has been sorted with respect to the given meaning metric, the data is coded. Frequency-based coding and horizon-type coding can both rely on ordering according to the bit significance level,

  but they use different methods for event coding.

  Assuming a digital signal, x (n) is represented for each x (n), by R precision bits, and the encoding implemented according to the invention encodes the most significant bit (or the most significant bits) each x (n) of the signal, then the bit having the next degree of meaning (or the bits), and so on. For example, in the case of a visually defined ordering, an image that requires a better quality in the center than in the corners or near the edges (for example some medical images) can be subjected to a coding such that the bits of lower order of the center pixels can be encoded before the order bits

  higher pixels on the edges.

  For a siting system based on bit distortion measurement of the bit significance, the binary values of the data are ordered according to the amplitude. In the case where the values are non-negative integers, as is the case for the intensity of the pixels, the order that can be used is the order of the memory planes (by going for example from the most significant memory plane at the least significant memory level). In embodiments where the negative integers by complementation to 2 are also allowed, the order of implementation of the sign bit is the same as the first non-zero bit of the absolute value of the integer. Therefore, the sign bit is ignored before a non-zero bit has been encoded. As a result, the possible values of an event of the Bit Significance System according to the invention are ternary values prior to encoding the sign bit. These ternary events are 'not significant', 'significant positive' and 'negative significant' For example, if we use the notation sign / amplitude, the number of 16 bits designating 7 is: From the point of view of the memory plane, the first twelve decisions will be 'not significant'. The first bit 1 appears in the thirteenth decision. The thirteenth decision will be "significant negative". After coding the sign bit, the possible events are reduced to binary values, namely 0 or 1. The quatozime and

  Fifteenth decisions are both "1".

  According to one embodiment of the invention, a list is used to keep track of the coefficients. In one embodiment, a 1-bit flag, called a group flag, associated with each coefficient, differentiates the coefficients whose sign bit has not yet been encoded, and the sign bit has already been encoded. In another embodiment, two or more lists may be used instead of a flag bit. In another embodiment, a

only list without flag.

  In another embodiment, no lists are used. All decisions concerning a coefficient are produced and labeled according to the degree of significance, before any decision concerning the following coefficient is produced. This eliminates the need to record all coefficients in lists. Coding and Decoding Process According to the Invention The following flow diagrams, shown in FIGS. 25A, 25B to 30A, B, describe embodiments of the coding and decoding processes.

according to the invention.

  Figures 25A and 25B show an organigram illustrating the

  process for transforming and modeling the encoder according to the invention.

  As can be seen in Figs. 25A, 25B, the encoder transformation and modeling process begins with the acquisition of input data (processing block 2501). After the acquisition of input data, the invention applies

  a reversible elementary wave filter (treatment block 2502).

  A test then determines whether another level of decomposition is desired (processing block 2503). If another level of decomposition is desired, processing continues in the process block 2504 where the reversible filter is applied to the LL coefficients resulting from the immediately preceding decomposition, and the process returns to the process block 2503. In this way the invention makes it possible to perform any number of decomposition levels. If no other level of decomposition is desired, the processing continues, in the processing block 2506, where the group flag relating to each coefficient is initialized to group A. After initialization of the group flag, the memory plane associated with the passage A, ie SA, is positioned on the most significant memory plane (max) (processing block 2507). Then, the memory plane associated with the passage B, ie SB, is positioned on the most significant memory plane coming from

  then (max-1) (processing block 2508).

  Then, a test determines whether to encode the memory array associated with the A, SA pass, with a frequency-based model (processing block 2509). If the memory array SA is to be encoded using a memory-based modal, the processing proceeds to the processing block 2510, where each cue is modeled using the frequency-based model and the encoding entropic. On the contrary, if the SA memory plane is not to be encoded using the frequency-based model, the processing continues in the processing block 2511, where each coefficient is modeled using a jointly-based model. on space and the

* Frequency and entropy coding.

  In either case, the processing continues after that in the processing block 2512, where a test determines whether the SA memory plane is greater than or equal to zero, to indicate whether it is the last memory map. If the memory map

  SA is greater than or equal to zero, the processing returns to the processing block 2509.

  Conversely, if the memory plane SA is not greater than or equal to zero, the processing continues in the processing block 2513, where a test determines whether the memory plane SB is greater than or equal to zero, so that the processing determines if the memory plane is the last memory plane to undergo a passage B. If the memory plane SB is greater than or equal to zero, the processing continues in the processing block 2509. However, if the memory plane SB is not greater than or equal to zero, the processing continues in the processing block 2514, where the coded data is transmitted on a channel or stored in a memory. After the recording or transmission of the coded data, the transformation process

  and modeling of the encoder according to the invention ends.

  FIGS. 26A and 26B illustrate a transformation and modeling process of the decoder according to the invention. As can be seen in FIGS. 26A, 26B, the process of transforming and modeling the decoder according to

  the invention begins by extracting coded data (processing block 2601).

  The encoded data may be received from a channel, memory, or other transmission system. After extracting the coded data, a group flag relating to each coefficient is initialized on the group A (processing block 2602). Following this initialization, the memory plane associated with the passage A, ie SA, is positioned on the most significant memory plane (max) (processing block 2603) and the memory plane associated with the passage B, namely SB, is positioned.

  on the next most significant memory plane (max-1) (processing block 2604).

  Then the value of each coefficient is set to an initial value of zero

(processing block 2605).

  After initializing the value of each coefficient to zero, a test determines whether or not the memory array SA is to be decoded using a frequency-based model (processing block 2606). If the SA memory plane is to be decoded using a frequency-based model, the processing proceeds to processing block 2607, where each coefficient is modeled using a frequency-based model. an entropy decoding. If the SA memory plane is not to be decoded using a frequency-based model, processing continues in the process block 2608, where each coefficient is modeled using a model

  based jointly on space and frequency and entropy decoding.

  After each coefficient has been modeled, the processing continues in the processing block 2609, where it is determined whether the memory array SA is the last memory array by means of an attempt to indicate whether or not it is higher or lower. equal to zero. If the memory plane SA is greater than or equal to zero, the processing continues in the processing block 2606. Conversely, if the plane, memory SA is not greater than or equal to zero, then a test determines whether the memory plane SB associated with the passage B is greater than or equal to zero (processing block 2610), this indicating that it is the last memory plane associated with a passage B. If this is so, the processing continues in the processing block 2606 to continue decoding. Conversely, if the memory plane associated with the passage B, ie SB, is not greater than or equal to zero, an inverse reversible filter is applied to the coefficients, starting from the coarsest level of the decomposition (processing block 2611). . A test then determines whether all levels have been subjected to inverse filtering (processing block 2612). If this is not the case, the inverse reversible filter is applied again to the coefficients, to the

  the coarsest level remaining from the decomposition (processing block 2613).

  After that, the treatment returns to processing block 2612 so that it is

  again checked if all levels were subjected to reverse filtering.

  Once all the levels have been subjected to the inverse filtering, the processing proceeds to the processing block 2612, in which the recording or

  the emission of reconstructed data takes place.

  Figs. 27A and 27B illustrate one embodiment of the modeling process of each coefficient. The described process represents the modeling process related to frequency-based modeling or JSF modeling and coding or decoding. Thus, each of the four blocks (2507, 2508, 2607, 2608) can be implemented using the modeling process of Figs. 27A and 27B. As can be seen in Figs. 27A and 27B, the process initially begins with checking whether the modeling is to be performed in a single pass (processing block 2701). If the modeling does not take place in a single pass, a test determines whether the memory plane SA is greater than the memory plane SB (processing block 2702). If this is not the case, then the process proceeds to processing block 2703, where a flag ("flag A") is cleared to indicate that a passage A should not be performed. If the memory plane SA is greater than the memory plane SB, then the processing continues in the processing block 2704, where the flag "flag A" is set to

  indicate that a passage A must be made.

  After either of the process blocks 2703 and 2704, the process proceeds to the process block 2705, where an experiment determines whether the memory plane SB is equal to the memory plane SA. If the memory plans are not equal, the invention erases a flag ("flag B") to prevent a passage B takes place

  (processing block 2705), and the treatment then proceeds to processing block 2707.

  If the memory plane SB is equal to the memory plane SA, the flag "flag B" is set to indicate that a passage B must be performed (processing block 2706), and the processing then also passes to the block of

2707 treatment.

  In the process block 2707, a test determines whether the passage flag A is set and the zero branching modeling is to be performed. If the flag indicates that a passage A is to occur and zero branching modeling is to be performed, a 'determined / undetermined' flag is initialized in the 'not determined' state for each coefficient (processing block 2708 ), and the processing proceeds to the processing block 2709. Conversely, if the passing indication flag A or the zero branching indication is set, the processing goes directly to the processing block 2709. In the block of 2709, the first coefficient is set to the variable C. Once the first coefficient is assigned the variable C, a test determines whether the passage indication flag B is set (processing block 2719). the flag of passage B (flag B) is set, the invention applies a passage B on the coefficient C (processing block 2710), and the treatment passes to the processing block 2711. Conversely, if the flag of pa ssage B is not set, then a B pass is not applied

  on C, and the treatment goes directly to processing block 2711.

  A test then determines whether the flag flag A "flag A" is set (processing block 2711). If the passage indication flag A is set, a passage A is then applied to the coefficient C (processing block 2717). Thereafter, the processing proceeds to processing block 2713. If the passing indication flag A is not set, processing continues in processing block 2713 without a passage A being applied to the coefficient C. the processing block 2713, a test determines whether the coefficient C is the last coefficient. If the coefficient C is not the last coefficient, then the treatment continues in the processing block 2714, where the next coefficient is

  is assigned variable C, and the processing proceeds to processing block 2719.

  However, if the coefficient C is the last coefficient, the processing proceeds to the processing block 2715, where a test determines whether the passing flag B "flag B" is set. If the passage flag B is set, the memory plane SB is set to be equal to the memory plane SB-1 (processing block 2716), and then the processing proceeds to the processing block 2717. If the flag indication of passage B is not set, processing continues in the process block 2717. In the process block 2717, a test determines whether the passage flag A is set. If it is set, then the SA memory plane is set to be equal to the SA-1 memory array (processing block 2718), and then the processing is terminated. Likewise, if the passage flag A is not set,

  the treatment ends then immediately.

  In some embodiments, the fact that a coefficient lying in a particular memory plane is in the group A or in the group B can be determined without the aid of a flag bit. This saves one memory bit per coefficient, which can be important for large images. Instead, we compare a mask using AND logic with a coefficient. If the result of the AND operation is zero, the bit is in group A; otherwise, it is in group B. An example of such masks is shown in Table 7 for eight memory planes. We note that these masks are the complements to 2 of the

  value 2 (memory plane + l) (without the sign bit).

  TABLE 7 Masks Memory map Mask (binary)

7,000,000

6 10000000

11000000

4 11100000

3 11110000

2 11111000

1 11111100

O 11111110

  Since independent masks can respectively be assigned to passage A and passage B (here called MA and MB), it is possible to perform as many passes A as desired before the corresponding passage B. In one embodiment with 17 memory planes, three passages A are performed, then fourteen passages A and B passages simultaneously made, and finally two passages B are performed. Since passage decisions A may typically be encoded more efficiently than passing decisions B, initially executing multiple passes A may improve the quality in the case of

lossy compression.

  Figs. 28A and 28B illustrate an embodiment of an encoder according to the invention, which uses a reduced flag memory (as described later). As can be seen in FIGS. 28A and 28B, the process of transforming and modeling the encoder begins with the acquisition of input data (processing block 2801). After the acquisition of the input data, the invention applies a reversible elementary wave filter (block of

2802 treatment).

  Then, a test determines if another level of decomposition is desired (processing block 2803). If another level of decomposition is desired, the processing continues in the process block 2804, where the reversible filter is applied to the LL coefficients resulting from the decompensation.

  immediately preceding, and the process returns to processing block 2803.

  In this way, the invention makes it possible to perform any number of levels

decomposition.

  If no other level of decomposition is desired, the processing proceeds to the processing block 2805, where the memory plane associated with the passage A, ie SA, is positioned on the most significant memory plane (max). Ensumite, the memory plane associated with the passage B, SB, is positioned on the next most significant memory plane (max-1) (processing block 2806). Then, a mask MA is set to - 2 (SA + 1) (processing block 2807) and a mask MB is set to - 2 (SB + 1) (processing block 2808). Then, a test determines whether to encode the memory array associated with the A passage, ie SA, using a frequency-based model (processing block 2808). If the SA memory plane is to be encoded using the frequency-based model, processing proceeds to processing block 2809, where one bit of each coefficient is modeled using the frequency-based model and entropy coding . Conversely, if the SA memory plane is not to be encoded using the frequency-based model, processing continues in the process block 2810, where one bit of each coefficient is modeled using a model

  based jointly on space and frequency and entropy coding.

  In either case, processing is then continued in process block 2811, where a test determines whether memory plane SA is greater than or equal to zero, indicating whether or not it is the same. last memory map. If the memory plane SA is greater than or equal to zero, the processing returns to the processing block 2808. In the opposite case, if the memory plane SA is not greater than or equal to zero, the processing continues in the processing block 2812, o a test determines whether or not the memory plane SB is greater than or equal to zero, so that the process determines if the memory plane is the last memory plane to undergo a passage B. If the memory plane SB is greater than or equal to at zero, the processing continues in the processing block 2808. However, if the memory plane SB is not greater than or equal to zero, the processing continues in the processing block 2813,

  o Coded data is transmitted on a channel or stored in a memory.

  After recording or transmitting the coded data, the process of

  transformation and modeling of the encoder according to the invention ends.

  FIGS. 29A and 29B illustrate another embodiment of the transformation and modeling process of the decoder according to the invention, in the case where a reduced flag memory is used. As can be seen in FIGS. 29A and 29B, the transformation and modeling process of the decoder according to the invention begins by extracting coded data (processing block 2901). The encoded data may be received from a channel, memory, or other transmission system. Once the coded data has been received, the memory plane associated with the passage A, ie SA, is fixed on the most significant memory plane (max) (processing block 2903) and the memory plane associated with the passage B, ie SB , is attached to the next most significant memory plane (max-1) processing block 2904). We then position the

  value of each coefficient on an initial value zero (processing block 2905).

  Then the mask MB is set to -2 (S + 1) (processing block 2902) and

  sets the MA mask to -2 (SA + 1) (processing block 2915).

  Next, a test determines whether the SA memory plane is to be decoded using a frequency-based model (processing block 2906). If the SA memory plane is to be decoded using a frequency-based model, processing proceeds to processing block 2907, where one bit of each coefficient is modeled using a frequency-based model and an entropy decoding. If the SA memory plane is not to be decoded using a frequency-based model, the processing proceeds to processing block 2908, where one bit of each coefficient is modeled using a jointly-based model. space and the

  frequency and entropy decoding.

  After each coefficient has been modeled, the processing proceeds to processing block 2909, where it is determined whether the memory plane SA is the last plane (it is checked whether it is greater than or equal to zero). If the SA memory plan is

  greater than or equal to zero, the treatment proceeds to the processing block2906.

  Conversely, if the memory plane SA is not greater than or equal to zero, then it is determined, by means of a test, whether the memory plane SB associated with the passage B is greater than or equal to zero (processing block 2910 ), which indicates that it is the last memory plane associated with a passage B. If so, the processing proceeds to the processing block 2902 for further decoding. Conversely, if the memory plane associated with the passage B, ie SB, is not greater than or equal to zero, an inverse reversible filter is applied to the coefficients starting from the coarsest level of decomposition (processing block 2911). A test then determines whether all levels have been subjected to inverse filtering (processing block 2912). If this is not the case, the inverse filter is again applied to the coefficients of the worst remaining decay level (processing block 2913). After that, the treatment returns to the processing block 2912, where an attempt is made again

  to determine if all levels have been reverse filtered.

  Once all levels have been subjected to reverse filtering, the processing proceeds to processing block 2912, in which a record or

  emission of reconstructed data takes place.

  Figs. 30A and 30B illustrate one embodiment of the modeling process of each coefficient. It is noted that, like FIGS. 27A and 27B, the process of FIGS. 30A and 30B can be used to implement the modeling operations of FIGS. 28A and 28B as well as 29A and 29D. As shown in Figs. 30A and 30B, the process first verifies that a passage A is desired and determines whether SA is greater than or equal to zero (processing block 3001). If so, the flag "flag A", which indicates that a passage A is to be performed, is set (processing block 3004), and the processing proceeds to the processing block 3002. Otherwise, the flag " to make flag A "

  is cleared (processing block 3003).

  If the memory plane SA is greater than the memory plane SB, the processing then passes to the processing block 3004, where a flag is positioned to indicate that a passage A must take place. If the memory plane SA is not greater than the memory plane SB, the processing then proceeds to the processing block 3003, where the flag

  indicating that a passage A is supposed to occur is erased. After either of the 3003 and 3004 treatment blocks, the treatment

  passes to the processing block 3002, o a test determines whether the memory plane SB is greater than or equal to the SA memory plane and whether a passage B is desired. If the memory planes are not equal, the invention erases a flag ("flag B") to prevent a passage B takes place (processing block 3005), then the processing proceeds to the processing block 3007. If the memory plane SB is equal to the memory plane SA, the flag "make the flag B" is set to indicate that a passage B must be carried out (processing block 3006), after which the treatment

goes to the 3007 processing block.

  In the processing block 3007, a test determines whether the passage flag A is set and the zero branching modeling is to be performed. If the flag indicates that a passage A is to take place and zero branching modeling is to be performed, a "determined / undetermined" flag is initialized in the "not determined" state for each coefficient that has children (block 3008), and the processing proceeds to the processing block 3009. Conversely, if the passing indication flag A or the zero branching indication is not set, the processing goes directly to block 3009. In block 3009, the first coefficient is set to variable C. Once the first coefficient has been assigned variable C, a test determines whether the flag indicating passage B is set (processing block 3019). If the flag flag B "flag B" is set, the invention applies a passage B to the coefficient C (processing block 3010), and the processing proceeds to the processing block 3011. Conversely, if the flag of passage B is not positioned, no passage B is applied

  at C, and the treatment goes directly to the processing block 3011.

  The test then determines whether the passing indication flag A has been set (processing block 3011). If the passage indication flag A has not been set, then a passage A is applied to the coefficient C (processing block 3017). Thereafter, the treatment proceeds to the processing block 3013. If the passage indication flag A is set, the treatment proceeds to the processing block 3013 without making a passage A to the coefficient C. In the processing block 3013, a test determines whether the coefficient C is the last coefficient. If the coefficient C is not the last coefficient, then the processing continues in the processing block 3014, where the following coefficient is assigned the variable C, after which the processing proceeds to the processing block 3019. However, if the coefficient C is the last coefficient, the processing proceeds to processing block 3015, where a test determines whether the passing flag B "flag B" is set. If the passage flag B is set, the memory plane SB is set to be equal to the memory plane SB-1 (processing block 3016), and the processing proceeds to the processing block 3017. If the passage indication flag B is not set, processing proceeds to processing block 3017. In processing block 3017, a test determines whether the passage flag A is set. If set, then the memory array SA is set to be equal to the SA-1 memory array (processing block 3018), and the processing terminates. Similarly, if the flag of

  Pass A is not set, so the processing ends immediately.

  Ramifications of the coefficients In a pyramidal system, the coefficients can be grouped into groups using a branched structure. The root of each branch is a pure low-pass type coefficient. Figure 5 illustrates the branched structure of a single pure low-pass type coefficient of the transformed image. For a two-dimensional signal such as an image, the root of the branch has three "children" and the remaining nodes each have four children. Ramificatio is not hierarchically limited to two-dimensional signals. For example, for a one-dimensional signal, a root has a child, and nodes that are not the root have two children each. The higher dimensions are deduced

  one-dimensional and two-dimensional cases.

  The branched structure also stems from the operation of the filters

  shown in Figures 4A-4C. The operation of the pairs of sub-filters

  sampling makes that the previously described coefficients are connected.

  According to the invention, after the coefficients have been set to the sign / amplitude format, a context model determines the one of the multiple coding methods that must be used to continue coding the coefficients. A frequency-based coding scheme, such as zero-branching coding, efficiently encodes the significance data that is associated with a given subband decomposition for a specified threshold. In addition to the use of symbols indicating the significance or non-significance of a single isolated coefficient in the associated subband decomposition, the items consisting of nonsignificant parents with all non-significant children (those with smaller amplitude or equal to the given threshold) are grouped together and are jointly coded. These ramifications are sometimes called zero ramifications. These non-significant branches are coded using a single specialized symbol, sometimes called a zero branching root. However, if there is a significant descendant, the element of a non-significant coefficient is coded using the symbol for an "isolated zero". Thus, an offshoot is coded using four symbols (significant positive, significant negative, isolated zero and zero branching root) with respect to decisions where the sign of

  coefficient has not yet been coded.

  Frequency-based coding is particularly useful in compression systems because the joint coding of insignificant branches allows for a small number of parent coefficients to predict the non-significance of a large number of downward coefficients. Since the elements of the branching associated with the falling coefficients can be predicted from the root, no additional symbols are needed to encode their nonsense. The non-significance of the whole branch is coded at the expense of a small expense of space. As a result, higher-order memory arrays consist mainly of insignificant coefficients, many of which are neither zero branch roots nor isolated zeros (ie, they are children in branches).

  not significant that it is not necessary to code).

  In U.S. Patent No. 5,321,776, Shapiro describes a frequency-based model called "zerotree", that is, "zero branching". According to the method described in this patent, two lists are used, namely one

  Dominant list and a subordinate list, to record all the coefficients.

  For each level of meaning, two passages are made, a dominant passage and a subordinate passage. In one embodiment, the model based on

  on the frequency according to the invention is the so-called "zero branching" model.

  In another embodiment, a frequency-based model

  similar to the "zero branching" model (as described by Shapiro) is used.

  Instead of using multiple lists, only one list is used, with each item in the list being identified as a member of one of two groups. The separation of the coefficients between a group A and a group B is equivalent to the separation that Shapiro obtains by using respectively a dominant list and a subordinate list. Shapiro's use of multiple lists provides greater flexibility for ordering coefficients in the subordinate list, at the cost of greater software and / or hardware complexity. The present single-list zero branching method uses two passages, a passage A and a passage B, which are respectively equivalent to the dominant passage and the subordinate pass described by Shapiro. We describe below

  the single-list zero-branching model.

  The coding system according to the invention stores in memory a list of the coefficients in the sign / amplitude format. Each item in the list has a single-bit label that indicates whether the item is a member of 'group A' or 'group B'. At the beginning of a processing phase, coefficients that have not yet been shown to be significant are labeled as belonging to group A. The coefficients that had previously been found to be significant relative to earlier, larger thresholds are labeled as belonging to group B. The list contains the coefficients in the order in which they will be processed during the coding. At the beginning of the very first phase, all the coefficients are labeled as members of group A, since no coefficient has yet been established as significant. When coefficients are determined to be significant or insignificant, the tags associated with them change from the initial designation "group A" to the designation "group B". This list will then be refined as thresholds appear.

  progressively finer. Thus, multiple passages in the list take place.

  In one embodiment, the bit events that correspond to the coefficients of group B are arithmetically binary coded according to a zero order Markov context model. Quaternary events corresponding to the coefficients of group A are also coded according to a model

  Markov context of zero order.

  The order of the coefficients in the list according to the invention preserves the

  branched structure so that no child can be modeled before its parent.

  Therefore, an ordering that preserves the branched structure is fixed and is used consistently. In one embodiment, the coefficients are stored in memory in the order starting from the first storage position used. In another embodiment, a list can be used

in sequential chained.

  In one embodiment, the coefficients are encoded in a bit significance scheme or memory array. Since the coefficients are coded from the most significant memory plane to the least significant memory plane, the number of data memory planes must be determined. According to the invention, this operation is carried out by searching for a higher bound to the amplitudes of the values of the coefficients which have been calculated from the data or obtained from the depth of the image and the filter coefficients. For example, if the upper bound is 149, then there is

  8 order of bit meanings or 8 memory planes.

  Figs. 6A and 6A (continued) illustrate an embodiment of the single list zero-branch coding process according to the invention. In one embodiment, the process of Figs. 6A and 6A (continued) can be used in the modeling process of Figs. 27A and 27B. As shown in Figs. 6A and 6A (continued), the process begins by checking whether the group flag associated with the coefficient C is set to "group A" (processing block 3221). If this is not the case, then the process is terminated Conversely, if the group flag associated with coefficient C is set to 'group A', then processing continues in processing block 3222, where a test determines whether the associated 'determined / undetermined' flag the coefficient C is set to "not determined". If the "determined / undetermined" flag of the coefficient is not set to "not determined", the process is terminated. However, if the "determined / undetermined" flag of the coefficient C is set to "not determined", processing continues in the process block 3203, where a test determines whether the

bit SA of coefficient C is 1.

  If the SA bit of the coefficient C is not 1, the processing continues in the processing block 3207. Conversely, if the SA bit of the coefficient C is 1, the processing proceeds to the processing block 3204, where a test determines whether the sign of the coefficient C is positive. If the sign of the coefficient C is not positive; the decision takes the coded form "significant negative" in the context or contexts 'group A' (processing block 3205), and the process proceeds to block lc processing 3229. If the sign of the coefficient C is positive, the decision takes the form coded as 'significant positive' in the "group A" context (processing block 3206), and the process proceeds to the process block 3229. In the process block 3229, the

  group flag associated with C is set to "group B".

  In processing block 3207, a test determines whether the SA bit is zero for all descendants (children) of coefficient C. If the SA bit is not zero, the decision takes the coded form "not significant with significant children" (01) in the "group A" context (processing block 3208), and the process terminates. Conversely, if the SA bit is 0 for all descendants (children) of the coefficient C, the decision is coded as "zero branching root" (00) in the context or contexts "group A" (processing block 3209). After that, the 'determined / undetermined' flag of all the descendants of the coefficient C is set to 'determined' (block of

  3221), and the process ends.

  In another embodiment, the end-of-process test may

  based on whether or not a desired compression ratio has been achieved.

  In one embodiment, the binary events resulting from the B-pass are entropic encoded according to a zero-order Markov source context modal. The 2-bit alphabet (size 4) resulting from the passage A is also coded according to a zero-order Markov source, by a

  Quaternary arithmetic coder (size 4 alphabet).

  FIGS. 6B and 6B (continued) illustrate another embodiment of the single-list zero-branching coding process according to the invention, using a reduced flag memory. In one embodiment, the process of Figs. 6B and 6B (continued) may be used for passage A of the process of Figs. 30A and 30B. As shown in FIGS. 6B and 6B (continued), the process begins by checking whether the result of the logical intersection (function E) of the coefficient C with the mask MA is zero (processing block 3201). If it is not, the process ends. Conversely, if the result of the logical intersection of the coefficient C with the mask MA is zero, the processing continues in the processing block 3202, where a test determines whether the "determined / undetermined" flag relating to the parent of the coefficient C If the parent flag of the coefficient is not set to "not determined", the process is terminated, but if the "determined / undetermined" flag of the parent of the coefficient C is set to 'not determined', the treatment continues in the

  processing block 3202, where a test determines whether the SA bit of the coefficient C is 1.

  If the SA bit of the coefficient C is not 1, the processing continues in the processing block 3207. Conversely, if the SA bit of the coefficient C is 1, the processing proceeds to the processing block 3204, where a test determines whether the sign of the coefficient C is positive. If the sign for coefficient C is not positive, the decision is coded as "significant negative" in one or more "group A" contexts (processing block 3205), and the process ends. coefficient C is positive, the decision is coded as 'positive significant' in one or more 'group A' contexts (processing block 3206), and the process ends. In one embodiment, a quaternary coder is used and the quaternary decisions are coded in a single context. In another embodiment, a binary encoder and three contexts are used (the three contexts are the first bit of the decision, the second bit when the first bit

  is 0, and the second bit when the first bit is 1).

  In processing block 3207, a test determines whether the SA bit is 0 for all descendants (children) of the C coefficient. If the SA bit is not 0, the decision is coded as "not significant with significant children" ", 'insulated zero' (01) in one or more 'group A' contexts (processing block 3208), and the process terminates. Conversely, if the SA bit is 0 for all descendants (children) of the coefficient C the decision is encoded as the 'zero branching root' (00) in one or more 'group A' contexts (processing block 3209). the "determined / not determined" flag of the coefficient C is set to "determined" (processing block 3210).

  "determined / not determined" of all the descendants of the coefficient, who have

  same descendants, are positioned on "determined" (block of

  3211), and the process ends.

  Decoding operations According to the invention, the decoding is done in synchronism with the coding. Fig. 6C illustrates an embodiment of the passing process A relating to a zero branch horizon horizon decoding process, and may be used in conjunction with the process of Figs. 27A and 27B. As shown in FIG. 6C, the process begins by checking whether the group flag of the coefficient C is set to "group A" (processing block 3521). If it is not, then the process ends. However, if so, the process proceeds to process block 3528, where a test determines whether the "determined / undetermined" flag of coefficient C is set to "not determined". If it is not, the process ends. If so, then the process goes to processing block 3502, where ternary decisions are decoded in one or more group A contexts. Then, a test determines whether the decision is "significant positive" (processing block 3503). If the decision is "significant positive", the sign of the coefficient C is set positive (processing block 3505), the amplitude of the coefficient is set to 2SA (processing block 3507), the group flag of the coefficient C is

  set to "group B" (processing block 3541), and the process ends.

  If the decision is not "significant positive" (processing block 3503),

  a test determines whether the decision is "significant negative" (processing block 3504).

  If the decision is not "significant negative, the process goes to processing block 3509, where a test determines whether the decision is" branching root

  If the decision is not "zero branching root", the process ends.

  If the decision is "zero branching root", the "decimated / determined no" flag of all the descendants of coefficient C is set to "no

  determined "(processing block 3531), and the process ends.

  However, if the test of the 3504 processing block determines that the decision is "significant negative", then the sign of the coefficient C is set negative (processing block 3506), the amplitude of the coefficient C is set to 2SA (block of 3507, the group flag of the coefficient C is set to

  "group B" (processing block 3541), and the process ends.

  Fig. 6D illustrates another embodiment of the pass process A serving a zio branch horizon decoding process, which uses reduced flag memory, and may be employed in the process described in Figs. 30A and 30B. As shown in FIG. 6D, the process begins by checking whether the result of the logical intersection (function Et) of the coefficient C with the mask MA is zero (processing block 3501). If it is not, then the process ends. However, if the result of the logical intersecin of the coefficient C with the mask MA is zero, the processing proceeds to the processing block 3508, where an experiment determines whether the "determinate / undetermined" flag of the parent C is "not determined" . If it is not, the process ends. If so, then the process continues in the processing block 3502, where the ternary decision is decoded in one or more group A contexts. Next, a test determines whether the decision is "significant podative" (processing block 3503) If the decision is "significant positive", the sign of the coefficient is set positive (processing block 3505), the amplitude of the coefficient is fixed at 2SA

  (processing block 3507), and the process ends.

  If the decision is not "significant positive", a test determines whether it is "significant negative" (processing block 3504). If the decision is not "significant negative", the process goes to processing block 3509, where a test determines whether the decision is "zero branching root." If the decision is not "zero branching root," the If the decision is "zero branch root", the "determined / not determined" flag of coefficient C is set to "determined" (processing block 3510), the "determined / not determined" flags of all descendants of the coefficient C which themselves have descendants are positioned on "indeterminate" (processing block 3511), and the

process ends.

  However, if the test of the processing block 3504 determines that the decision is "significant negative, then the sign of the coefficient C is set negative (processing block 3506), the amplitude of the coefficient C is set to 2SA (block of

  3507) and the process ends.

  There are alternatives to Shapiro's choice to use quaternary decisions to describe ramifications. Larger alphabets can be used to further characterize the characteristics of an entire branch when coding the branching root. In one embodiment, the following set of non-significant 6: nonsignificant decisions with nonsignificant children (non-significant branching root) with at least one significant significant positive child, of which all children are non-negative significant positive, having at least one negative significant negative child, all of whose children are non-positive

  At significant negative, having at least one positive child.

  In this embodiment, sign information in addition to the non-sign

  meaning is predicted for an entire ramification. In other embodiments, branches having other sign constraints or amplitude constraints can be predicted. Other predictors could be especially used to represent texture or to represent multiresolution characteristics. With larger alphabets one can use

  higher order Markov contexts (as described below).

  Implant modeling based jointly on space and frequency

with list for several Dassages.

  According to the invention, the frequency implantation coding, like the currently described horizon type model, encodes the ternary events corresponding to the coefficients of the group A. In the type coding of the horizon type, all the initializations preceding the coding operations are identical to those of the frequency-based system. In one embodiment, a binary entropy coding is performed in connection with three contexts, namely "amplitude

  Group A "," Group A Sign "and" Group B ".

  Fig. 7A is a flowchart of an embodiment of the passage A for a single list horizon type coding process according to

  the invention. This process can be used in the process of Figures 27A and 27B.

  As shown in FIG. 7A, the process of the passage A begins by checking whether the group flag associated with the coefficient C is positioned on

  "group A" (treatment block 3111). If it is not, the process ends.

  If the group flag of coefficient C is set to "group A", the process proceeds to process block 3102, where a determined test is performed if bit SA of coefficient C is 1. If bit SA of coefficient C is not 1, the decision is coded as "not significant" (0) in a "group A" context (processing block 3103), and the process is terminated. If the SA bit of the coefficient C is 1, then the processing proceeds to the processing block 3104, where a test determines whether the sign of the coefficient C is positive. If the sign of the coefficient C is positive, the decision is coded as "significant positive" (10) in one or more group A contexts (processing block 3106), and the process proceeds to the processing block 3117. Conversely if the sign of the coefficient C is not positive, the decision is coded as "significant negative" (11) in one or more "group A" contexts (processing block 31105), and the process proceeds to the block 3117 In the 3117 processing block, the group flag of the

  coefficient C is set to 'group B'.

  Fig. 7B is a flow chart of another embodiment of passage A for a single-list horizon type coding process using reduced flag memory. This process can be used in the process of Figures 30A and 30B. As shown in FIG. 7B, the process of the passage A starts by checking whether the result of the logical intersection (AND function) of the coefficient C with the mask MA is zero (processing block 31101). If it is not, then the process ends. If the result of the logical intersection of the coefficient C with the mask MA is zero, the processing proceeds to the block of

  31102, where a test determines whether the SA bit of the coefficient C is 1. If the.

  bit SA of the coefficient C is not 1, the decision is encoded as 'insignificant' (0) in a context of 'group A' (processing block 3103), and the process ends. If the SA goal of the coefficient C is 1, then the processing continues in the processing block 3104, where a test determines whether the sign of the coefficient C is positive. If the sign of the coefficient C is positive, the decision is coded as "significant positive" (10) in one or more "group A" contexts (processing block 3106) and the process terminates. Conversely, if the sign of coefficient C is not positive, the decision is coded as "significant negative" (11) in one or more context (s) of "group A" (block of

  3105), and the process ends.

  Decoding Operations Fig. 7C illustrates an embodiment of the A passage process associated with a single list horizon type decoding process according to the invention, and may be employed in the process of Figs.

27B.

  As shown in Fig. 7C, the process begins by checking whether the group flag of coefficient C is set to 'group A' (processing block 3411). If it is not, then the process ends. However, if the group flag of coefficient C is set to 'group A', processing continues in processing block 3402, where the ternary decision is decoded in

one or more "group A" contexts.

  Then, a test determines whether the decision is 'significant positive' (treatment block3403) If the decision is 'significant positive', the sign of coefficient C is set positive (processing block 3405), the magnitude of the coefficient is set to 2SA (processing block 3407), the group flag of coefficient C is set to 'group B' (processing block 3418), and the process is terminated If the decision is not "significant positive, a test determines it is significant negative (processing block 3404). If the decision is not 'significant negative', the process ends. However, if the decision is "significant negative", then the sign of coefficient C is set negative (processing block 3406), amplitude C is set to 2SA (processing block 3407), the group flag of coefficient C is

  set to "group B" (processing block 3418), and the process ends.

  Fig. 7D illustrates another embodiment of the pass A process associated with a single-list horizon type decoding process using reduced flag memory, and may be employed in the process of Figs. 30A and 30B. As shown in FIG. 7D, the process begins by checking whether the result of the logical intersection (function El) of the coefficient C with the mask MA is zero (processing block 3401). If it is not, then the process ends. However, if the result of the logical intersection of the coefficient C with the mask MA is zero, the processing continues in the processing block 3402, where the ternary decision is decoded in one or more contexts of

"group A".

  Then, a test determines whether the decision is "significant positive" (processing block 3403) If the decision is "significant positive", the sign of coefficient C is set positive (processing block 3405), the magnitude of the coefficient

  is set to 2SA (processing block 3407), and the process ends.

  If the decision is not "significant positive", a test determines whether it is "significant negative" (processing block 3404). If the decision is not "significant negative", the process ends. However, if the decision is "significant negative", then the sign of coefficient C is set negative (processing block 3406), amplitude C is set to 2SA (processing block 3407) and the

process ends.

  Passage B associated with both the zero branch and the horizon type In one embodiment, the pass B process is the same for the zero branch and the horizon type, according to the invention. Embodiments of the passage B algorithm associated with the coding process and the decoding process are shown in FIGS. 8A and 8B, respectively, and

9Aet9B.

  Fig. 8A illustrates an embodiment of the pass B process which is used partially for the single-list horizon and zero-branch coding process, and may be employed in the process of Figs. 27A and 27B. As shown in FIG. 8A, the process initially checks whether the group flag of the coefficient C is set to "group B"

  (treatment block 3111). If this is not the case, then the first one ends.

  Conversely, if the group flag is thus set, the processing continues in block 3202, where a test determines whether bit SB of coefficient C is 1. If the bit of SB of coefficient C is not 1, then the The decision is coded as "0" in one or more "group B" contexts (processing block 3333), and the process is terminated. If the bit SB of the coefficient C is 1, then the decision is coded as "1" in one or more contexts of "group B" (processing block 3404), and the

process ends.

  FIG. 8B illustrates another embodiment of the pass B process, which is partially used for the single-list horizon and zero-branching coding process and which uses reduced flag memory, which process can be employed in the process of Figs. 30A and B. As shown in Fig. 8B, the process initially checks whether the result of the logical intersection (AND function) of the coefficient C with the mask MB

  is non-zero (processing block 3301). If it is not, the process ends.

  Conversely, if the result of the logical intersection of the coefficient C with the mask MB is non-zero, the process proceeds to the process block 3302, where a test determines whether the bit SB of the coefficient C is 1. If the bit SB of the coefficient C is not 1, so the decision is coded as "0" in one or more "group B" contexts (processing block 3303), and the process ends. If the SB bit of the coefficient C is 1, then the decision is coded as "1" in one or more

  "Group B" contexts (Processing Block 3304), and the process ends.

  Fig. 9A illustrates an embodiment of the decoding associated with passage B according to the invention, and may be employed in the process of Figs. 27A and 27B. As shown in Fig. 9A, a test initially determines whether the group flag of coefficient C is set to "group B"

  (Treatment block 3611). If it is not, then the process ends.

  However, if the group flag of the coefficient C is set to 'group B', then the decisions are decoded in one or more 'group B' contexts (processing block 3602), a test then decides whether the decision is "1 "(processing block 3603) If the decision is not" 1 ", the process is terminated If the decision is" 1 ", the bit SB of the coefficient C is set (processing block 3604) and the

process ends.

  FIG. 9B illustrates another embodiment of the decoding associated with the passage B according to the invention, which uses a reduced flag memory, which embodiment can be used in the process of FIGS. 30A and B. As shown in FIG. 9B , a test initially determines whether the results of the logical intersection (function El) of the coefficient C with the mask MB is non-zero (processing block 3601). If the result of the intersection

  logic of the coefficient C with mask MB is zero, so the process ends.

  However, if the result of the logical intersection of the coefficient C with the mask MB is non-zero, then the decisions are decoded in one or more contexts of "group B" (processing block 3602). A trial then decides whether the decision is "1" (processing block 3603). If the decision is not "1", the process ends. If the decision is "1", the bit SB of the coefficient C is set (block of

  3604 processing) and the process ends.

  By using the combination of the zero-branched order coding and the horizon type command coding, the invention realizes a coding according to the degree of significance of the bits for the coefficients produced by the reversible elementary waves. It should be noted that the joint use of group A and group B, as well as ternary events and binary events corresponding respectively to passages "A" and "B", is especially important in view of the fact that a switch is established when we go from using the zero branching order to the horizon type order at the end of any A pass. This compensates for the inefficiency of prediction that accompanies the zero branching order for lower order. Thus, according to the invention, the system starts by coding the data of the higher order bits according to the zero branching, and then after a certain number of passages in the lists, that is to say after a certain number memory planes have been coded, the encoder according to the invention switches so as to encode the rest of the data using a coding of the horizon type. The number of passes can be selected statistically or can be adaptively selected by monitoring the performance of the coding block in the order of

zero branching.

  Other context models In one embodiment, five compartments of binary contexts are used. This is little compared to other systems, for example the JBIG which uses a little more than 1024 contexts. Compression can be improved by using more context compartments. Decisions can be conditioned by a spatial position, level, or bit position. Decisions can also be conditioned by previously decoded data that is close to current data with respect to spatial position, level, or bit position. In general, the previously described zero order Markov contexts can be replaced by

  higher order Markov contexts.

  Some examples are given below. The most significant (and therefore most easily predicted) bit of each mantissa (group B data in some embodiments) could use a different context than the other bits. The significant or insignificant decision could be conditioned by a similar decision taken for previously spatially close coefficients of the same level of transformation. Similarly, the sign bits of the significant coefficients could be conditioned by the sign of previously spatially close coefficients having the same level or by the

sign of the coefficient of the parent.

  The enhancements due to the context model can be especially important when it comes to compressing images having spatial structure or multiresolution type. Gray scale images belonging to line drawings or text are an example of images having both types of structures. Improvements are also important when compressing files that, in principle, need to be

  compressed and decompressed with a specified peak error.

  Other Embodiments of the Invention The invention can be implemented in the form of hardware equipment, in software form or in both forms at the same time. A hardware implementation of the invention requires the realization of the elementary wave filters, a management of the data flow with respect to the memory to provide the data intended for the filters, a context model for controlling the coding by implantation according to the invention, a management of the circulation of the data relative to the memory making it possible to supply the data intended for the context model, and an entropy coder

binary.

  Elementary Wave Filters An embodiment of the direct elementary wave filter according to the invention is shown in FIG. 10. The elementary wave filter shown in FIG. 10 processes four input pixels of the 16 bit complementation type, represented by X (2) -X (5). As can be seen in FIG. 10, the two-tap low-pass filter "1" uses a 16-bit adder 1001. The output signals are respectively called S and D. The output signal of the adder (S) is truncated to 16 bits using a block 1003 shifted by 1. Block 1003 of the shift of 1 performs a division function by 2 by shifting one bit towards the

  right its 17-bit input signal.

  The high-pass filter "-1 -1 8 -8 1 1" at six intermediate taps requires the calculation of -SO + 4D1 + S2. The function S2-So is calculated using the 16-bit subtractor 1005 which receives the output signal from the shift block 1003 of 1 and Y0 (0). The term 4D1 is calculated using the subtracter 1002 and an offset block 1004 of 2. The output signal produced by the 16-bit subtractor 1002 is shifted two positions to the left, which has the effect of multiply by four its output signal. The addition of the output signal 4D1 from the shift block 1004 of 2 to the output signal of the subtractor 1005 is performed by a 20-bit adder 1006. The output signal of the final adder is truncated to 18 bits at the using a shift block 1007 of 2. The shift block 1007 of 2 performs a division function by four by shifting two bits

  to the right its 20-bit input signal.

  Thus, the total computing equipment required (not counting the registers used to store temporary results) is: - a 16-bit adder, - two 16-bit subtractors,

a 19-bit adder.

  It is noted that the offset is made using the wiring, so that no circuit

logic is necessary.

  In other embodiments, for input signals of size N, an N-bit adder, two N-bit subtractors, and one N-bit adder can be used.

adder at (N + 3) bits.

  Because of the extremely low material cost of these adders and

  subtractors, one can use, if desired, a filter assembly in parallel.

  Note that, instead of subtracting X (3) and X (2), we can calculate X (4) X (5) and put the result in reserve until we need it later in form X (2) -X (3) for the next offset or the next filter application. The direct filter (like the reverse filter described later) can be pipelined to provide superior performance. The inverse elementary wave filter is shown in FIG. 11. The input signals Y0 (0) and Y0 (2) are subtracted by a subtractor 1101. The result of the subtraction is shifted two bits to the right by a block This has the effect of dividing by four the output signal of the subtracter. A subtraction is performed between the output signal of the shift block 1104 of 2 and the input signal Y1 (0). The input signal Y0 (1) is shifted one bit to the left by the shift block 1103 of 1, which multiplies the input signal by two. After Y0 (1) has been shifted by 1 (i.e., multiplied by 2), the least significant bit (LSB) of the shifted value is the least significant bit taken from the output signal of the subtractor 1104 and combined with the 16-bit output signal from the offset block 1103 of 1 to form the input signal for the adder 1105 and the subtractor 1106. The other input signal of the adder 1105 and of the subtractor 1106 is constituted by the output signal of the subtractor 1104. The output signals of the adder 1105 and the

  subtractor 1106 can then be clipped.

  You can choose two clipping operations. In both cases, the 20-bit value is shifted by 1 (divided by two) to give a value of 19 bits. For a system that performs only lossless compression, the least significant 16 bits can be output (the remaining three bits can be ignored). In a lossy system (or a lossy / lossless system), the 19-bit value is set to zero if it is negative or is set to 216-1 if it is greater than 216-1; if not,

  the 16 least significant bits are output.

  For input signals of size N bits, it is possible to use an N-bit subtractor, a (N + 2) -bit subtractor, an (N + 3) -bit adder and

  a (N + 3) bit subtractor, and the clipping unit outputs N bits.

  Mode of use of the memory With regard to the memory management and the data flow applicable to the elementary wave filters according to the invention, in the case of images such that a complete image can be placed in memory, the management of memory and data flow is not difficult. Even for medical images representing 1024 x 1024 times 16 bits (2 megabytes), it is reasonable for many applications to request a full image buffer. For larger images (eg 4-color 400 dpi images of A4 size, about 50 megabytes in size), it is desirable to perform the elementary wave transformation using

  a line buffer memory representing a limited amount.

  Note that, according to the invention, it is not necessary to have a complete image buffer to implement a single-pass system. As a result, the required memory can be reduced by a factor of approximately 100 (compared with the use of a full image buffer for large

  images). The one-pass system according to the invention will be described below.

  The data stored in the filter memory consists of a series of coefficients that must be subjected to implementation encoding and binary entropy coding. Implant coding uses a context model to coordinate the use of frequency-based or horizon-type coding and to provide data in the desired order. The context model works in conjunction with a memory management scheme. For systems with a full image buffer, it is not difficult to provide data in the correct order. For systems without a full image buffer, the transformation data management scheme of the single pass embodiment of the invention (described hereinafter) provides coefficients to the context model so that the context model only needs to buffer the coefficients for a single branch. A single-pass frequency-based context model and a context-based contextual model based on space and frequency of the single-pass type

  work on only one branch at a time.

  The result of the implantation operation according to the invention is to produce bitstreams from the frequency-based modeling mechanism according to the invention and the space-based and frequency-dependent modeling mechanism according to the invention. 'invention. These bitstreams are then coded to

  using a binary entropic coder.

* For a system with a full frame buffer, use any binary entropic encoder (or other appropriate encoder). For systems without a complete image buffer, several independent encoders must be used, or the encoder must be able to simulate several independent encoders. In addition, it is necessary to manage the memory or the channel to keep track of the output signals of the independent encoders. One advantage of the invention is that the data to be managed are classified according to a certain order of priority (so-called "implanted"). If there is not enough space or bandwidth, during compression or transmission, less important data can be discarded by allowing reasonable loss compression. A single-pass system according to the invention The invention proposes a single pass transformation which allows

  to completely process the input data of the system upon receipt.

  In such a system, data processing does not depend on the following data. The memory required to compress an image is independent of the length of the image. By removing the dependency, the invention provides a system that can deliver compressed data before all data has been

processed.

  A. Data Management for a Single-pass Transformation Figure 12 shows a portion of an image that is being compressed in a certain dithering order by the tape method using the teachings of the invention. We consider the case of a decomposition

  four levels. Each branch has 24 x 24 = 16 x 16 = 256 coefficients.

  However, since the high-pass filter of the elementary wave transformation according to the invention is overlapping, each branching depends on more than 256 input pixels. The L-shaped low pass filter '' 1 1 '' does not cause any overlap, the entire overlap from the high pass filter '-1 -1 8 -8 1 1' at six intermediate taps, The most important overlap occurs for the cascade of three low pass filter applications followed by a high pass filter (LLIH) application. Three low pass filter (LLL) applications require support of 23 = 8 input pixels. Supporting regions with a size of 8x8 pixels are shown in Figure 12. When including the high-pass filter in the cascade, the support regions are (6 x 23) x (6 x 23) = 48 x 48 pixels. A support region of 48 x 48 pixels, consisting of thirty-six 8x8 blocks is shown in Figure 12. It is assumed that the coefficients of the 48 x 48 pixel support region shown in Figure 12 are being treaties. The lightly shaded portion of the support region indicates pixels that have already been used in previous support regions. The slightly shaded portion that is outside the support region indicates pixels that have already been used in previous support regions and are needed in future support regions. The 16 x 16 pixel black region is the portion of the support region that contains pixels that have not been previously used. Similarly, the shaded 16x16 pixel region contains pixels that have not been previously used but will be used in the next 48 x 48 pixel support region. A three-level 16 x 16 transformation is computed, the previous results of eight other 16 x 16 three-level transformations are sought in a buffer, and the fourth level of the transformation is applied to the nine 16 x 16 three-level transformations. The buffering capability required to accomplish this operation is sufficient to store the three-level transform coefficients for (2 x '+32) x 16-pixel image width, plus a 16-line buffer (one band)

pixels.

  Fig. 13 is a block diagram showing an embodiment of the single-pass elementary wave filter unit, which comprises a filter control unit 1301, a memory 1302 and a filter 1303. The filter 1303 is constituted by the filter described in connection with Figure 10. The memory 1302 relates to the memory described above in connection with Figure 12 and stores pixels or coefficients. The filter control unit 1301 determines the flow of data between the memory 1302 and the filter 1303. The operation of the 1301 unit will be explained below.

filter control.

  FIG. 14 represents another unit of elementary wave filtering. For fast operation, several filters can be used. In one embodiment, since the filter 1303 requires four or five inputs (eg inverse filter, direct filter) and produces two

  output signals, the necessary memory bandwidth may be important.

  The memory may have multiple pixels or coefficients per location, multiple memory blocks, and / or multiple accesses. A memory interface unit 1401 reduces the necessary memory bandwidth by providing small buffers for local data used during processing. The memory interface unit 1401 also provides multiplexing and demultiplexing

  between the input / output (I / O) of the memory 1302 and the input / output of the filter 1303.

  In addition to the memory bandwidth required for filtering, additional bandwidth may be required for the application of the pixels to the input of the memory 1302 and the delivery of the coefficients to the context moduIC. If pixels are inputted following a dithering order, a

  Additional memory may be needed for the tape buffer.

  If a memory stores multiple elements (pixels or coefficients) in each location, instead of horizontally or vertically storing adjacent elements in a row or column, this may reduce the amount of memory access and buffering capacity required by making the elements contained in an N x N block, where Nest a power of 2, share the same location. This gives equal convenience to the vertical and

horizontal.

  Several memory blocks can also be implemented so that horizontal and vertical access can both benefit from the multiple blocks, as shown in FIG. 15. In the case of two memory blocks, one can block selection bit for selecting one or the other of the memory blocks may be formed, in one embodiment, by means of a logical addition (exclusive OR) of the least significant bits of the horizontal coordinates and vertical. In the case of four blocks of memory, the two block selection bits can be formed by addition (modulo 4 using a 2-bit adder) two least significant bits of the co-ordinates

horizontal and vertical.

  Figure 16 illustrates the single-pass filtering operation for implementing a two-level decomposition using the

  filter control 1301 (Figure 13). It is noted that, as part of the description,

  we will first present the description of a decomposition at two levels in vuc

  to illustrate the general technique of the invention. In other embodiments, three-level, four-level or more decompositions are used. A two-level decomposition has 16 coefficients per branch and requires a calculation working with 16 input pixels that have not been used previously. The filtering relating to a coefficient branch takes place in 16 units of time or less so as to match the input and output rates. In this example, two filters operating parallel are used to achieve the desired performance of two filtering operations per unit of time. For each spatial location, where the front side of a filter is applied, Figure 16 shows a number that indicates the time at which each

  filtering operation was performed.

  Since the order of the filtering operations is determined by the front side of the filter, the filtering does not produce all the coefficients of a certain branch before producing some of the coefficients of the next branch. The filtering of the children of the branching takes place before the filtering of the parents, and the low-pass filtering is carried out before the corresponding high-pass filtering. Filtering acts on the "group A" of coefficients which has the same number of coefficients of a type as a branch.

  The level 1 e horizontal filtering is executed during the time period from time 0 to time 7, and the results are stored in a temporary buffer. (Each spatial location gives two coefficients.) During the time period from time 2 to time 9, vertical filtering is performed (through the second filter) on data contained in the buffer and data from the previous horizontal filtering from of memory (twice per space location). Vertical filtering can begin as soon as the second horizontal filtering operation is complete. The coefficients HH, HL and LH are ready to be delivered to the context model (at the appropriate time). The LL coefficients are

used in the next level.

  With only two filters, level 0 horizontal filtering can not begin before time 8 o Level 1 horizontal filtering is complete, thus making a filter available. Level 0 horizontal filtering can not be completed before the cycle time after level 0 vertical filtering has completed, providing all necessary data. Then, during the lapse of

  time of the times 11 and 12, the level 1 vertical filtering can take place.

  Table 1 below summarizes the operation of each filter during each unit of time. The elements of the table are presented in the following format: level number, horizontal or vertical ("L" or "V") and spatial location of the previous side. Items subjected to vertical filtering operations are identified as low-pass or high-pass filtered using the "L" or "H" index. It is noted that it is not necessary to assign a certain filter to the execution of the horizontal filtering and the other to the execution of the vertical filtering, since

the two filters including identical.

TABI.FAU 1

  Time _ Filter 1 | Filter 2 O 1H (0,0) (free)

1H (0.1)

2 1H (2.0) 1VL (O, O)

3 1H (2.1) 1VH (O, O)

4H (0.2) 1VL (0.2)

1H (0.3) 1VH (2.0)

6H (2.2) 1VL (0.2)

7H (2,3) 1H (0.2)

8 OH (0.0) 1VL (2.2)

  9 (i) OH (2,2) OH (O, 1) (free) OVL (O, O)

12 OVH (O, O)

  I 13 (Free) 14 L (free) While level 1 horizontal filtering may start with the next group of input pixels at time 11, this will cause the filter to operate at a speed exceeding the input and output rates. exit. Instead, according to the invention, the filters remain free and the next groupc processing begins CC at time 16. The free filter cycles can be used for memory transfers. Instead of appearing at the end of filtering for each groupc, cycles

  free could be split between filter cycles if this were desirable.

  In connection with the explanations for the level 2 case, Table 3 presents the three-level case. Concatenations of two or four units of time were used to transfer the information on a page, from

  to make reading easier.

TABLEAUI2

  Time fi lter 1 fi lter 2 S 0-3 2H (0,0), 2H (0,1), 2H (2,0) 2H (2,1) (idle), (idle) 2VL (0,0) , 2VH (O, 0)

  4-7 2H (4.0), 2H (4.1), 2H (6.0) 2H (6.1) 2VL (2.0), 2H (2.0), 2VL (4.0), 2VH (4.0)

  8-11 2H (0.2), 2H (0.3), 2H (2.2) 2H (2,3) 2VL (6.0), 2H (6.0), 2V1 (0.2), 2VH (O 2)

  12-15 2H (4.2), 2H (4.3), 2H (6.2) 2H (6.3) 2VL (2.2), 2H (2.21, 2V1, (4.2), 2HH ( 4,2)

  16-19 2H (0.4), 2H (0.5), 2H (2.4) 2H (2.5) 2VL (6.2), 2H (6), 2VL (0.4), 2HV (O, 4)

  2-20-23 2H (4.4), 2H (4.5), 2H (6.4) 2H (6.5) 2VL (2.4), 2H (2.4), 2VL (4.4) , 2VH (4,4)

I

  24-27 2H (0.6), 2H (0.7), 2H (2.6) 2H (2.7) 2VL (6.4), 2H (6.4), 2VL (0.6), 2VH (0.6)

  28-31 2H (4.6), 2H (4.7), 2H (6.6) 2H (6.7) 2VL (2.6), 2H (2.6), 2VL (4.6), 2VH (4.6)

  32-35 1H (0.0), 1H (0.1), 1H (2.0) 1H (21.1) 2VL (6.6), 2H (6.6), 1VL (0.0), IVH (O, 0)

  36-39 1H (OO, 2), 1H (0.3), 1H (2.2) 1H (2,3) 1VL (2,0), 1H (2, O), VI (0, 2) , 1V! (0,2)

  -43 OH (0.0, (free OH (0.1), (free) 1 VL (2.2), 1 VH (2 ''), (idle), OVL (O, O), 44-47 2VH ( O, O), (free), (free), free) 48-51 52-55 (free) (free) 56-59 -63 Table 3 illustrates the four-level case Since there are now 256 units of time per group of coefficients, it has not been shown, for simplicity,

  than the level and meaning of filtering.

TABLE 3

  Time Filter 1 Filter 2 0-1 Level 3 Horizontal (Free) 2-127 Level 3 Horizontal Level 3 Vertical 128-129 Level 2 Horizontal Level 3 Vertical Level -159 Level 2 Horizontal Level 2 Vertical -161 Horizontal Level 1 Vertical Level 2 162-167 Level 1 Horizontal Level 1 Vertical 168 Level 0 Horizontal Level 1 Vertical 169 (Free) Level 1 Vertical Level 0 (Free) Horizontal 171 (Free) Level O Vertical 172 (free) Vertical level 0 173-255 (free) (free) The output signal of the filtering and storage subsystem according to the invention is constituted by a series of coefficients which undergo a coding

  by implanting the degree of significance of the bits, according to the invention.

  B. The context model for the single-pass system In one embodiment of the invention, namely the context model implanted with respect to the bit significance level for the single-pass system, each branch is processed in four parts. The root of the branching, ie the highest LL coefficient, is encoded by a

  one-pass horizon ordering coding. The three sub-

  branches from each of the three children of the root, namely the highest-level coefficients HH, HIL, and LH, are processed using a single-pass space and frequency-based single-pass frequency-based modeling. The soint coefficients are coded so that coded data can be delivered before the bit pitch pattern contextual model has acted on all the data. Branching of One-pass Meanings The zero-branch context model can not be used in the single-pass system. Zero branching requires a list (or many) that contains all the coefficients, and zero branching performs several passes in the list (s). Another frequency-based model, the one-pass branching model, requires no list containing all the coefficients. Another difference between the branching of one-pass meanings and the zero branching is that the meaning branching treats all children before treating their parents during production.

  decisions, unlike the zero branching that first deals with parents.

  The context model according to the invention is presented in the form of a block diagram in FIG. 17. The context model 1700 contains two processing units, the sign / amplitude formatting unit 109 (FIG. and the signal processing unit 1702. The context model 1700 also uses two memories (as well as a memory control logic circuit), an amplitude memory 1701 and a branch memory 1703. Each of these two units memory can be implemented using multiple storage areas to allow alternate use during high-speed operation (i.e., while data is being

  written in one memory, the other is being read, or emptied).

  The amplitude memory 1701 reorders the coefficients contained in the branch according to a meaning-based order, such as an amplitude-based order. This is achieved by maintaining a queue for each possible amplitude. The signal processing unit 1702 receives functionally ordered (eg, amplitude) ordered coefficients and outputs decisions to an encoder which manipulates the A-passage algorithm. The branch memory 1703 is coupled to the meaning processing unit 1702 and eliminates the zero branching as a result of a party

  entirely made up of zeros.

  The following discussion assumes that the coefficients are at 18 bits and

  that the input data has been decomposed at four levels.

  An embodiment of the sign / amplitude unit 109 is shown in Fig. 18 and sets the input coefficients to sign / amplitude. The sign / amplitude unit 109 is coupled to receive the 18 bits of the coefficients and comprises an inverter 1801, a multiplexer (MUX) 1802, a priority encoder 1803 and a counter 1804. The sign / amplitude unit 109 delivers a indication of significance (for example a value with S bits), the mantissa of the center coefficient (for example 17 bits), the sign of the input coefficient (1 bit) and an index coming from the

counter 1804 (for example 7 bits).

  The multiplexer 1802 is coupled to receive 17 bits of the coefficient as applied directly to the sign / amplitude unit 109 and an inverted version of the 17 bits from a complementation device to 2, designated 1801. As a function of the sign bit (bit 17 of the coefficient) received on the selection input of the multiplexer 1802, that of the two input signals which is

  positive is issued under the mantissa.

  The sign / amplitude unit 109 uses the priority encoder 1803 to determine the first significant bit of each coefficient. Depending on the first significant bit of each coefficient, a significance level can be associated with the coefficient. The counter 1804 is used to associate an index with the current element of the branching. For a four-level decomposition, the index varies from 0 to

  84 (since 1 + 4 + 16 + 64 = 85 is the number of elements of a subset

  branching out). The coefficients applied to the input are in the order of the branch, which order is assumed to be the following, the parents first, the children last, according to this example. The coefficients come from different levels of decomposition, as shown in Table 4, for

the coefficients placed in order.

TABLE 4

Niveaul Index of coefficients

0 0

"

1, 1.22, 43, 64

  2 2, 7, 12, 17, 23, 28, 33, 38, 44, 49, 54, 59, 65, 70, 75, 80

  3 3 ... 6, 8 ... 11, 13 ... 16, 18 ... 21, 24 ... 27, 29 ... 32, 34 ... 37, 39.

  42, .. DTD: 45 ... 48, 50 ... 53, 55 ... 58, 60 ... 63, 66 ... 69, 71 ... 74, 76 ... 79, 81. ..84

  Fig. 19 is an embodiment of the amplitude memory 1701, in the form of a block diagram. A counter and a memory are associated with each possible level of significance (except that nothing is needed for zero coefficients, which need not be coded). For example, the counter 1916 and the memory 1936 are associated with the level of significance 17. In one embodiment, there are sixteen levels of

  meaning. There are therefore seventeen counters and seventeen associated memories.

  In one embodiment, each memory must have 85 locations, for each possible sub-branching coefficient (since each subbranch contains 85 coefficients), but the memory size could be rounded to a power of 2, by Example 128, for convenience. Each element contained in the memory may have a sign bit, a 7-bit index and N amplitude bits, where N is the level of significance. If one wishes to use a memory of fixed width, one can combine the elements relating to the levels of signification 16 and 0, 15 and 1,

  etc., so that each word includes two elements totaling 32bits.

  Of course, for an odd number of levels of meaning, a word must

  contain only one element, which is level 7 in this example.

  The values associated with the sign, index, and mantissa that are received from the sign / amplitude unit 109 are written to the appropriate memory at the address provided by the counter associated with the memory. The associated counter is then incremented so that the next coefficient having this level

  meaning can be stored in the following location.

  The reading is carried out in each of the memories 1920 to 1926 in descending order of the degrees of significance. The output signal relative to each coefficient includes its mantissa, its sign and its index. If the counter relating to the highest level of significance (for example level 16) is non-zero, it is decremented and the reading of the memory takes place at this address. This is repeated until the counter value reaches zero. Then we consider the next level of meaning (eg level 15). Each level of significance is considered in turn, until all counters have been decremented to zero and all memories have been dumped. In a real-time system, it may be desirable to use two blocks of counters and memories, so that a block can be used to

  the entrance while the other is used for the exit.

  The counters address the memory associated with them in order to implement a LIFO procedure (which means "last in, first out") .The LIFO procedure corresponds to the correct order in case -Ramifications are in order placing the parents first.On another possibility, if the subradifications are in the order where the children are first, we can change the operation of the counters by setting

  a FIFO procedure ("first in, first out").

  Fig. 20 is a block diagram showing an embodiment of the meaning processing unit 1702. As can be seen in Fig. 20, an index counter 2001 is used to switch from one coefficient to another in a sub-ramification, children being first. In a mode of

  realization, the index counter 2001 is initialized to 84 and counts down to zero.

  The counter of significance 2004 begins at the level of maximum significance (for example 16 in the example considered) and counts each time the index counter 84 completes a cycle (that is to say, amounts to 84). so that the 2004 significance counter keeps track of the memory map. The level of a particular index is determined by a logic circuit (setting the index to

  2003) performing the function presented in Table 4 above.

  An amplitude memory unit 1701 supplies the index, amplitude and sign of the next coefficient in the memory validated by the output signal of the counter of significance 2004. If the index provided by the memory is the same as the index issued by the index counter 2001, the logic equivalence circuit 2002 assigns the non-zero output indication. The non-zero output indication means that the amplitude memory could provide the next index in the next cycle. If there is no matching, then an indication of non-matching is

  sent to a 2008 decision generator.

  In one embodiment, three flip-flops, represented by a flag 0 (2005), a flag 1 (2006) and a flag 2 (2007), are used to keep track of non-zero data and are respectively assigned to decomposition levels. O, 1 and 2. Note that the number of necessary flip-flops is one less than the number of decomposition levels. The scales 2005 to 2007 are initially erased. When the non-zero signal from the logic circuit of equivalence 2002 is established, all the flip-flops 2005 to 2007 which have been assigned a level lower than the current level are positioned. The latch assigned to the current level is cleared. The level is provided by the logic circuit 2003 of setting the index to the level, which provides the level in response to

  the index provided by the 2001 index counter.

  "Coded" flags are memorized (for certain modes of

  in a register file), one bit for each index.

  When the non-zero signal is set, the bit associated with the current value of the index counter present in the flag of the encoded flag is set. Otherwise, if the value of the significance counter is the maximum value, the associated bit is cleared. For the rest, the value of the bit remains unchanged. The already coded output signal from the coded flag memory is the same as the new bit value associated with the current index. It is noted that, in another embodiment, the coded flags

  are not used and the already coded signal is never used.

  In one embodiment, the decision generator 2008 determines whether the current level is 3 and whether the previous level was not. Following this determination, the decision generator 2008 sets the start output signal, the start level output signal being the previous level. If the non-zero signal is established, the decision generator 2008 issues a decision in the "significant" form and also delivers the sign (00, 01) and the mantissa. Otherwise, if the already encoded input signal is established, no decision is issued. For the rest, if the scale at which the current level has been assigned is set, the decision generator 2008 issues the decision "not significant, having significant children." (10) Otherwise, the decision generator 2008 issues the decision ' not significant, and non-significant children '(11) and sets the signal fully

consisting of zeros.

  It is noted that, to implement both the frequency-based modeling and the space-based and single-pass frequency-based modeling of the horizon type, the following change is made to the meaning processing unit. 2000. The value of the significance counter 2004 is compared with a threshold, and the output signal consisting entirely of zeros is

  established only if the value of the counter is greater than that of the threshold.

  In one embodiment, the significance category input signal applied to the branch memory 1703 (shown in Fig. 21 and described hereinafter) is the output signal of the significance counter 2004. In this embodiment From the context model (for example, the unit of bit significance), the category of meaning is based on the number of memory planes, and there are seventeen different categories of meaning. This is an arbitrary choice. In another embodiment, memory maps may be combined to create less significance category. In addition, level information may be added to the memory map information to create more categories of meaning. More categories of meaning can give better lossy compression while fewer categories can

  reduce the complexity of the equipment.

  Fig. 21 is a block diagram showing an embodiment of the branch memory unit according to the invention. As can be seen in Figure 21, a memory 2101 has the space to store a decision and an indication of significance for each possible decision. In one embodiment, for a four-level decomposition with seventeen levels of significance, the number of locations of the

  memory 2101 is equal to 85 x 17 = 1445.

  To access the memory 2101, addresses are created. A counter 2102 is initially zero. When the decision generator 2008 does not set the input signal consisting entirely of zeros, the value of the counter 2102 is used to address the memory. If the decision generator 2008 sets the start input signal, the current value of the counter 2102 is stored in one of the registers 2110 to 2112 depending on the start level, which acts as a selection mechanism. Then, the

counter 2102 is incremented.

  When the decision generator 2008 sets the input signal consisting entirely of zeros, the value of the register (for example 2110, 2111, 2112) selected by the level input signal is used to address the memory 2101, and this value, plus 1, is loaded into the counter 2102. This causes the memory locations used for non-significant children of a

  non-significant parent are ignored.

  During the data delivery by the memory, the counter 2102 is decremented to output the address of the location. The delivery (as well as the decrementation) stops when the counter 2102 reaches zero. The output signal of the branch memory unit 2100 is received by an entropy encoder which appropriately encodes the decision on the desired meaning. To enable real-time operation, two branch memory units can be used, so that one is used for input while

  that the other is used for the output.

  Coefficient Alignment In one embodiment of the invention, the zero branching context model uses a non-standard 1 + Z-1 low pass filter. However, the zero-branched context model can be used with standardized filters, such as: 1 + Z- 'In order to be able to use normalized filters, it is possible to use, between the direct elementary wave filter 1000 and the context model 105 , an alignment unit, such as the alignment unit 2200 shown in Fig. 22, to compensate for the energy gained (or lost) by the non-normalized filter, which improves the compression. Since alignment allows nonuniform quantification of the lossy operation, alignment can improve the visual quality of lossy image reconstructions. In the one-dimensional case, the coefficients of each level of the branching will have a different alignment (the divisors are '2, 2, 2-f2, 4, and the multipliers are 2f2, 2, f2, 1). In the two-dimensional case, the divisors will be 2, 4, 8, 16 and the multipliers

will be 8, 4, 2, 1.

  Since the alignment simply serves to group analogous bit decisions for coding, the use of the exact normalization value is not crucial. Alignment must be reversed during decoding, so multiplication and division are both necessary. Using multipliers and / or divisors that are powers of 2 would instead provide an efficient offset by hardware equipment. When coefficients are multiplied by a power of 2, the zero bits of least

  added meaning do not have to be coded.

  However, instead of limiting the multiplier / alignment diviseum to the powers of 2, an approximation of the type * -1.5 or -2-2 + 1.5 can be used with the following method. Instead of multiplying, or dividing, the coefficients by the multiplier, or the divisor, we content ourselves with proportioning the "significant" coefficients by means of the multiplier, or the divisor. The sign / amplitude unit can be modified as shown in Fig. 23, so as to include a priority encoder "1.5", which (1) returns to the position of the most significant bit "1" if the bit next significant is "1" equally, or else, (2) returns to a position decreased by one notch relative to the position of the most significant bit "1". A truth table of a "1.5" priority coder with three input bits is

presented in Table 5.

TABLE 5

Input (binary) Output

001 O

O

011 1

1

101 1

2

111 2

  Depending on the level of the coefficient indicated by the current value of the index, a multiplexer 2302 selects the meaning from the normal priority encoder or the priority encoder "1.5". Whenever the "1.5" alignment is used, the mantissa contains N + 1 bits, where N is the value of significance. Otherwise, the

mantissa contains N bits.

  An alignment unit 2200 comprising a two-input multiplexer acting as an offset means may implement an alignment of 1 or 2. By combining this alignment with the "1.5" alignment provided by the sign / amplitude, we obtain alignments of 1, 1.5, 2 or 3, which are a good approximation of the desired multipliers in the case of one-dimensional signals, since the numbers are simpler (for example powers of 2). (For two-dimensional signals of the image type, the numbers are simpler.) During decoding, the (N + 2) th bit of the mantissa (which is not encoded) is the complement of the (N + 1) th bit when using the encoder

priority '1.5'.

  The alignment of the coefficients can be used to give zero branching and for finer and nonuniform quantification. In the case of images (two-dimensional signals), an embodiment of the transformation RTS aligns the coefficients by multiplying the frequency band by the numbers presented in FIG. 31. The multiplication by these numbers makes the RTS transformation become an approximation. very close to the waves

  elementary reconstruction of IS transformations.

  To be effective, the entropy coder must consider the alignment process. Fractional Fractional Fractional Frequency Based Context Models Another embodiment of feeder-based modeling uses fractional memory arrays or fractional bits of meanings. One implementation consists in treating each memory plane twice, so that the passages comprise a passage A1, a passage B1, a passage A0 and a passage BO. It is noted that the designations of the passages were chosen because the A1 passage deals with coefficients starting from "11" and the

  passage A0 treats those starting from "10".

  During the passage A1 associated with the memory plane S, a coefficient of the group A is significant only if the bits S and S-1 are both non-zero. during

  the passage A2, a coefficient of group A is significant if the S bit is non-zero.

  Since the two most significant bits are known, the passage B1 and the passage BO must only process the bits S-1 (assuming that S = O is the

  least significant memory scheme).

  Since the fractional memory planes differ from one to the other by a factor of 1.5 or 2 / 1.5, the alignment of the different levels can be achieved.

  grouping the desired fractional memory maps for each level.

  Fractional memory schemes provide finer modeling of data through the parent-child relationship used in the frequency-based context model. More than two passages, for example four or eight passages, can be used to obtain even finer modeling. For example, in the case of four passages, the passage All treats the coefficients that begin with "'111'". The other passages deal with '' 110 '', '' 101 '' and '' 100. '' A less fine modeling could also be used, for example, a passage could be made for only one memory plane out of two. less fine, more bits are encoded using the BC group Memory / channel management and encoder for single-pass system Memory management for coded data in the single-pass system applies to systems that memorize all data in memory and systems that transmit data over a channel In the single-pass system, the encoded data must be stored in such a way that it can be accessed in an established causal manner, so that

  to exclude less significant data without losing more significant data.

  Since the coded data are of variable length, one can call upon a

dynamic memory assignment.

  In one embodiment of the invention, the implementation encoding scheme uses 18 memory planes and therefore, assigns 18 levels of significance to the data. The encoder of a single pass system must be "causal implanted". Thus, the decoding events corresponding to a memory plane do not require information from the lower order memory planes. In the case of a single pass, all the bits coming from a branch will typically be coded before any of the bits of the next branch are coded, so that bits of different meanings will not be separated. For coders that do not use an internal state, such as Huffman coders, this is not a problem. However, many compressors

  sophisticated ones with better compression use the internal state.

  One way to solve this problem in the case of these encoders is to use 18 different encoders, maybe 18 chips constituting Q encoders. A technique that would allow the use of 9 chips encoders type Q is described in the US patent No. 097261 (Langdon, Jr.), entitled 'Data Compression for Recording on a Record Medium,' which was issued March 17, 1992. A better way is to use a pipeline type encoder to implement different virtual codes using a single hardware coder, as described in United States Patent Application No. 08/016 035, entitled "Method and Apparatus for Parallel Coding and Encoding of Data", which was filed on February 10, 1993. In such an encoder, the multiple states of a bit generator, relative to the respective probabilities, are each assigned to a portion of the data. For example, each of the 18 states could be assigned to a particular memory array for 18-bit data. Registers contained in the encoder offset means are also assigned to each part of the data. In the encoder, no interleaving is performed; each

  part of the data is simply grouped according to the bits.

  In embodiments having multiple hardware encoders or multiple virtual encoders, memory is allocated to each portion of the data. When the compression is complete, we have obtained, as a result, a

  linked list describing the allocated memory, plus the contents of the allocated memory.

  If memory overflows, the memory allocation scheme causes larger data to be written over smaller data. For example, the least significant bit of a numeric data could be overwritten first. Information describing how memory

  is assigned must be stored in addition to the encoded data.

  Figure 24 shows an example of a dynamic memory allocation unit for three categories of significance. To avoid complicating the invention, only three categories are described; typically, a larger number of categories would be used, for example 8, 16 or 18. A register file (or other storage means) holds a pointer for each category of meaning, plus another pointer to indicate the location. of memory

  free next. The memory is divided into fixed size pages.

  Initially, each pointer assigned to a meaning category points to the beginning of a memory page and the free pointer points to the next available memory page. Coded data, identified using a significance category, is stored at the memory location that is addressed by the corresponding pointer. We then increment the pointer to the location of

following memory.

  When the pointer reaches the maximum of the current page, the address of the beginning of the next free page, stored in the free pointer, is registered with the current page as a link. In one embodiment, the portion of the encoded data memory, a separate memory or a register file could be used for this purpose. Then the current pointer appears on the next free page. The free pointer is incremented. These operations cause a new memory page to be assigned to a particular meaning category and produce links to memory pages containing data pertaining to a common meaning category, so that the order

  allocation can be determined during decoding.

  When all the pages in the memory are used and there is more data that is more significant than the least significant data in the memory, a re-allocation of the memory can be performed. Three of these re-allocation techniques are described. In all three cases, the memory allocated to the least significant data is reassigned to the data more

  significant and the least significant data are no longer recorded.

  First, the page that in the current state is used by the least significant data is simply assigned to the more meaningful data. Since most typical entropic coders use state-of-the-art information, the least significant data set

  were previously memorized in this page is lost.

  Second, the page that was currently used by the least significant data is assigned to the more meaningful data. Unlike the previous case, the pointer is positioned at the end of the page and, as more meaningful data is written to the page, the corresponding pointer decrements. This has the advantage of preserving the least significant data at the beginning of the page in the case where more data is available.

  Significant do not need the whole page.

  Third, instead of the current page associated with the less significant data being reallocated, it is possible to reassign any page of least significant data. This requires that the coded data of all the pages be coded independently, this may reduce the compression finally obtained. This also requires that uncoded data corresponding to the beginning of all pages be identified. Since any page of least significant data can be rejected, we have dmunc

  greater flexibility of quantification.

  The third means may be especially useful in a system that performs a fixed rate compression on regions of the image. A specified number of memory pages may be assigned to a region of the image. Whether or not less significant data is retained may depend on the compression performed in a particular region. Note that the memory assigned to a region may not be fully utilized if lossless compression requires less than the amount of memory allocated. Performing a fixed rate compression on an image region may allow

  direct access to the regions of the image.

  Once the compression is complete, the data can be torn, if desired, to a channel or storage device, according to the order of the meanings. The various links and the various pointers will not be necessary anymore and a decoding in several passages will have to be carried out. According to another possibility, in the case of a single-pass decoding, the pointers

  pointing to the data of each meaning can be preserved.

  In some applications, some categories of meaning may not be used. For example, a 16-bit compressor can be used on a 12-bit medical image, so that the categories of meaning corresponding to the memory planes 15, ... 12 will not be used. In the case of implementation with large pages and many unused meaning categories, there is a waste of memory (when the system does not know in advance that some categories are not used), since there is no need to allocate them of memory. Another solution to this memory wasting problem would be to use a small memory (or register) to account for the respective categories of meaning. This account would keep track of the number of "no significant, no significant children" decisions that were made before any other decision was made. The memory required for these counters must be taken from the memory used for the categories of

meaning not used.

  To better utilize the total amount of memory available in the system, the ability to write data to each page from both ends can be invoked. When all pages have been assigned, any page that has sufficient free space at the end may be given a use from that end. The ability to use the ends of a page should be measured by the cost of keeping track of where the two types of data meet. Note that this is not the same as the case where one of the data types is not significant and

can be simply crushed.

  Using a channel In a system where data is transmitted on a channel instead of being stored in a memory and where memory pages of a fixed size are used (but where only one page is needed per category of meaning ), when a memory page is full, it is sent on the channel, and the

  Storage locations can be reused as soon as there has been broadcast.

  In some applications, the page size of the memory may be the size of the

  data packets used in the channel or a multiple of packet size.

  (Note that in one embodiment, two pages per level of significance can be used, so that data can be written into one while the other is read to send to the channel. In some telecommunication systems, eg ATM (asynchronous transfer mode), priorities can be assigned to packets. The ATM system has two priority levels, namely the priority level and the secondary level. Secondary packets are only issued if sufficient bandwidth is available. A threshold can be used to determine which categories of significance are given priority and which categories are secondary. Another method would be to use a threshold in the encoder to not transmit the significance categories that are less significant.

than a threshold.

  Bounded peak error loss compression In some applications, perfect (lossless) reconstruction is not necessary. It may be desirable to perform the compression by allowing a specified maximum peak error. It will be assumed that the peak error is E. This can be done by truncating the compressed data, so that all the data of less significance, which are not necessary for the realization of the

accuracy, are rejected.

  Another way to perform the compression with a specified maximum crest error is to divide (in integer division) by a value less than or equal to 2E + 1 each pixel of the image to be compressed. During the reconstruction, each pixel of the image is processed according to the following relation: output pixel = (2E + 1) x input pixel + E. (Otherwise, instead of adding E during decompression, one can perform subtraction during compression, before dividing by 2E + 1). Another way to perform compression with a specified maximum peak error is to replace division and multiplication with offsets. The offset amount is L1og2 (2E + 1A.) Since the offset is convenient, a better error specification (replacing the peak error) will be

  given by errors of the form -2n <error <+ 2n.

  What is being stated must not be confused with the quantization of the coefficients, which is a well-known technique of lossy image compression. In many lossy compression systems (eg JPEG), the transform domain coefficients are assigned a maximum peak error, which only indirectly controls the peak error of the image. A crucial difference with this technique is that the invention performs quantization on the pixels and uses a compression of

coefficients without losses.

  Quantification can also be used in the field of transformation. Many coefficients have an effect on the propagation of the peak error across the multiple levels of transformation. It is easier to determine the effect on the peak error in the case of high-pass coefficients that do not have children. We will consider a one-dimensional signal which must be coded using a maximum peak error of E. This can be done by quantifying, at + 2E, the high-pass coefficients associated with the finest detail. For a two-dimensional signal, since there are two applications of the high-pass filter, the

  HH coefficients associated with the finest detail must be quantified at 4E.

  Instead of using a quantization of the input image, we can

  order the decisions provided to the entropy coder. An example is given below.

  below. For each coefficient, if setting the coefficient to zero would not make the error present in any pixel affected by this coefficient exceed the maximum error, the coefficient is set to zero. In some implementations, only particular coefficients will be checked, perhaps only AC coefficients that have no children. The coefficients can be considered according to a greedy strategy, in which only one coefficient is considered at a time. Other strategies might consider small groups of coefficients and choose zero

  for the largest possible subset of the group.

  Of course, one skilled in the art will be able to imagine, from the

  description which has just been given for purely illustrative and not limiting purposes,

  various variants and modifications that are not outside the scope of the invention.

AFEbU = C

  Code example for RTS transformation (direct).

  Single-level decomposition void RTS (T, w, m, n) int w, m, n; int 'T; {int i, j, k: int wX, -Y; for (iO: i <n; i ++) for <jO; j <m; j ± 2) {X [j / 2] (Tfi * w + j] + T [i * w + j + l]) >> l; Y [j / 2] - T [i * w + j] -T [i * w + j + 1]; for (jO: j <m / 2: j ++) T [i * m + j] -X [j]; T [i * m + m / 2 + j] - (-X [j] + (Y [(j + 1)% (m / 2)] "2) + X [(j + 2)% (m / 2) ) 1) >> "2:

  Code example for RTS transformation (inverse).

Decomposition at one level.

  void InverseRTS (T, w, m, n) int w, m, n; int 'T; {. int i, j, int * B, 'D; for (i-o0: i <n; i ++)! for (j-0; j <m / 2; j ++) B (Bj] - (-Tli * m + j] + T [i * m + ((j + 2)% (m / 2))]) &0X3; D [(j + 1)% t (m / 2)] - ((T [i * m + j] -Ti * m + ((j + 2)% (m / 2))] + (T [i " m + m / 2 + j] "2) + 3B [j])"> 2); for (j0; j <m / 2; j ++) T [i * w + 2 * j] ((T [i * m + j] "<< 1) + D [j] +1) >> 1; T [i * w + 2 * j + 1] - T (i * w + 2 * j] - D [j]; }

Decomposition at two levels.

  Transformation RTS (direct) void R $ (T, w, <, T n nt W zn; int - T; in: i, j, k: in .: tervp; in'- X, Y: for i-0; i <n: i ++) for j-; j <: j ± 2)! o Xrj / 2] - {Ti'w + j] + T [i "vj * l] 1 >>: Y [j / 2] - TIi" w + j] - T [ i-j + l]; ter.p [iL4 + j] -X [j]; you. i "mm + = / 2 + j1- (-X [j]] (Y [(j + 1)% (m / 2)] <C: 2) + X [(j + 2)% (md2)]> 1 > 2: t for {jO:; <j-: +> for f i- r: i <n; ± 2) X [i / 2] <(eimpt [im-3 + j] em? [I + Ullr + j]) ">; vii / 2] - e.'- .-. e. ## EQU1 ## where: ## EQU1 ## (+ !! z (n / 2)] << 2) + X [(i + 2}% {n / 2}]) '>>:

Decomposition at two levels.

RTS transformation (inverse).

i -. v,., _: '* -n: Ze-a

for j: t '.

  fc _c: {j-0: j <*: * -I for (i-.::<r.12::--): r .. 7.:e<-<_:-. "-] + a (2 '= 1;' m -.- - -re -. = [2 ': -.- m; - D [_ |: for (-: <.: -)

f35 (, -O: j <- / 2:,?

  B [j] - (-e. [I'm'j] * ter [i * (j * 2)% (m / 2)) & X3 has t ([+!)% (= / 21l ((: e : [-], tje ..-: r i -, ((j + 2%)% (m / Z >>] + :: e.-z: '-.-./ 2-j] <2 - - "23j]"> 21;} for (jO; j <m / 2; j ++) f T [i * w + 2 * j] - ((temp [i * m + j] "1) + D [j ] + l)> "l; T [i * w + 2 * j + 1] - T [i * w + 2 * j] - D [j];}} 3, T:

Claims (21)

REVENDICAIONS   A method of encoding input data, characterized in that it comprises the following operations: producing transformed signals in response to the input data, where the transformed signals are produced using an onmides transformation elementary reversible; and compress the transformed signals into data representing a   version, compressed without loss of input data.   2. Method according to claim 1, characterized in that the signals   transforms comprise a plurality of coefficients.   3. Method according to claim 1, characterized in that the production operation comprises the step of decomposing the input data with at least one reversible filter of non-minimal length in order to produce a series of coefficients.   4. Method according to claim 3, characterized in that said reversible filter of non-minimum length comprises a plurality of one-dimensional filters. 5. Method according to claim 1, characterized in that the data   input include image data.   The method according to claim 1, characterized in that the compressing operation comprises the step of implant coding the transformed signals, which comprises the steps of ordering the series of coefficients and performing an implementation according to the degree of meaning of bits on the transformed signals.   The method of claim 1, further characterized by the steps of: decompressing the compressed version without loss of the input data into transformed signals; and producing the input data from the transformed signals by putting it in the form of a reconstructed version of the input data using a   reversible elementary wave transformation.   8. A method for decoding data into initial data, characterized in that it comprises the following operations: decompressing a version, compressed without losses, of input data, so as to put in the form of a plurality of signals processed; and producing a reconstructed version of the initial data from the plurality of transformed signals using wave transformation reversible elementary reversals.   9. Method according to claim 8, characterized in that the transformed signals comprise a plurality of coefficients. The method according to claim 8, characterized in that the production operation comprises the step of decomposing the input data with at least one non-minimum reversible filter to produce a series of coefficients.   11. The method of claim 10, wherein said non-minimum length reversible filter comprises a plurality of one-dimensional filters. An input data coding method, characterized in that it comprises the following operations: producing a first plurality of transformed signals in response to the input data, wherein the transformed signals are generated using a reversible elementary wave transformation; compressing the first plurality of transformed signals to put it in the form of data representing a compressed version without loss of the input data; decompressing the lossless compressed version of the input data into a second plurality of transformed signals; and producing the input data from the second plurality of transformed signals by putting them in the form of a reconstructed version of the input data using an inverse reversible elementary wave transformation. 13. An input data coding method, characterized in that it comprises the following operations: transforming the input data into the form of a series of coefficients; and encoding by implementation the series of coefficients, this operation comprising the operations of ordering the series of coefficients and performing an implementation according to the degree of significance of the bits on the series of coefficients, where a first type of coding by implementation is performed on a first part of the data and a second type of coding by implantation is   performed on a second part of the data.   14. Method according to claim 13, characterized in that the transformation coding operation comprises filtering the input data by elementary waves. 15. The method of claim 13, characterized in that the first   The type of implementation coding includes branching type coding.   16. The method according to claim 13, characterized in that the implantation coding operation comprises the operation of putting the series of   coefficients in the sign / amplitude format.   An input data coding method, characterized by comprising the steps of: transforming input data into a series of coefficients using reversible universal waves; converting the series of coefficients according to a sign / amplitude format into a series of formatted coefficients; encoding a first portion of the set of formatted coefficients using a first type of implementation encoding to produce a first bit stream; and encoding a second portion of the set of formatted coefficients using a second type of implementation encoding to produce a second bit stream, wherein the first bit stream and the second bit stream are combined in a single bit stream.   18. The method of claim 17, characterized in that it comprises   further entropy coding of the single bit stream.   19. The method of claim 17, characterized in that the first   encoding type includes a coding of the branch order.   20. Method according to claim 17, characterized in that the first part comprises the higher order bits and the second part comprises the bits. lower order.   21. The method of claim 17, characterized in that the train of   single bit represents a version, compressed without losses, of the input data.