FR2699775A1 - Computer interface for telephone services - Google Patents

Abstract

Switchable telephone line circuits (2) input to a standard interface circuit (8) which provides system isolation and power. Analogue tone signals are then converted to digital signals (7) and passed to a digital signal processor (3).The processor operates on the digital signals, representing various services and passes them, via a flash EPROM (18) and parallel exchange processor (19) to a BUS (17). The BUS distributes the output to a number of parallel computer storage sections, a flash EPROM (12), EPROM memory (13), RAM (14) and to a decoder (15) for converting the processed signals to analogue form.

Description

SERVER LINE EQUIPMENT CARD
OR Switches
The present invention relates to the use of a DSP (Digital Signal Processor) to carry out the dialogue between a server and its remote powered terminals, and, therefore, connected by wired links in direct metallic conduction.

It can be materialized by the production of a line equipment card which includes signaling interface means, arranged to detect analog signals from a line connected to said card, a signal processing processor for transforming them. into corresponding logic signals, as well as analog-digital and digital-analog conversion means of frequency signals exchanged with the terminal.

A telephone line is connected to a server by line equipment which supplies the line with the necessary current for the connected remote powered terminal as well as the various signaling signals necessary, such as the ringtone, the dialing tone or the dial tone. occupation. With the increase in the number of services offered, other tones and frequencies are transmitted, such as the tone signaling that a third party is trying to reach a busy correspondent. If a subscriber has a charge counter, to check the billing of the network operator or to be billed for the call from an immediate payment station, such as a card payphone, line must still recognize and send other frequency signaling signals. It also detects line signals.

Furthermore, the line equipment comprises, on a specific link, which is also connected to the line, a codec (encoder decoder) converting the analog phonic signals into digital signals transmitted to the connection network of the server, and vice versa.

This line equipment comprises, in addition to the codec, as many signal generators or detectors as there are signaling signals, or at least comprises means of connection to- common signal generators or detectors. The more the number of frequency signaling signals increases, the more complex, expensive, cumbersome and energy consuming the line equipment becomes.

In addition, the use of common detector circuits or signal generators requires the routing, inside the server, of the corresponding analog signals, between the line equipment and the corresponding circuits.

However, the bandwidth of the links inside the server is limited, so that only relatively low frequency signals, a few kiloHertz, can be used, while the line could transmit signals at several tens of kiloHertz. The variety of signaling signals is therefore limited.

The present invention aims to overcome this drawback.

To this end, it relates to a line equipment card for a server or a switch intended to be connected directly to stations or terminals and comprising signaling interface means, arranged to detect analog and frequency signals of a line. connected to said card and supplying, to card management means, a corresponding logic signal, by the use of analog-digital and digital-analog conversion means and of processing means.

Thus, the processing means being directly connected to the line, the high frequency signals reach them without difficulty.

Advantageously, the interface means and the conversion means are integrated into the same processing circuit comprising a signal processing processor.

Thus, contrary to the preexisting prejudice which wanted to separate the phonic signals, going to the connection network to cross it, and the signaling signals, going to the connection network, to control it, the applicant proposes to maintain together all analog signals. The processing circuit receives all the analog signals and supplies digital signals in response which nothing distinguishes from each other, except that they are transmitted to different recipients.

The gain in material is significant and does not penalize the availability of the corresponding functions, because, during a transmission, at most one or two signaling signals are generally transmitted, which does not overload the signal processing processor.

Advantageously, several lines being connected to the card, said management means are mounted on the card and there is provided management means, of the signal processing processor, in timeshare between the signals of said lines.

As mentioned previously, the processor work is limited, so that it can process several lines in timeshare. In particular, it is possible to cyclically allocate a time slot of fixed duration for processing the phonic signals, which must be digitized, or vice versa, according to a fixed rhythm, generally at 8 kiloHertz, which avoids contention in the management of the processor. signal processing and avoids loss of time.

 I1 can also be provided with other means for managing the signal processing processor, arranged to have the latter process several types of line signals.

Thus, if several types of frequency signaling signals are used, the signal processing processor is sufficient to process them.

Conversely, towards the line or lines, the signal processing processor can be arranged to generate analog line signals from corresponding digital tables.

It is thus possible to generate signals with very precise frequency, since the signal processing processor is generally controlled by a quartz. In addition, their level is also very precise and can be modified, if necessary, by a simple numerical control.

Advantageously, the card management means comprise a control unit associated with memory means arranged to receive program data coming from a central unit of the server and transmit them to the signaling interface means.

One can thus have a universal card and download it according to the type of line connected and in particular the signaling used.

In order to have a very fast signal processing processor, to process a maximum number of lines, it is advantageous to use a signal processing processor with RISC architecture (Reduced Instruction Set
Computer).

The present invention will be better understood with the aid of the following description of the preferred embodiment of the card of the invention, with reference to the single appended figure which represents a block diagram of the line interface means of the card as well as a card management microcontroller associated with memories.

The card, which will now be described, belongs to a server, or automatic switch, and comprises a line signaling interface 1 connected, here, to four analog lines, generally marked 2, through known interface circuits 8, ensuring galvanic isolation and supply of direct current to the connected substation or terminal.

A microcontroller 11 of the card is associated with an EPROM flash memory 12, an EPROM memory 13 and a RAM memory 14. A circuit 15 address decoder, controlled by a bus 17 connecting the components 11 to 14, ensures the decoding of the weights of the address and selects the corresponding component. To the bus 17 are also connected another EPROM flash memory 18 and an interprocessor exchange circuit 19, also connected to a signal processing processor 3 (DSP, for Digital
Signal Processor) of the interface 1. A link circuit 20 provides the link between a main bus 21, here of RS 485 type, external to the card, and the microcontroller 11.

In this example, the processor 3 is a TMS 320C51 processor, in this case an integrated technology circuit.
CMOS manufactured by the company TEXAS INSTRUMENTS. A quartz 4, at 40 MHz, supplies a clock signal to the processor 3. The processor 3 comprises RAM memories 5 of program and data which can be loaded from the flash memory EPROM 18, which is itself loaded at through the link circuit 20 from a central unit of the server, not shown, connected to the main bus 21.

ROM memories 6 of processor 3 contain program data as well as the tables indicated below.

Between the processor 3 and each of the interface circuits 8 is, here, interposed a codec 7 of the interface 1, ensuring the analog-digital conversion of the signals going from the lines 2 to the processor 3 and the reverse conversion in the other meaning.

It will be understood that the four codecs of this example can be replaced by a single codec used in timeshare. In particular, this codec can be integrated into processor 3 and constitute with it a single circuit having a functional unit, capable of exchanging analog as well as digital signals.

The operation of the circuits of the card will now be explained.

Analog frequency signals from lines 2, here in the range of a few hundred
Hertz to a few tens of kiloHertz, are digitized in codecs 7 and transformed into digital signals.

They are then processed by the processor 3, then, through the exchange circuit 19, the bus 17, the microcontroller 11 and the main bus 21, reach the central processing unit of the server.

The homologous digital signals coming from the central processing unit of the server follow the same path, in the opposite direction, and are converted into analog signals by the codecs 7 before being transmitted on line 2.

The analog signaling signals coming from a line 2 likewise arrive directly at processor 3, that is to say without crossing elements providing an attenuation as a function of frequency, and processor 3 compares their frequency with frequencies predetermined signage. Frequency detection is performed by performing, for example, recursive filtering on successive samples representing the amplitude of the received signal. Weighting coefficients of the intermediate results used in the stages of the digital filter fix the value of the frequency sought and the bandwidth of the filter. These coefficients can be changed cyclically to use the computing circuits of processor 3, essentially multipliers, in time shared between several frequencies sought and several lines 2 capable of transmitting these frequencies. These coefficients are stored in the ROM memory 6.

The level of the signaling signals is also compared with predetermined signaling signal thresholds, also cyclically variable and contained in the ROM memory 6. In the event of recognition, a corresponding signal is transmitted to the microcontroller 11, which, after analysis, the transmits if necessary to the external central unit to the card when, for example, a signaling message of level 3 or above, in the seven ISO layers, has been received. On the other hand, for level 2 signals, which is the link level, the card itself manages exchanges with lines 2 and locally takes a decision by controlling the interface 1 accordingly, for example by commanding the continuation of the detection. during a determined period, of value stored in the ROM memory 6.

The creation, in the processor 3, of a signaling signal of determined frequency is carried out from a sine table of the ROM memory 6 which is scanned with steps, multiples of the quartz period 4, more or less large, so that the frequency generated is higher the greater the steps.

The management of the above time sharing is carried out from control data contained in the flash memory 18 and transmitted to the RAM memories 6 of the processor 3. This data comes from the microcontroller 11, as a function of the signals which it previously received. and they also come from the external central unit.

Some of these data are permanent, for example those allocating a specific time periodically to the phonic signals.

In the case mentioned or the codec function 7 would be integrated into the processor 3, which would then by itself constitute a single processing unit for the interface circuit 1, the time allocated for this function is then increased compared to that of the present example, or processor 3 simply has to transmit digitized signals, without converting them itself.

In order not to unnecessarily occupy its digital links with the rest of the card by means of restraints, processor 3 has a DMA access mode (Direct Access
Dissertation), without intermediary.

Claims (10)

1. Line equipment card for server or PABX intended to be connected directly to stations or terminals and comprising signaling interface means (3) arranged to detect analog and frequency signals of a line (2) connected to said card and supply, to card management means (11-20), a corresponding logic signal, by the use of analog-digital and digital-analog conversion means (7) and of processing means ( 3). 2. Card according to claim 1, characterized in that the interface means (3) and the conversion means (7) are integrated in the same processing circuit (1) comprising a signal processing processor. 3. Card according to one of claims 1 and 2, wherein, several lines (2) being connected thereto, said management means (11) are mounted on the card and there are provided means (11, 18) for management , of the signal processing processor (3), in time sharing between the signals of said lines (2). 4. Card according to one of claims 1 to 3, in which other means (11, 18) for managing the signal processing processor (3) are provided, arranged to have the latter process several types of signals line. 5. Card according to one of claims 1 to 4, wherein the signal processing processor (3) is arranged to generate analog line signals from corresponding digital tables. 6. Card according to one of claims 3 to 5, wherein the card management means comprise a control unit (11) associated with memory means (12) arranged to receive program data from a unit server central office or automatic branch exchange and have them executed by the control unit (11). 7. Card according to one of claims 3 to 5, wherein the card management means comprise a control unit (11) associated with memory means (12) arranged to receive program data from a unit server central office or automatic branch exchange and transmit them to the signaling interface means (3). 8. Card according to one of claims 6 and 7, wherein said memory means comprise an EPROM flash memory (12; 18). 9. Card according to one of claims 1 to 8, wherein the signal processing processor (3) is RISC architect. 10. Card according to one of claims 1 to 9, wherein the signal processing processor (3) comprises a DMA channel.