FR2686174A1 - UNIVERSAL BUS SYSTEM. - Google Patents

Abstract

Universal bus system, to the data bus (B) to which data sources and data collectors are connected, in the form of users (P, P ') which contain signal processors (S, S') and rapid external memories (R, R ') associated with them, with bus access and interface circuits (I, I'), characterized in that the users (P ') who are not externally accessible for emulations, initializations or logic checks, are accessible from an external auxiliary command (H) for intervention in the program and data calls, via the bus (B), this command auxiliary being connected to at least one user (P) with a connection (G), accessible from the outside, for remote control and remote monitoring.

Description

The present invention relates to a bus system

  universal, to the data bus of which data sources and data collectors are connected, in the form of users contain signal processors and fast external memories, associated therewith, with circuits

interface and bus access.

  A system of this type is known from DE 39 00 348 Ai For optimal use of the surface (see DE 39 23 533 Ai), in the case of bus access arbitration, very flexible and rapid (see DE 39 28 481 Al), it is designed with a connection in several layers of integrated circuits for specific use of bus interface (cf DE 39 23 533 Ai) and has an extremely small footprint, including with regard to its mechanical constitution with its bus users, i.e. fast input / output circuits and corresponding signal processors with the bus, through

  fast external memories (see US Patent 4,698,729).

  To modify the program, initialize and

  perform a fault analysis in sub-

  systems, in particular in the connected processors, it is necessary to have a hardware access to the signal processor concerned, with a development system or a logic analyzer But in most of the users, this direct access is already hardly possible in the situation test and often quite impossible in the situation of

  due to wiring conditions and.

compactness described.

  The object of the invention is therefore to achieve, in a multi-processor bus system with several layers, and of compact construction, possibilities of freely selectable access by an observer, to user processors, for analysis of

  faults and interventions in the program.

  This object is achieved according to the invention with a bus system of the aforementioned type in that the users who are not accessible from the outside for emulations, initializations or logic checks, are accessible from an external auxiliary command. for interventions in the program and data calls, via the bus, this auxiliary control being connected to at least one user with a connection, accessible from the outside, for remote control and remote monitoring. According to this solution, it suffices to design or arrange, electrically and mechanically, at least one of the users connected to the central bus, so that it is physically accessible, directly or in any case by its rapid external additional memory. , for an at least temporary auxiliary control command In this case, it is possible to introduce, from the outside, a control data block which is sent, in an arbitrary manner, to the bus system, by this processor interface of signals (hereinafter also referred to as interfacing circuit), associated with this user, in order to trigger the current interventions concerned in the user to be monitored, not physically accessible, by a remote control monitoring register in the circuit target interfage. These interventions can be the interrogation and the retransmission of a current configuration of instruction bits, after a passenger stop or an idle operation of the monitored user, this switching as well as the return to normal operation being supplied, from the auxiliary monitoring command, with the command data block; it can also be the initialization of selection from a range of prepared function programs or even a direct intervention in programming, in order to modify a signal processing program existing in the user controlled But by means of the external auxiliary command it is also possible to check whether the external memory of any user contains correctly generated data blocks, under addresses which relate specifically to the system These blocks can be called up, for verification during the current operation of the bus, from the memory of the user concerned and be stored in an intermediate manner in the associated interfacing circuit, in the monitoring register, until access to the bus is possible in auxiliary control, for transmission to external operations. The remote control data block is sent, as the feedback thus triggered, coming from the monitored user, in the interfacing circuits, by the monitoring registers, in order to avoid collisions with operating data, but for the rest it is transmitted as an ordinary data block (as a rule, however, with the highest arbitration priority possible) to the additional external memory, having precisely at this instant the reception function, of the signal processor of the user, therefore addressed and treated for the rest as an ordinary data block. Thanks to the means according to the invention, it is therefore possible, in the test situation as in operation, to access any users of the bus, from a single hardware interface and to exchange, as operating data ordinary, control instructions and control information, regardless of the type and direction of transmission of ordinary function data, by use of the bus protocol, in any case organized for operation, this surveillance information however receiving timely S high priority of current arbitration This is how rapid direct access to the user concerned can be achieved by its bus interface, with any direction of data transmission, to hinder as little as possible the normal operation of this user, through the monitoring function, through the quick memory buffer

  external, during the interface remote control.

  Various other features and benefits

  of the invention appear from the detailed description

  which follows An embodiment of the invention is shown by way of non-limiting example on the

attached drawing.

  The single figure is a unipolar block diagram, symbolically simplified, of several users who through interfacing circuits, which are associated with them, have access to a common bus, as transmitters and receivers of

data.

  As described in detail in DE 39 00 348 A 1 already cited, for users P, P ', connected to bus B insofar as these are not fast input / output circuits of programmed signal processors S 'which generate data D, to send them to other users P', or to process data D 'which they have received from other users P Each of these users P, P' can therefore serve as both a data source and

of data collector.

  To reduce the bus B occupation times as much as possible, after a user P, P 'has

2686174

  had access, by an arbitration procedure (cf DE 39 28 481 Al) for a transfer (transmission or reception) of D, DI data, the D, Dl data outgoing or incoming are not delivered or received directly by the processors of signals S, Si, but are memorized in an intermediate manner in external fast memories R, RI, with optional access (with regard to processors, external RAM) In the event of authorized access to the bus, the call or the storage of the current block of data D, D 'is carried out by means of an interfacing circuit I, Il (system bus interface) associated with a user P, P', a guiding information being completed from an intermediate interface memory Z, Z The data block D, D 'finally delivered to the bus or received by it, contains, in addition to the signal information proper, indications of origin and destination for the unequivocal identification of the source and for targeted storage in ns a specific user P 'receiver, and in addition additional information relating to the urgency of access to the bus (arbitration characteristic) as well as internal control information, in particular concerning the length of the data block D to currently transmit and, on the reception side, to memorize in an intermediate manner in the register of the

external memory R '.

  For the initialization of determined functions in determined users P, Pl, namely for example for the initialization of the system but also for the adaptation of a user P, P 'determined in the complete system already initialized for other tasks or modified tasks, it is advantageous to have targeted external hardware access to the user's S, SI processors, for example by means of an emulator in order to modify the internal signal processing program or by means of a monitor (keyboard console and screen) for data monitoring, designated here, generically, by temporary auxiliary control HA because of the extremely compact nature of the electrical and mechanical construction in several layers of these systems multiprocessor complexes (see US patent 4, 698, 729 and DE 39 23 533 A 1), without counting the realization of numerous functions inside the circuits of an integrated circuit d 'specific use, a large number of users P, P' are not accessible for external direct access for interrogation of the voltage on a resistor or the supply of

  signals in specific circuit paths.

  It is therefore planned, according to the invention, to equip each user P, Pl directly or in any case its bus access interfacing circuit I, I ', with a monitoring register 0, 0' (which can be realized as part of a global memory in which is defined also the intermediate memory Z, Z ') and to equip a reduced number of users P, in any case at least one, favorably designed and configured for a external access, of this multiprocessor bus system, with an electromechanical connection G for the monitoring and intervention function of the temporary auxiliary control H. This connection G does not expediently act directly on the signal processor S, SI associated , but like the bus access interface circuit I, I ', associated, via its external memory R, so as not to hinder the functional exchange of data D, D' in

the bus.

  By means of the auxiliary control Hl indirectly connected to bus B,  by this user P accessible from the outside,  it is possible to introduce,  for monitoring or influencing operation,  in any other part of the bus system,  a command data block d,  externally generated,  and to store it in an intermediate manner in the fast external memory R,  who,  in the event of an interface call,  by the interfacing circuit I,  performs specific functions in a specific user P ',  connected in a completely different way to this bus system,  but not accessible externally,  or difficult to access This is how it is possible to ensure that in the user P 'concerned,  signal processing is either switched to step-by-step monitoring or is completely stopped,  until the auxiliary command H executes,  for example,  a fault analysis and,  after a change of program,  normal operation is again authorized For this,  the monitoring register 0 means that in the user P,  used for auxiliary control H,  this command data block d obtains as high priority for access to the bus as possible,  to make operative,  as quickly as possible,  for example program changes in user P,  called by bus B,  or to be able to call bit patterns without delay,  currently

  concerned, from user P 'to monitor.

  In this user P 'to be monitored, the remote control register 0' also means that the command data block d is not treated at the user P 'as data to be processed for the ordinary operation of the bus, but that the 'information Dl of interest is stored in an intermediate manner by the processor S' in the external memory R 'and is then transmitted, when accessing the next bus, by the interface circuit I' to the external memory R to which is connected the auxiliary control H. It therefore suffices with a single user P of bus, physically accessible, externally, to act on any other user P 'any, not accessible either externally, so as to a 2686174 remotely controlled independently of the operating data of the user P and of the direction of transmission thereof, namely via the bus of the system B, in order to initialize for example this user Pl or to reprogram it check or check only its operation in current service.

Claims (6)

  1 Universal bus system, to the data bus (B) to which data sources and data collectors are connected, in the form of users (P, P ') which contain signal processors (S, S') and fast external memories (R, R ') associated with them, with bus interface and access circuits (I, I'), characterized in that the users (P ') who are not not accessible from the outside for emulations, initializations or logic checks, are accessible from an external auxiliary control (H) for interventions in the program and data calls, via the bus (B), this auxiliary control being connected to at least one user (P) with a connection (G), accessible from the outside, for the remote control and the remote monitoring.   2 bus system according to claim 1, characterized in that the auxiliary control (H) at the user (P), accessible from the outside, can be   switched to its signal processor (S).   3 Bus system according to any one of   claims 1 or 2, characterized in that the   auxiliary control (H) at the user (P), accessible from the outside, has access to the interface and bus access circuit (I), via its memory (R) external.   4 Bus system according to any one of   claims 1 to 3, characterized in that the   interfacing circuits (I, I ') include monitoring registers (0, O') for the intermediate storage of a control data block (d), currently triggered by the auxiliary control (H) and, if necessary also, for the intermediate storage of data (DI) to   retransmit to the auxiliary control (H).   Bus system according to any of   claims 1 to 4, characterized in that the   information triggered or called by the auxiliary control (H) has the highest priority for access to the bus.   6 Bus system according to any one of   Claims 1 to 5, characterized in that the control   auxiliary (H) is a development system for programming interventions in processors (SI) of users.   7 Bus system according to any one of   Claims 1 to 6, characterized in that the control   auxiliary (H) is the screen console of a test system also allowing interventions in the   current functioning of a user (Pl).