FR2669171A1 - Autoadaptive, multi-standard time base for TV monitor - Google Patents

Abstract

The invention relates to a time base for a TV monitor, of the type comprising signal generation means such as, particularly, horizontal and vertical scanning control signals, horizontal and vertical suppression control signals, and clamp control signals, allowing an image to be viewed on the screen of the TV monitor, the time base comprising: - means (13) for memory storage of time base parameters corresponding to various predetermined standards; - means (11) for identifying the standard of the video signals received; - reprogrammable means (14) for generating control signals, - the reprogrammable means (14) being driven by the means (11) for identifying the standard received by means of parameters contained in the memory storage means (13).

Description

 Multistandard time base autoadaptative for TV monitor.

 The field of the invention is that of time bases for television monitors.

 A time base for a TV monitor consists of a set of electronic circuits responsible for generating control signals for displaying an image on the monitor screen. These signals act directly either on the means of horizontal and vertical deflection of the electron beam of the cathode ray tube, normally located at the rear of the cathode ray tube, or on the video signal itself. The time base elaborates the different signals from the synchronization signal applied to the monitor.

 These signals are, in known manner, generally five in number. There is first the blocking signal, also called "clamp" which allows the calibration of the reference level of the video signal at the beginning of each line. Next are two scanning signals, a vertical scanning signal determining the duration of each frame, and a horizontal scanning signal determining the duration of each line. Finally, two deletion signals, one called horizontal suppression signal to inhibit the visualization during the line return, and the other called vertical suppression signal to inhibit the visualization during the frame return, are provided in the existing time bases.

 Receiving a TV standard assumes that the reception monitor's timebase can generate the previous five signals.

There are TV monitors with different time bases capable of generating each of the control signals corresponding to a standard, depending on whether the received television signal corresponds to one or the other of these standards. In mainstream television, we know the PAL / SE standards
CAM and the American NTSC standard. The change of standard control comes from the reception channel change detection, the channel change being caused by the user. The different reception channels are distributed on the TV control panel according to the reception standard corresponding to the channels. Thus, the current television sets for receiving different standards have as many different time bases as they allow the reception of different standards.

 The main drawback of existing TV monitors is that the fact of requiring different time bases implies a higher cost price.

 In addition, it is not possible to change the TV monitors of individuals so that they can receive emissions coded according to a standard different from that originally planned.

 Moreover, in the military field, there are many standards for receiving signals, each standard being specific to a different origin of the signals. It is thus often necessary to display radar images on a screen, and, because of the specific standard of the radar signals received, it is advantageous to have a time base adapted to these signals, in order to confer a good definition on the radar. image on the monitor screen. A number of video lines are then associated with a number of radar scan lines. The disadvantage is that these monitors can no longer be used for other applications and are therefore dedicated to a certain category of radars.

 In addition, the time base is specifically defined for each type of monitor, the video standard depending on the image quality and characteristics of the monitor (dimensions, remanence).

 Another disadvantage of existing systems is that they do not include means for troubleshooting time bases when they fail.

 The present invention is intended in particular to overcome these shortcomings of the state of the art.

 More specifically, it is an object of the present invention to provide a time base for a TV monitor that is adaptable to different video signal standards.

 Another object of the present invention is to provide such a multistandard time base that is programmatically reconfigurable to allow the reception of video signals according to new standards.

 Another objective of the present invention is to provide such a multistandard time base ensuring automatic self-adaptation of the TV monitor display standard, by recognizing the standard of the received TV signal.

In other words, it is a question of adapting the time base of a TV monitor to different standards of received TV signals, in order to allow a correct visualization of these different signals.

A complementary objective of the present invention is that such a multistandard time base can generate a test pattern on the monitor screen
TV, to facilitate a possible troubleshooting.

 A further object of the present invention is to provide such a multistandard time base which is of small size and low cost.

These objectives, as well as others which will appear subsequently, are achieved according to the invention by means of a time base for a TV monitor, of the type comprising signal generating means such as in particular control signals. horizontal and vertical scanning, horizontal and vertical suppression control and clamp control, for viewing an image on the screen of said TV monitor, said time base comprising:
means for storing time base parameters corresponding to
different predefined standards;
means for identifying the standard of the video signals received;
reprogrammable means for generating said signals of
control, said reprogrammable means being controlled by said
means for identifying the standard received by means of said parameters
contained in said storage means.

 Advantageously, said standard identification means comprise means for extracting the frame sync signal from said received video signal, means for counting the number of lines present in a frame, as well as means for measuring the time duration of said frame. frame.

 Preferably, said standard identification means comprise a transcoding table providing data identifying said identified standard according to said number of lines present in a frame and the time duration of said frame.

 According to a preferred embodiment of the present invention, said standard identification means comprise noise filtering means affecting the received signal, said filtering means emitting a standard change signal only after confirmation of said change on several clock shots.

 The filtering means therefore make it possible to ensure that there has indeed been a change in the standard of the video signals received, and that this change of standard does not result from disturbances due to the medium of propagation of the video signal.

Advantageously, said filtering means consist of:
- apparent change of standard detection means;
- Stability confirmation means on several clock ticks after
apparent change of standard, and provide standard change information and the value of the new standard after each stability confirmation following an apparent change of standard, said apparent standard change detection means cooperating with comparison means of the new apparent standard with the current standard.

 In this way, if the new apparent standard is equal to the current standard, the current standard is maintained and there is no interruption in the operation of the time base. This corresponds to the case where noise affecting the signal caused an apparent (temporary) detection of change of standard, without (hypothetically) the standard having actually changed.

 Preferably, said means for storing time base parameters consist of a set of pages each containing the parameters corresponding to a separate standard, said storage means being addressed on the one hand in MSB by a loading logic for the selection one page and the other LSB by said reprogrammable means for reading and transferring all the parameters of said selected page.

 Advantageously, said loading logic controls the loading of said parameters into said reprogrammable means according to said identified standard.

 According to an advantageous embodiment of the present invention, said reprogrammable means comprise counters loaded by said parameters contained in said storage means, said parameters corresponding to said identified standard.

 According to this embodiment, said counters advantageously cooperate with flip-flops to generate said control signals.

 According to an advantageous embodiment of the present invention, the time base according to the invention also comprises a pattern generation module generating synchronization signals for displaying a predetermined pattern on the screen of said monitor.

 Preferably, the time base according to the invention comprises a synchronization signal selection mutiplexer coming either from said pattern generation module, or from said standard identification means, said selection being controlled by an external target selection signal.

 Advantageously, said parameter storage means corresponding to said different standards also comprise parameters corresponding to said pattern.

 Preferably, said parameters corresponding to said pattern are located from the address $ 0H of said storage means, so that when said time base is turned on, said parameters corresponding to said pattern are read by said means for generating said control signals to display said pattern on said screen of said monitor.

 According to a preferred embodiment, the pattern selection is generated when no standard is recognized by said standard analysis means.

 Preferably, said pattern generation module, said standard analysis means and said means for storing said parameters are made from LCA (Logic Cell Array) circuits.

 The realization of these means from reprogrammable circuits makes it possible to reconfigure the time base so that it can recognize new standards. This makes it possible to adapt the existing monitors to obtain a maximum definition of the image.

Other features and advantages of the present invention will appear on reading the following description of a preferred embodiment of the invention, given by way of illustration and not limitation, and the appended figures in which:
FIG. 1 is a block diagram of a preferred embodiment
of the multistandard time base according to the present invention;
FIG. 2 is a block diagram of the contents of the analysis module of FIG.
standard of Figure 1;
FIG. 3 represents the principle of the extraction of the sync signal
frame made in block 20 (fig.2) included in the analysis module of
standard of Figure 1;
FIG. 4 is a block diagram of the standard filter block of FIG.
Figure 2;
FIG. 5 is a timing diagram corresponding to the various signals
present in the standard filter block of Fig. 2;
- Figure 6 shows the organization of the chrono generation block
metric of Figure 1;
FIG. 7 represents the structure of the configuration table of the
figure 1;
FIG. 8 shows the chronometry of the line counter included
in the frame analysis module of FIG.

FIG. 9 represents the structure of the generator module 10
of Figure 1.

 FIG. 1 is a block diagram of a preferred embodiment of the multistandard time base according to the present invention.

 The self-adaptive time base according to the invention comprises five modules: a pattern generation module 10, a standard analysis and identification module 11, a loading logic module 12, a module 13 comprising a table configuration and a chronometry generation module 14.

 The operating principle of the time base according to the invention is as follows: when the time base is turned on, an MST signal goes from the low state to the high state and the loading logic module 12 positions commands to initialize modules 10,11 and 14.

This initialization consists in positioning the chronometry generation module 14 according to parameters associated with a pattern. Thus, when the time base is turned on, a pattern appears on the monitor screen, until the standard analysis module 11 has recognized the standard present on the input.
SYH. These initialization commands are conveyed by the Mode bus which programs the reading mode of the module 13, also called the configuration table, by the Adr MSB bus which points to the appropriate pages of the configuration table 13, and by the serial authorization signal. AUTOS is in the high state (binary value 11111).

 Modules 10, 11 and 14 have the support of making reprogrammable logic circuits of the Logic Cell Array (LCA) type and of the read-only memories. The chronometry generation module 14 reads on a parallel data bus DONPAR data it points through the Adr LSB bus in the configuration table 13.

The chronometry generation module 14 also loads the standard analysis module 11 and the pattern generation module 10 with data present in the configuration table 13 by the serial link DOUTE DIN2,
DOUT2 and DIN1. Since the AUTOS signal is at 1, this serial link is passing through the AND gate 15.

When the loading of the initial configuration is finished for the modules 10 and 11, the chronometry generation module 14 sends to the loading logic 12 an end of loading order FDC. The loading logic 12 then modifies the state of the AUTOS signal by setting it to 0. The serial link
DOUT5, DIN2, DOUT2 and DIN1 is thus made inactive since the output of the AND gate 15 is kept at 0. The modules 10 and 11 no longer need to be loaded since they are in their final configuration. .

 When the time base detects a change of the signals present on lines CHSTD (change of standard) and SELMIRE (selection of the target), a reconfiguration of the module 14 of chronometry generation is launched. The read mode programming mode bus of the configuration table 13 and the adr MSB pointing bus of the page corresponding to the desired standard are then activated. The configuration table 13 includes parameters relating to different standards, as will be specified below, with reference to FIG.

The desired standard number is provided by the standard analysis module 11 and is encoded on an STDV bus connecting the modules 11 and 12. This coding consists in giving a number to each of the standards stored in the configuration table 13. According to a preferred embodiment of the present invention, eleven standards are memorized and numbered from one to eleven, the standard bearing the number 0 being a particular standard corresponding to the pattern.

After detecting a reconfiguration request, the chronometry generation module 14 is reconfigured by reading parameters on the bus
DONPAR. The module 14 signals the end of its loading by an end of charging pulse FDC.

 The chronometry generation module 14 elaborates all the control signals required for the vertical and horizontal scanning, clamp and video suppression circuits. These signals are typical of the video standard applied to the monitor input.

 The time base according to the invention therefore makes it possible, from measurements of the temporal characteristics of the synchros contained in the video signal, to recognize a given standard. I1 then automatically generates the control signals specific to the input signal which make it possible to obtain an image on the monitor screen.

 The following description of the contents of the various modules used in the present invention will provide a better understanding of the operation of the time base according to the invention.

 FIG. 2 is a block diagram of the content of the standard analysis module 11 of FIG. 1.

 The standard analysis module 11 includes a block 20 for extracting the frame sync from a composite sync signal SYH. The signal SYH has previously been processed by a device for suppressing double pulses present in interlaced scanning chronometry, this device not being shown. The extraction of the frame sync signal is based on a discrimination of the width of the signal SYH, as represented in FIG.

 FIG. 3 represents the principle of the extraction of the frame sync signal produced in the block 20 (FIG. 2) included in the standard analysis module 11 of FIG. 1.

 The SYH composite sync signal (line / frame) has rising and falling edges between which is included the useful signal. The separation of the frame sync is performed by two-beat width discrimination p and q. A counter is started at each pulse start, after having been loaded by a value N, with qmin> N> pmax, and operates in counting mode. When it reaches the value 0, the state of the SYH composite sync is observed. If the sync signal SYH is 0, it is a start-of-line sync, and if the sync signal SYH is one, it is a start-of-frame sync. The standard analysis is therefore performed by detecting two parameters, the top frame and the top line.

 The clock counting the counter is HORL1 (fig.2). The clock signal HORL1 is produced by a free oscillator (not shown) resynchronized by horizontal sync.

 FIG. 2 also shows two blocks 21 and 22 receiving the frame sync from block 20 which perform a characterization of the received frame. Block 21 counts the number of lines present between two consecutive frame sync and block 22 measures the time duration of the frame.

 Block 21 comprises a counter whose clock signal is the line sync SYH. The chronometry of this counter is represented in FIG. 8. The counter is reset to the rhythm of two frame sync pulses according to the chronometry defined by the CLNLI signal (FIG. 8) and delivers, at the end of the counting phase, the number of lines present. per frame between two consecutive frame sync on an NLL bus The data on the NLI bus corresponds to the number of lines per frame. This information is available during phase 2 for standard analysis.

Block 22 also includes a counter whose clock is constituted by a real time clock HORL2. The counter is reset synchronous fanon at the end of 2. It delivers at the end of the counting phase 1 a number corresponding to the time duration of the DTT frame in no clock, the clock being HORL2. We have:
DTT = T, / Th where: - Tr is the recurrence of the frame sync;
- Th is the period of the HORL2 clock.

 The DTT information is available during the phase (p2 for standard analysis.

 A coding table 23 receiving the data DTT and NLI performs the recognition of the standard. Each standard is characterized by a number of lines (625, 1125, 1023, ...) and a frame period most commonly associated with a frequency (50 Hz, 60 Hz, 70 Hz, ...).

 The following table shows the typical values of the p, r, q, and j times for different numbers of lines.

Nbr. Freq. Between lines (fiv) laced 625 50 yes 4,7 59,3 27,3 4,7 625 60 yes 2,67 50,6 24 2,67 1125 60 yes 2,73 26,9 12,79 2, 02 1023 70 yes 2.75 25.18 11.96 2 909 60 no 3.37 15 5.79 3.37
To take account of the fluctuation of the image renewal frequencies, each standard is in fact associated with several pairs NLI, DTT.

 The eleven standards are each encoded by STD information defined on four bits. This information is available at the end of each phase 2 (FIG. 8) at the output of the transcoding table 23.

 The STD information is provided to an analyzed STD filter block 24 which suppresses spurious variations of the STD bus as shown in FIGS. 4 and 5.

 If a received standard is not recognized, the value STD = 0 corresponding to the target is read in the transcoding table 23.

 FIGS. 4 and 5 respectively represent a block diagram of the standard filter block 24 of FIG. 2 and a timing diagram corresponding to the various signals present in the filter block 24.

 The four bits of the STD bus are sent by a clock pulse H in a register 40. The clock H has a frequency half that of the signal SYTR. The four bits corresponding to the previously received STDC standard are stored in a register 42. At the next clock pulse H, an EXCLUSIVE OR device 41 compares the current STDR standard with the previous STDC standard. The result of the comparison is four bits which are summed by an OR gate 43. In case of difference between the two standards, the summator 43 provides a logic level "1" on its output. This result called EVOL is recorded in a device consisting of three registers forming 44,45,46 digital delay lines. The outputs of these three registers are connected to an OR gate 47 summing the output bits of these registers 44, 45, 46 with the current output value of the OR gate 43, and this at each clock pulse H. The output of the OR gate 47 is connected to a flip-flop D 48. The flip-flop D 48 provides on its output a value which is associated with the value present on the input of the flip-flop D 48 by a logic function 49. This device allows the creation an impulse if there has indeed been a change of standard. The XCHST output of the AND gate 49 thus goes to "i" during a clock period and the current standard is stored in a D flip-flop 50 outputting a four-bit STDP signal, relative to the standard to be programmed. The XCHST signal therefore corresponds to a standard changeover clock.

 The device of the block 24 therefore gives priority to any change and delays the change of standard decision until the stability of this standard. According to the embodiment described, the change of standard decision is delayed by four clock strokes, after receiving a different STD standard and the device verifies that the STD signal does not change during these four clock strokes.

 Of course, other standard change verification means are conceivable, and the embodiment described is only one embodiment among others.

The STDP and XCHST signals are supplied (FIG. 2) to a validation block which takes into account the external notion of selection of the test pattern.
SELMIRE. This command has priority over STDP and the STDI internal standard responds to the logical equation:
STDI = STDP. SELMIIRE * + (STD = 0). SELMIRE
*: reverse logic
The signal SELMIIRE can come from a user's order (actuation of a switch) and / or an OR logic whose inputs respectively correspond to a lack of video signal (unplugged cable, ...) and to a non recognition of standard (non-existent synchro, ...).

 The validation block therefore makes it possible not to select the standard of the video signals received if the SELMIIRE function is activated. This function makes it possible to display the pattern on the screen of the monitor, even if the time base according to the invention identifies the standard of the video signals received.

Before requesting a new operational loading of the chronometry generation, the device must confirm that there has been a difference between the internal standard STDI and the validated standard current STDV. Indeed, on a parasitic detection, there is internal request for change of standard by XCHST for a value of standard STDP and this although the standard STDV is equal to
DPFS. The aim of the evolution analysis block 26 is to make a comparison between the register containing STDP and the register containing SIDV. This comparison is performed by an EXCLUSIVE OR. If there is a difference, the STDP standard replaces the STDV standard and the reconfiguration is requested by CHSTD at the loading logic 12 (fig.1).

 The chronometry is based on the SYTR frame sync divided by two.

If there is no sync, SELMIRE is activated by external means and the clock is replaced by SYTRMI (frame synchronization).

 FIG. 6 represents the organization of the chronometric generation block 14 of FIG.

 The chronometry generation block 14 comprises four sets 60, 64, 67 and 70 reconfigurable to each standard.

The assembly 60 consists of two counters 61 and 62 and a rocker
JK 63. The counter 61 delays the signal SY by a duration N1 and the counter 62 delays the signal delayed by N1 by a duration N2. The combination of the counters 61 and 62 and the flip-flop 63 makes it possible to generate a pulse SY1 of duration N2 delayed from the start of sync SY by a duration N1.

 The assembly 64 consists of a counter 65 and a JK flip-flop 66 making it possible to generate delayed pulses SY2 of duration N3 with respect to a sync start SY. The SY2 pulses can be inhibited by an external Sup.Ext suppression command. 64. This signal for canceling sync occurs when you reach the end of the line.

 The assembly 67 consists of a delay counter 68 N4 and a flip-flop JK 69 producing a generation of slot SY3 of duration N4 from the detection of the signal SY.

The assembly 70 makes it possible to position external states specific to each standard, in particular for the generation of the double pulse of interlaced standards, the safety devices, etc. The set 70 is in particular followed by a
DAC (analog-to-digital converter) not shown.

 Depending on the type of monitor used for viewing the received signals, different combinations of sets of types 60, 64 and 67 are used.

Thus, according to a specific embodiment of the present invention, when the time base is to generate clamp, horizontal and vertical scan, and vertical and horizontal suppression signals, the sets of the following types can be respectively used:
- Type 60 assembly for the generation of the clamp signal;
- Set of type 64 for the generation of the horizontal scanning signal;
- Type 67 assembly for the generation of the vertical scanning signal;
- set of type 60 for the generation of the suppression signal
horizontal;
- set of type 60 for the generation of the suppression signal
vertical.

 We can therefore have to implement different sets of the same nature as needed.

 On the other hand, in the case of monitors requiring a different number of control signals, plus or minus five, the present invention also applies, since it is easy to generate other control signals, as needed. .

The clock H for controlling the sets 60, 64 and 67 is either the clock HORL1 for line chronometry, or a horizontal synchronization signal SYHB for the frame type chronometry. The synchronization signal
SY is then respectively the horizontal sync signal SYHB for the line sync or the vertical sync signal SYTRB for the frame sync.

The synchro signals SYHB and SYTRB are selected by a multiplexer 16 (FIG.1) which selects the chronometry source. For a source, the sync signals SYHs and SYTRB respectively correspond to signals
SYHMI (horizontal synchronization pattern) and SYTRMI (frame synchronization pattern). For an external source, they correspond respectively to SYH and SYTR signals. The control of the multiplexer 16 is provided by the signal SELMIRE.

 The chronometry generation block 14 consists entirely of LCA (Logic Cell Array) circuits and is therefore entirely reconfigurable for each standard. The reconfiguration is effected either by modifying the programming parameters N1 to N4 of the counters 61, 62, 65 and 68, or by modifying the production of each synchro, using the appropriate set 60, 64, 67.

 FIG. 7 represents the structure of the configuration table 13 of FIG. 1.

 The configuration table 13 contains all the programming parameters of the programmable and reconfigurable logics. It includes in particular the data necessary for the control of the chronometry generation module 14, and also the delay and duration values N1 to N4 whose different combinations each correspond to a specific standard. Table 13 is divided into 16 pages of 4 Kmots. At the top of the stack of the table, up to $ FFPH, on four pages, are contained the data from the modules 10,11 and 14. These data are addressable by the bus MSB Adr and correspond to those sent for the generation of the test pattern, for standard analysis and for the generation of chronometry loaded at initialization (test pattern).

An address on this bus is used to select the appropriate parameter block in the configuration table (target, standard 1, standard 2, ..., standard n). In the lower part of the stack of the table are the data relating to each of the stored standards, the data corresponding to the pattern starting at the address $ 0H. All these data of the different standards are available on the bus
DONPAR, by sending an LSB address on the Adr LSB bus by the chronometry generation module 14. Sending LSB addresses allows scanning of the selected standard block for loading.

 The presence in the low zone of the data associated with the test pattern is explained by the fact that one can have the following sequence: initialisation (test pattern), reconfiguration (one of the eleven standards), standard failure (no identification) and therefore activation of the signal SELMIRE, reconfiguration associated with the pattern (STDV = 0).

 Since the configuration table 13 is made from LCA circuits, it is easy to modify its parameters, and thus adapt the time base according to the invention to new standards. One can thus program a number of sets of very important standards.

The generation of the test pattern is provided by the module 10 which delivers a signal
SYHMI of horizontal sync (start of line) in mode, a signal SYTRW of frame sync in mode and three bits of RGB on a video bus RGB.

 FIG. 9 represents the structure of the pattern generation module 10 of FIG. 1.

The pattern generation module 10 comprises an interlace mode synchronization generation block 90. The block 90 provides, from the clock signal HORL1 which is the pixel clock for the target mode, the following signals:
- SYHMI line start sync;
- SYHMD shifted sync of half a line for the second frame;
- signals on an AdrLI bus allowing the positioning of the signals
video in a line.

 The AdrLI bus signals are generated by a counter whose control clock is HORL1. The start of counting of the counter is triggered by a global reset when powering on (MST) and selecting the pattern (SELMIRE). The reset of this counter is performed at each end of line.

 The SYHMI and SYHMD signals are summed by a block 91 and the summation result is supplied to a frame sync generation block 92. Block 92 provides the SYTRMI frame sync and data on an AdrR bus for positioning lines in an image. This data is generated by a counter whose clock signal is the logical sum (OR function 91) of SYHMI and SYHMD signals. The reset of the counter is performed at each image end, for example after 1023 clock ticks.

 The SYTRMI frame sync signal is supplied to a set of three blocks 93, 94, 95 for generating a pattern having slow vertical scrolling on the monitor screen. Such scrolling allows in particular to avoid local burns of the surface of the screen.

An image counter 93 advances the offset of the circular counter on a CO bus. This offset is provided to a scroll management block 94 also receiving the INIB and PAS signals. The INIB signal is an inhibition command programming the output DEF bus of the block 94 to 0. In this state, there is no image shift and the latter is therefore fixed. The command
NOT changes the scrolling speed of the image on the screen:
If PAS = 0 DEF = CO
If PAS = 1 DEF = CO x 2
Block 95 performs the addition between the internal counter AdrR and the scrolling value DEF. The resulting sum is on an ADRRE bus. This sum constitutes an address.

The sequencing of operations is as follows:
First picture: Starting address ADRRE = ADRR (0)
count of ADRRE = 0 to ADRRE + number of
lines per frame
Second picture: Starting address ADRRE = ADRR (0) + DEF
count of ADRRE to ADRRE + number of lines
per frame
DEF = f (CO (2nd image), NOT)
Third picture: Starting address ADRRE = ADRR (0) + DEF
DEF = f (CO (3rd image), NOT)
count from ADDRE to ADDRE + number of lines
per frame
The addresses of the bus ADRRE are provided to a block 96 containing a table of sight. This table contains the information constituting the image. More precisely, it contains NxP pixels where N is the number of lines per image (ADDRE) and P the number of pixels per line (AdrLI).

Each pixel is encoded by three RGB bits. The information constituting the target is admitted into a buffer register 97 driven by the clock signal HORL. The buffer register 97 may for example be constituted by a flip-flop
D whose contents can be reset by a synchronization pulse
SYNCHRO from module 14 (Fig. 1). This pulse makes it possible to suppress the video signal during the horizontal scanning generated by the SYHB and
SYTR ,.

 Blocks 90,91,92,93,94,95 and 97 are made from LCA circuits, which allows their reconfiguration, for example to display a different pattern.

Block 96 containing the table of sight is for example made using a read-only memory (ROM). The module 10 generation of pattern can thus be made from two circuits.

 As already stated, the generation of a test image constituted by the test pattern makes it possible to replace the faulty incident video, to perform troubleshooting operations and validation of proper operation associated with logistics and industrialization.

 The pattern is also used to provide continuity of service in synchronization signals necessary for the operation of the standard analysis module 11.

 The present invention applies of course to all types of existing monitors, whether television screen type or other. The invention is particularly applicable to hardened monitors used in the military field in which the standards are varied. Hardened monitors are monitors that are protected against mechanical problems (shocks), against electromagnetic impulses (lightning protection) or against radiation emitted by the monitor.

 The application of the present invention to these monitors makes it possible, for example, to display, with a maximum of definition, the images received and, in the case of viewing radar signals, to assign for example to each type of radar signal a predetermined standard associating a number of video lines to a number of radar scan lines.

Claims (15)

 A time base for a TV monitor, of the type comprising means for generating signals such as, in particular, horizontal and vertical scanning control signals, horizontal and vertical suppression control and clamp control, enabling the visualization of a image on the screen of said TV monitor, characterized in that it comprises:  means (13) for storing time base parameters  corresponding to different predetermined standards;  means (11) for identifying the standard of the video signals received;  reprogrammable means (14) for generating said signals of  control, said reprogrammable means (14) being controlled by said received standard identification means (11) by means of said parameters contained in said memory means (13).  2. Time base according to claim 1, characterized in that said standard identification means (11) comprise means (20) for extracting the frame sync signal (SYTR) from the received video signal (SYH), means (21) counting the number of lines present in a frame, and means (22) for measuring the time duration of said frame.  Time base according to claim 2, characterized in that said standard identification means (11) comprise a transcoding table (23) providing data identifying said identified standard according to said number of lines present in a frame and the duration time of said frame.  4. Time base according to claim 3 characterized in that said means (11) for standard identification comprise means (24) for filtering noise affecting the received signal, said means (24) for filtering emitting a signal change of standard after confirmation of said change on several clock ticks (H).  5. Time base according to claim 4, characterized in that said filtering means (24) consist of:  - Means (40,41,42) apparent change detection standard;  - means (43,44,45,46,47,48,49) of stability confirmation on several  clock ticks (H) after apparent change of standard, and provide standard change information (XCHST) and value (STDP) of the new standard after each stability confirmation following an apparent change of standard, and in that said apparent standard change detection means (40,41,42) cooperates with means (26) for comparing the new standard (STDP) with the current standard (STDV) to validate the actual standard changes.  Time base according to claim 1, characterized in that said means (13) for storing time base parameters consist of a set of pages each containing the parameters corresponding to a separate standard, said means (13) of memorization being addressed on the one hand in MSB by a loading logic (12) for the selection of a page and on the other hand in LSB by said means (14) reprogrammable for reading and transferring all the parameters of said selected page.  7. Time base according to claim 6 characterized in that said loading logic (12) controls the loading of said parameters in said means (14) reprogrammable according to said identified standard.  8. Time base according to any one of claims 1,6 and 7 characterized in that said means (14) reprogrammable comprise counters (61,62,65,68) loaded by said parameters contained in said means (13) storage, said parameters corresponding to said identified standard.  9. Time base according to claim 8 characterized in that said counters (61,62,65,68) cooperate with latches (63,66,69) to generate said control signals.  10. Time base according to any one of claims 1 to 9 characterized in that it also comprises a module (10) for generating a pattern generating synchronization signals (SYTRMI, SYHMI) for displaying a target predetermined on the screen of said monitor.  Time base according to claim 10, characterized in that it comprises a synchronization signal selection mutiplexer (16) originating either from said target generation module (10) or from said standard identification means (11). , said selection being controlled by an external (SELMIIRE) target selection signal.  12. The time base as claimed in claim 1, wherein said means for storing parameters corresponding to said different standards also comprise parameters corresponding to said pattern.  13. Time base according to claim 12, characterized in that said parameters corresponding to said pattern are located from the address $ 0 of said memory means (13), so that when said base of said time, said parameters corresponding to said pattern are read by said means (14) for generating said control signals to display said pattern on said screen of said monitor.  14. Time base according to claim i1 characterized in that the target selection is generated when no standard is recognized by said means (11) standard analysis.  15. Time base according to any one of claims 1 to 14 characterized in that said module (10) for generating a pattern, said means (11) for standard analysis and said means (13) for storing said parameters are made from LCA (Logic Cell Array) circuits.