FR2653283A1 - APPARATUS FOR DETECTING ERRORS ON COMMUNICATION PATHS. - Google Patents

Abstract

An apparatus for detecting errors on a communication path is provided. To do this, the level of a digital input signal (INPUT) is sampled several times per bit, for example by a reversible counter (1) or a shift register with serial input and parallel output (20) and an adder (21). The number of samples per bit having the same value is compared in a comparator (2) to upper and lower limits and, if the number is between these limits, an error signal (FAULT) is produced. Application: in particular to aeronautics.

Description

The present invention relates to apparatus for detecting

  errors on communication paths. Such devices may be used between a digital communication path and a receiving apparatus to detect errors due to electromagnetic interference or different modes of disturbance due to

to short circuits.

  When digital signals are transmitted over a communication path such that a first level and a second voltage level respectively represent the binary digits "0" and "1", the voltage levels at the receiving end are detected. of the path and converted into an interface circuit, into the corresponding digital voltage levels used by the digital circuits of the receiving apparatus. Such an interface conversion is necessary even when the digital voltage levels of the receiving apparatus nominally correspond to those of the transmitter providing the digital signals to the communication path, because the transmission properties of the path and Spurious signals picked up by the path may degrade the signals beyond the tolerances of the receiving device. The interface circuit provides resistance, for example, to voltage spikes or transients induced in the conductors of the path and performs a voltage comparison to detect the binary digits.

signal from the path.

  However, certain forms of noise and certain types of abnormal states cause the signals in the communication path to be impaired to such an extent that known types of interface circuits make erratic voltage level detections. This then causes the receiving apparatus to receive degraded signals without realizing that an error has occurred. For example, in digital control systems used in aeronautics where digital signals are transmitted from one part of the aircraft to another along a communication path, a "hot short circuit" may occur. such that a conductor of the communication path is short-circuited on a supply voltage. This may cause the receiving device to receive incorrect data or incorrect command signals, with results

potentially very serious.

  According to the ivention, an apparatus for detecting an error on a communication path is provided, comprising sampling means for sampling an input signal at a plurality of sampling times during each bit period and for providing an output signal representing the level of the input signal at each of the sampling times, and an abnormality indicating means for providing an abnormality indication signal when the output signal of the sampling means represents a number of input signal samples of the same level, which number is between a first predetermined number and

a second predetermined number.

  Preferably, the sampling means are arranged to detect that each sampled value of the input signal is in a predetermined voltage range, for example in a voltage range greater than a predetermined value. In a case where the predetermined voltage range corresponds to a binary or logic level "1", the anomaly indicating means provide the anomaly indication signal when too many of the sampled levels are at the same level. "1" so that the received bit represents "0" reliably, but too few sampled levels are at "1" so that the received bit represents "1" reliably. However, by not requiring that all the sampled levels be at level "1" so that the received bit represents "1", or that all the sampled levels are "less than 1" so that the received bit represents "0", the The apparatus is immune to interference such as transient voltage variations or spikes and can be used to detect bits representing "0" and "1" with a high

degree of reliability.

  The apparatus itself can be used as an interface between a communication path and a receiving apparatus and can convert between the input signals from the path and the generated digital output signals depending on whether the output signal of sampling represents a number of input signal samples of the same level greater than or equal to the first predetermined number (for example representing "1") or less than or equal to the second predetermined number (for example representing "0"). When the apparatus includes means for generating digital output signals, the problem of the type of output signal to be provided when an error is detected may occur. To remedy this problem, the apparatus may include means for repeating an earlier digital signal when the abnormality indication signal is generated. Thus, a signal whose level can not be detected with confidence can be replaced by a previously correctly detected signal. Alternatively, separate means may be provided for transforming the input signals into digital output signals, and appropriate processing means arranged to receive the digital output signals and the anomaly indication signal may be used to exert

  the appropriate action when an error is detected.

  In one embodiment, the sampling means may comprise a reversible counter having a reversible control input for receiving the input signal, a clock input for receiving a clock signal whose frequency is greater than the bit rate. of the input signal, and means to prevent

  negative and positive overflow of the meter.

  In another embodiment, the sampling means may comprise a parallel output serial input shift register having a data input for receiving the input signal and a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and an adder for adding the outputs of the shift register. In both embodiments, the clock frequency may be nominally equal to a multiple of the bit rate, and the abnormality indicating means may include one or more digital comparators. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing, in which: FIG. 1 is a circuit diagram of an apparatus for detecting an error on a communication path; constituting a first embodiment of the invention, and FIG. 2 is a circuit diagram of an apparatus for detecting an error on a communication path, constituting a second embodiment of the invention.

the invention.

  The apparatuses shown in the accompanying drawing can be used to detect errors in signals received from any digital communication path in which the binary digits are received in series and are represented by standard logic voltage levels. One application of such circuits is the detection of short circuit occurring on communication paths, for example to fuel control systems in aircraft engines. Several such circuits can be provided as interface parts between several communication paths and subsequent circuits, such as information processing machines, and interfaces comprising several circuits of the type shown in the accompanying drawing can be provided. on, for example an integrated circuit

application-specific (ASIC).

  The apparatus shown in FIG. 1 comprises a three-bit reversible counter 1 having a two-way control input connected to receive an input signal INPUT (INPUT) of a communication path, so that when the INPUT signal has a logic high value, the counter 1 starts counting in ascending direction, while, when the INPUT signal has a low logic level, the counter 1 starts to count down. The counter 1 has a clock input connected to receive clock pulses CLK, and it also includes means for preventing a positive or negative overflow of the counter, i.e. means for preventing the content. of the counter to go below zero and rise above seven. In the embodiment shown in FIG. 1, the bit rate of digital signals received from the communication path is nominally 400 bits per second and the Clock frequency of CLK clock signals is 2.8 kHz. So, counter 1 actually samples

  the INPUT signal seven times during each bit period.

  The outputs QA, QB and QC of the counter 3 are connected to a digital comparator 2 which has a first output delivering an output signal when the content of the counter 1 exceeds five and a second output signal when the content of the counter 1 is less than two. The comparator 2 has a first output 3 and a second output 4 for the first output signal and the second output,

respectively.

  The first and second outputs 3 and 4 of the comparator 2 are connected to a first and a second complementary or inverting input of an AND gate 5 whose output is connected to a data input of a D-type flip-flop 6 The flip-flop 6 has an output Q intended to provide a fault indication signal FAULT when an error or anomaly is detected and a clock input connected to the output of an inverter 7 whose input

  receives clock pulses CLK.

  The apparatus shown in Fig. 1 further comprises means for providing a digital output signal OUTPUT representing the detected logic level of the input signal INPUT and for repeating an earlier output signal when an abnormality is detected. These means

  include two D-type and D-type flip-flops, a NAND gate

  AND at two inputs 10, a two-input OR gate 11 having complementary tap-in or inverting inputs, and an inverter 12. The clock inputs of the flip-flops 8 and 9 are connected to receive the clock pulses CLK and the clock pulses

  inverted from the inverter 7, respectively.

  The data input of the flip-flop 8 is connected to the Q output of the flip-flop 9 whose data input is connected to the output of the gate 11. A first inverting input of the gate 11 is connected to the output of the gate. inverter 12 whose input is connected to the first output 3 of the comparator 2. The second inverting input of the gate 11 is connected to the output of the gate 10 whose first input is connected to the output Q of the flip-flop 8 and whose second entry is connected to the exit of the

door 5.

  During normal operation, where correct bits of the input signal are received, a transient anomaly signal is generated whenever the input signal varies between the logic high and low levels. However, such transient anomaly signals can be rejected, for example by sampling the anomaly signal in synchronism with the incoming bits of the input signal or by integrating the anomaly signal of the input signal.

  to identify only persistent anomalies.

  In operation, the counter 1 samples the voltage level of each bit of the seven-point input signal. The comparator 2 determines whether the sampled values correspond to more than five logical high levels or less than two low logical levels. Thus, if the sampled bit of the input signal is logically high for six or seven of the samples, it is assumed that this indicates that the bit represents a logic high level or "1" in positive logic. Conversely, if the input bit is logic high for zero or sample, the input bit is detected as low logic, representing logical O in positive logic. In both cases, the gate 5 supplies a logic low level to the gate 10, which prevents the passage of signals from the flip-flop 8. In addition, the flip-flop 6 is set to zero, so that the anomaly signal is deleted. The flip-flop 9 is set at the logic level of the first output 3 of the comparator, and it is provided in

  as the output signal of the circuit.

  By arranging the comparator 2 to compare the number of samples at the logic high level at two and five, the circuit is immunized against certain errors, such as spikes or transient voltages of narrow voltage that can affect one of the seven samples of each bit . However, in the case of larger errors or anomalies of communication paths, such as hot shorts, the number of samples of the input signal at logic level 1 will be greater than or equal to two and less than or equal to five. In this case, the first output 3 and the second output 4 of the comparator 2 will be at the low logical level, so that the output of the gate 5 will be at the logic high level. The output of the flip-flop 6 will thus be 1, which indicates that an anomaly or error has been detected. In addition, the output of the gate 5 opens the door 10, which has the effect that the previous output level of the flip-flop 9, which was previously directed in the flip-flop 8, is returned to the flip-flop 9. Thus, each Once a fault condition is detected, the digital output of the circuit is maintained at the

  detected value without previous anomaly.

  The embodiment shown in Figure 2 differs from that shown in Figure 1 in that the counter 1 is replaced by a shift register 20 and an adder 21. The other components shown in Figure 2 are designated by the same numerical references as those used in Figure 1 for

  corresponding elements and they will not be described further.

  The shift register 20 is of the serial input parallel output type and includes a data input which receives the input signal INPUT and a clock input which receives the clock pulses CLK. The shift register has seven stages whose outputs QA to QC are connected

  at respective inputs of an adder 21.

  The adder 21 comprises a three-bit parallel output which represents in binary form the sum of the high logic level signals provided by the outputs of the shift register 20. Thus, the three-bit binary output of the adder 21 represents the number of samples at the logic high level in the sampled bit of the input signal. The rest of the operation of the circuit shown in FIG. 2 is the same as that shown in FIG.

  Figure 1, and it will not be described further.

Claims (7)

  An apparatus for detecting an error on a communication path, characterized by sampling means (1, 20, 21) for sampling an input signal at a plurality of sampling times during each bit period of time. input signal and to provide an output representing the level of the input signal at each of the sampling times, and an abnormality indication means (2, 5, 6) for providing an indication signal of anomaly when the output signal of the sampling means represents a number of input signal samples of the same level, which number is between a first predetermined number and a second predetermined number.   Apparatus according to claim 1, characterized in that the sampling means (1, 21) are arranged to detect that each sampled value of the input signal is included in a   predetermined voltage range.   Apparatus according to claim 2, characterized in that the sampling means (1, 20, 21) are arranged to detect that each sampled value of the input signal is greater than one predetermined value.   4. Apparatus according to any one of   preceding claims, characterized by means (5,   8-12) for providing an output signal having a first value when the number of input signal samples of the same value is smaller than the first predetermined number and a second value when the number of input signal samples of the same value is greater than the second predetermined number, the second predetermined number being greater than the first predetermined number. An apparatus according to claim 4, characterized by means (8-11) for repeating an earlier output signal when the abnormality indication signal is generated. 6. Apparatus according to any one of   preceding claims, characterized in that the   sampling means comprise a reversible counter (1) having an up and down counting control input for receiving the input signal, a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and means for preventing overflow negative or positive counter.   7. Apparatus according to any one of   Claims 1 to 5, characterized in that the means   method comprises a serial input and parallel output shift register (20) having a data input for receiving the input signal and a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and an adder (21) to add the   outputs of the shift register (20).