FR2633470A1 - METHOD FOR DEMODULATING AND DEMODULATING DIGITAL CONSTANT ENVELOPE AMPLITUDE SIGNALS IN CONTINUOUS PHASE AND / OR FREQUENCY MODULES - Google Patents

Abstract

The invention applies to the demodulation of digital signals composed of series of symbols of duration T transmitted by means of phase and / or frequency jumps. The method consists in sampling 1, the phase of the modulated signal detected, within each symbol duration T by means of a comb of sampling pulses obtained from N clock pulses regularly spaced by an interval time equal to T / N; calculating the d intersymbol differential phase angle for each phase sample of the detected current symbol; in coding 4 each differential phase angle d by assigning a coding cost to it; in calculating 4 the sums of the coding costs for the samples of the same symbol rank belonging to a determined number L of consecutive symbols; in memorizing 4, among the N sums obtained the one which gives the greatest result; to take 4 as symbol synchronization clock, the clock which in the pulse comb has the same rank as the rank of the samples which led to the greatest sum and to decode 5 the differential phase angle which has the same rank as the stored sample. Application: digital transmission of radio signals.

Description

Demodulation method and demodulator of digital amplitude signals

modulated constant envelope

  in phase and / or in frequency continuously.

  The present invention relates to a demodulation method

  digital amplitude demodulator and demodulator

  constant veloppe modulated in phase and / or in frequency continuously. It relates in particular to the demodulation methods of radio signals carrying digital information,

  and their uses in transmission systems of the in-

  packet formation or frequency evasion.

  In these methods, the data to be transmitted are conver-

  in the form of constant-duration symbol sequences forming the baud interval of the transmission for continuously modulating frequency or phase a carrier wave of constant envelope amplitude. Their interest lies mainly in the fact that they lead to lower frequency occupations than those of the transmission systems known by the abbreviations FSK or PSK of the Anglo-Saxon designations "Frequency Shift Keying" and "Phase Shift".

  Keying "that use rectangular shaped symbols.

  An example of a system implementing a continuous phase-modulated carrier modulation method and a constant envelope amplitude is known from the application of FIG.

French Patent No. 82,08043.

  According to the modulation system described, the modulator

  includes an encoder that matches the data

  or symbols to transmit discrete values of phase hops and a symbol synthesizer that elaborates according to the information provided by the encoder a form of continuous phase variation with minimal slope, expressed as a function of time by a polynomial law. The receive demodulator uses synchronous demodulation and proceeds by correlation to recover the characteristic times of modulation and frequency drift between the transmit and receive carriers. This system has the advantage of occupying a low frequency bandwidth with respect to the bit rate of the information it transmits and allowing, for example, transmissions of data at 16 K bits / s in wide channels of 25 KHz with

  an attenuation outside the channel of 50 dB.

  However, the demodulator is complicated to achieve

  when the data transmission systems have to transmit

  be data packet or frequency evasion of the fact

  in particular the complexity of the system for estimating the hor-

  symbol box that is used. Since this one has a func-

  specificity to estimate the DC component and a function

  to estimate the symbol clock conditioned by the estimation of the DC component, the noise effects

  transmission and frequency drift of the os-

  pilot pilot of reception relative to that of the oscilla-

  issuers are not dissociated. As a result, the performance of the synchronization circuit is degrading

  as the transmission is tainted by noise.

  The object of the invention is to overcome the above-mentioned disadvantages.

  For this purpose, the subject of the invention is a demolition process

  digital signal modulation of constant envelope amplitude and modulated in phase and / or in frequency continuously, the digital signals being composed of sequences of symbols of the same duration T and juxtaposed with each other in time, the symbols being transmitted by means of phase and / or frequency jumps, characterized in that it consists in: detecting the phase of the modulated signal in the form of a variable amplitude signal as a function of the phase variations of the modulating signal; - to sample, according to a sampling period equal to T / N. the phase of the modulated signal detected, within each symbol duration T by means of a sampling pulse comb obtained from N clock pulses evenly spaced by a time interval equal to T / N ;

  - to calise the differential phase angle d0 sepa-

  ranting each phase sample of a detected current symbol, of the sample of the same rank located in the detected symbol at the preceding symbol time; - Coding each differential phase angle dO by assigning a coding cost dependent on its amplitude; to calculate the sums of the coding costs for the samples of the same rank belonging to a determined number L of consecutive symbols; identifying, among the N sums obtained, the one that gives the largest result by memorizing the rank occupied in each symbol by the corresponding samples, to be taken as a symbol synchronization clock, to define the synchronization instants of the demodulator, the clock which in the pulse comb has the same rank as the rank of the stored sample;

  - and to decode the differential phase angle that pos-

  ranks the same as the stored sample.

  It also has a purpose, a demodulator for setting

of the aforementioned method.

  The invention has the advantage that it allows for

  the symbol clock compatible with the length of the

  characteristic stages of transmission in frequency evasion.

  accordingly. This result is obtained thanks to the relatively

  simple used to retrieve the symbol clock.

  This simplicity results from the fact that the estimation of the symbol clock is carried out according to one and the same concept whatever the cause of the fluctuation of the rhythm, which can

  be due either to a constant delay between transmission and reception

  tion or drift in frequency of reference frequencies.

  these posts, either to a frequency drift due to the effect

  Doppler, that is to say to the Gaussian noise

each transmission.

  On the other hand, the performance compared to previous systems should normally be improved because true phase and non-frequency filtering is done by the proposed system and a finer correlation is obtained for

the search for synchronization.

  Other features and advantages of the invention

  will appear below with the help of the description made opposite

  attached drawings which represent: Figure 1 a curve to recall the principle of continuous phase modulation;

  Figure 2 the principle of sampling implemented

  by the invention for obtaining differential phase samples; FIG. 3 a known representation of a diagram of the eye corresponding to a continuous phase modulation with 5 states; Figures 4 to 6 an illustration of the cost functions used as synchronization criterion; Figure 7 an embodiment of a demodulator according to the invention; Figure 8 an embodiment of the differential phase calculation block of Figure 7;

  FIG. 9 an embodiment of the memory block

  the differential phase of FIG. 7; FIG. 10 an embodiment of the calculation block of the synchronization clock of FIG. 7; Figure 11 a three-dimensional graph of distribution of the cost function taking into account the frequency drift of the carrier; Figure 12 a top view of the graph of Figure 11; Figure 13 an embodiment of the demodulator of

  the invention provided with a drift correction device.

  The curve of FIG. 1 traces the phase variation law 0 (t) of a constant envelope signal obtained according to the known principle of phase-phase modulation. Sure

  this curve the points marked O, +11/2, -Â1, -11/2 etc ... represent

  sense states taken by the phase 0 (t) of the signal to transmit the different symbols Sn which characterize a transmission, each symbol being represented by a state of

phase determined.

  As described in the aforementioned French patent, 11 is given the same phase value and the same slope at the origin of each symbol S and at the end of the symbol Sn 1 which n n-i

  it precedes it, on the other hand, the maximum slope of the curve

  phase (t) is minimal between successive phase states so as to minimize the width of the

  frequency spectrum occupied. By adapting a poly-

  third degree, the phase variation between each Sn and Sn-1 symbol is very slow, and the width of the frequency spectrum occupied by the modulation is less than that occupied by the FSK or MSK type modulations cited above.

previously.

  According to the invention, phase 0t) of the signal is

  in the manner shown in Figure 2 by a sampling comb of which each tooth represents a clock of

synchronization possible.

  The differential phase dO (tnk) measured between two successive samples is equal to dO (tnk) 0 (tn, k) - 0 (tn, kT) (1) with tnk = nT * kte with te = T / N o: N is the total number of synchronization clocks

  - t is the sampling period of the differential phase

tielle - T is the symbol period

  and k is an integer from 0 to N-1.

  To reliably decode the symbols, the symbol clock is accurately estimated taking into account the

  fact that the decision instant chosen for the decoding is

  periodically spaced in time from a symbol period and that it does not

  does not necessarily coincide with the moment of synchronization.

  The synchronization instant t corresponds to the location

  o Figure 3 o The timing information is the most dense. This moment is defined by a

  number of different phase sample values

  tielle a = d0 (to) for which the minimum difference taken in absolute value between two samples is the most

  large possible so that the noise immunity sclt the greatest.

  However, as the exact values of ai are not

  never reached because of noise and technological imperfections

  The synchronization instant can only be evaluated by estimating the distance between the values of the samples

  the exact values of the samples ai corresponding to

  actually tooth at the moment of synchronization. This distance measures the probability of actually finding the instant of synchronization and is defined, in this - following, using a cost function of which an example of a graphical representation is shown in FIG. amplitude A maximums when the sample has differential phase

  dM measured corresponds exactly to the synchronization instants

  tion and zero values for the different phase samplings

  dd located in the middle of the intervals between

  the exact moments of synchronization successL's. On the representatives

  FIGS. 4 and 5 show the variations of the cost function between each point of the zero amplitude curve and the two

  points directly adjacent to maximal amplitudes A are linearly

  res, the corresponding straight lines having opposite slopes.

  However, according to other variants of embodiments of the invention,

  tion, the linear variation mode may be replaced by

polygonal variation modes.

  The maximum amplitude A of the cost is fixed by the width

  a statistical window counted as a number of symbols and possibly

  Limitations Imposed by the specifications

  (length of an EVF bearing for example).

  For the samples a and aimax correspon-

  At the extreme symbols of the window, the symmetry of the cost function is that shown in FIG. 5. A variant taking into account a non-equiprobablity of the samples ai is shown in FIG. 6. According to this variant, each cost function relating to a sample ai of a symbol Si has a maximum amplitude Ai of its own. This amplitude A1 is defined by the relation A1 = A x P1 / P o A denotes the maximum possible amplitude and

  P1 is the probability of obtaining the instant of synchronization

  tion t coincides with the sampling time of the o

differential phase d0.

  The estimation of the clock takes place by choosing the one which is closest to the position in time of the sequence of the samples of order ai of each symbol whose total costs accumulated on L consecutive symbols and measured with the aid of the cost function described above is maximum. This statistical estimation is carried out in the case of a mode of packet transmission or frequency evasion, on the number L of the symbols of a packet or a stage in escape from

  frequency. For each symbol symbol clock k of a set

  N clocks correspond to a statistical estimate described by a relation of the form: S (k) = C (d0 (tno k)) C (d0 (tno + 1, k) + ... + C (d0 (tnoL, k )) If ke is the estimated synchronization clock, this one is determined by the sum Sk which presents the

largest result.

  Following this estimation two actions are carried out

  The first action is to correct the clock of the demo-

  dulator to allow the registration of this one on the moment

k clock previously estimated.

  The second action is to decide on the decoding.

  The correction action of the demodulation clock is

  performed via an internal sequencing of the demodulator and

  cute in the sense that returns to the symbol clock taken as a reference, at the initial time, this instant can be chosen as the middle of the time range covered in a symbol by all the clocks of the comb. Since the decision clock of the decoding is not necessarily confused with the synchronization clock but may have a constant difference with the synchronization clock, the decision time of the decoding must also be determined by a translation in the same

  meaning that that carried out for the moment of synchronization.

  An exemplary embodiment of a demodulator according to the invention

  FIG. 7. It comprises a block 1 for calculating the differential phase d 0, driven by a pilot clock 2, and coupled to a storage block 3, to a calculation block of the synchronization clock 4 and to a decoder 5. The calculation block of the synchronization clock 4 is coupled

  on the other hand, at the storage block 3 and at a sequence block

and enslavement 6.

  The calculation block of the differential phase 1 is

  detailed in Figure 8. It includes an implementation stage.

  form 7, connected to a shift register 8. The shift register

  lage 8 is coupled to a phase locked loop

  by a buffer register 9, a state comparator 10 and a divider

  11. The status comparator 10 is connected to a shift register 13 through a phase down counter 12. The phase counter 12 is connected to a first operand input of a subtractor circuit 14. The second operand input of the subtractor circuit 14 is connected

to this shift register 13.

  The differential phase calculation block 1 constitutes the functional input of the demodulator. His role is to put

  in a binary form exploitable by the demodulator, the

  baseband IF radio station Derived from transposi-

  Conventional frequency transmission not shown, obtained in known manner at the output of the intermediate frequency stages of a receiver. This function is provided in known manner by the shaping stage 7 by means, for example, of a voltage comparator circuit, not shown, able to work at frequencies and voltages compatible with the input signal. . In this respect, two types of formatting may possibly be performed. A first formatting can consist in comparing the input signal with the average value of the latter and in this case, the comparator must be provided with a hysteresis system to avoid instabilities in the case where the signal of Entrance

  is weak. A second formatting can consist of comparing

  Differentially input the IF input signal. The advantage

  the latter type of comparison is that it allows a transcription

  point where the level of the input signal is

  nule. The second function provided by the calculation block 1 is the calculation of the differential phase d0 itself. The first operation that is performed is to create a digital signal from the master clock, able to be compared

  in phase with the input signal. This is ensured in a way that

  naked by a phase locked loop. This loop is

  composes in figure 8 elements 8 to 11.

  The register 8 contains the samples of the signal of

  and its contents are renewed with precision and periodi-

  quoted equal to those of the programmable divider 11.

  The buffer register 9 makes it possible to stabilize two samples.

  of the signal taken successively and this at the frequency of

the local clock.

  The comparator 10 provides a comparison between the quantities of the samples contained in the register 9. It provides in this way on its output, two information qualifying

  phase growth or decay of the input signal.

  Its time evolution has a precision which is fixed by the ratio of the pilot clock and the input signal. For example, the sampling step is 10, if the report is the

  1 / 36th of the period of the input signal.

  The two phase advance information (+10 in the example) and the phase delay (-10 in the example) provided by the state comparator 10 are applied to the input of the

circuit 11.

  The up-down counter 12 performs the accounting of the advances and phase delays provided by the comparator

  10. A phase advance increases the

  naked counter 12 and a delay decreases its content by one unit. The output of up-down counter 12 can provide under these conditions the absolute phase 0 (t) of the input signal from any moment of use to the zero value of the content.

of the down-counter 12.

  The shift register 13 has a stack register structure, also known under the Anglo-Saxon designation FIFO which is the abbreviation for "First in firs out", and forms with the subtractor circuit 14, the differential phase calculation element. well said. The subtractor circuit 14 receives in addition the successive phase samples 0 (t).

  from the up / down counter 12 and receives

  the successive phase samples O (tT) originating from the shift register 13 whose fixed number of offsets is equal to the ratio of the sampling frequency of the modulating signal (He) to the frequency of the modulating signal itself (H symbol ). The phase difference d0 (t) obtained at the output of the subtractor circuit 14 satisfies the relation d0 (t) = 0 (t) -0 (t-T)

  where t is the present moment and T is the period of the modu-

  this period being the same as the symbol period described above. The differential phase samples d0 (t) are transmitted to the input of the storage block 3. This block, which is represented in FIG. 9, comprises random access random access memory 15 addressed by an address selector 16 and by the output of a subtractor circuit 17. The memory 15 allows the recording and the reading of the samples of the phase

  Differential d0 () obtained from the calculation block 1. The selection

  There are two inputs to the number of transmitters. One input receives the number of the decoding clock, the other is connected to the output

  of a sample counter 18. The subtractor circuit 17 com-

  carries two operand inputs. A first operand entry

  marked (+) is connected to the output of a symbol counter 19.

  The second operand entry marked (-) receives in the form of a binary word the number of symbols L on which the statistical calculations described above relate. The symbol counter 19 progresses at the rate of pulses provided by a divider circuit 20, this circuit 20 dividing by

  the number N of samples contained in a symbol of the frequency

sampling frequency Fe.

  In order to retrieve the information, in particular the rhythm and the characters of the modulation, it is necessary that the modulating signal received and the differential phase d0 (t) calculated,

  undergo constant oversampling. This exchange

  sampling is chosen N times higher than the symbol frequency and the difference between samples is 360 / N degrees of the phase

of the modulating signal.

  For this purpose, the calculation block of the synchronization clock

  sation 4 operates by sliding treatment on the consecutive symbols

  corresponding to the length of the statistical processing.

  To satisfy these conditions, the memory 15 is organized

  It is used to store N x L samples of the differential phase and its operation is similar to that of a shift register. Its structure is preferably that of a memory

  random access to allow flexible operation

  Frequency or information transmission mode

in packages.

  The addressing of the memory 15 is carried out using the

circuits 16 to 20.

  The selector 16 switches between two distinct modes of operation in writing or reading the

memory 15.

  The write operation mode allows recording

  in the memory 15 of differential phase samples

d0t from calculation block 1.

  Addressing is defined to allow each last

  sample d0 (t) arriving at a moment to, of taking

  instead of the one that was recorded at time t = t0-LT ie L symbols instead. The location of the o

  concerned memory box is provided by the contents of the

  In the read operation mode, the sample of the differential phase d0 '(t) occupying the place of the next to come is directed to the calculation block of

  synchronization clock 6. However, the mode of operation

  Reading is also used to convey the sample.

  a differential phase of time d0 (t) to the decoder 5 whose (t) clock number has been recognized having the highest probability of being the corresponding one. to the synchronization clock. The combined operation of the selector 16 and the subtractor 17 makes it possible to operate the memory in the addressing mode.

  packets, the selector 10 being controlled to select the hor-

  decoding box, the noted input (-) of the selector 11 receiving a binary number between zero and L.

  The calculation block of the synchronization clock represents

  shown in Figure 10 consists of 4 parts.

  The first part comprises an encoding device 21 formed by a programmable read only memory or any device

  equivalent for coding the different phase samples.

  -competitive. Coding is done by applying the function coit

  previously described for each phase sample of

  The memory of the decoding device 21 is addressed on the one hand by the incoming phase sample d 0 (t) and by the sample already stored in the memory 15.

at time t = to-LT.

  The second part includes an adder circuit 22 and

a RAM 23.

  The memory 23 has a role of accumulator for the circuit

  adder 22. It comprises a stack of N accumulated registers

  organized in the FIFO mode. The adder circuit 22 adds to each data read out by the last register of the

  stack the transforms (C.d0 (t) and Cd0 '(t)) by the functions

  described previously, phase samples

  differential d0 (t) and d0 '(t). Each result of the ad-

  The output calculated by the adder circuit 22 is stored in the first register of the stack, the contents of each accumulator register of the memory 23 being successively pushed into the following registers of the stack at each new result supplied by the adder circuit 22, additions and offsets

  taking place at the sampling frequency N / T.

  In this way, at the sum of the last L costs, obtained for each series of samples spaced from N, the cost C.d0 '(t) coming out of the memory 15 is subtracted and the cost (t) added.

  entering C.d0 (t) in the memory 15.

  The third part of the calculation block of the synchronization clock comprises a buffer memory 24, a comparator circuit of superiority 25 and a buffer register 26. Its function is to locate in the N sums costs, which are constantly updated. in the memory 23 by the adder circuit 22, that which gives a maximum amplitude, this marking occurring in real time with the bit rate of the modulation, that is to say at the symbol frequency 1 / T. Each maximum cost sum is stored in the memory 24, where it

  remain until a new sum is found for the replacement.

  to place. This memorization is determined by the comparison circuit.

  superiority 25 which compares at any moment the content of

  the buffer memory 24 with each of the sums of the costs

  by the adder circuit 22. The comparator circuit

  superiority also provides a control signal to the regis-

  buffer 26 to memorize each new sample number.

  which gives rise to a new maximum of the cost function.

  All N samples, the memory 24 has in memory the sum of the highest costs and the buffer register 26 has the number of the clock associated with this sum. The number of the clock is then transferred to a buffer register 27 connected to the

  buffer register 26 and the previous process is repeated.

  The fourth part of the calculation block of the synchronization clock comprises a control logic 28 which acts

  according to the clock number stored in the tamper register.

pon 27.

  Depending on the type of modulation used, the control logic supplies the decoder 5 with the n0 of the decoding clock.

  found in the buffer register 27 and information to compare

  order the sequencing and servo block 6 of the

  freezer. The decoding of the differential phase is carried out by

  decoder 5, this one decodes the different phase sample.

  tielle whose clock number is the one retained by the cost function

  To enable the demodulator to operate with several different types of modulation a programmed memory

  specific to each modulation may be included in the deco-

  5 and following this memory, several types of cir-

  out cooking could be considered, to adapt the function

the demodulator to the different types of transmission

sions.

  The demodulation process and the demodulator which comes

  to be described have acceptable performance if the

  Frequency bank of the carrier remains low. The frequency drift on the radio carrier is related to the difference in frequency between the pilot clocks of the transmitting and receiving stations. This drift can be, for example, + 1 kHz for a carrier frequency of 100 MHz with a pound clock frequency of 5 NlHz to +10. To this must be added or subtracted the drift specific to the Doppler effect which is estimated for terrestrial vehicles at +10 7 times the frequency of the radio carrier, which corresponds in the preceding example to a drift of +10 Hz. For airplane-ground or aircraft connections the value of the drift due to the Doppler effect is larger and can reach +2 10-6 times the frequency of the radio carrier, which in the previous example gives 200 Hz of drift. This drift effect results in a positive or negative slip of the differential phase. For example, with 1o a symbol frequency F symbol of 25 KHz and a drift A f estimated at + 1KHz we obtain / Af / F symbol = + 0.04, that is to say a slip of 15 of the differential phase. As a result, the presence of drifts causes an offset of the symbolic characters specific to the phase modulation used. For important drifts, the method and the demodulator described above must be

  adapted to take account of these drifts and the fact that

  The drift and the sampling clock must be performed in very short times, less than the duration of the frequency evasion transmission systems containing the useful data. This problem can be solved by

  performing a simultaneous estimation of the sample clock-

  reception and drift of the carrier. In fact, the drift on the carrier can be estimated by means of the decentering that is observed on the differential phase. As a result

  drift can be estimated in degrees per symbol period.

  Instead of using a cost function parameterized by the reception sampling time, the implemented method uses a cost function parameterized by a vector whose two components are the sampling clock and the drift. It is possible to represent this cost function, the sampling clock parameter being fixed, since this function is invariant by translation of this parameter. This

  function can be represented in a three-dimensional space

  sions, a foreground being formed by the axis of the drifts on the

  carrier and the axis of the differential phase, the axis of the

  representing the cost being perpendicular to this plane. The same cost function described above with respect to FIGS. 4 to 6 can then be used. This function serves as a reference

  calculations because it corresponds to the case where the drift on the por-

  is null. The reference function can be considered as the projection of a general cost function on the equation plane: drift = O. The projected of the general cost function on the equation planes drift = Cte are obtained by translation of the phase parameter differential of the amount given by the drift.

  A representation of the projections is shown in FIGS.

res 11 and 12.

  The estimated parameter is the parameter that maxirruse the

static thus obtained.

  With the previous notations and the addition of a para-

  meter derives from, the statistical estimate (2) becomes S (kde) = C (d (tno of) + C (d0 (tno dk) e) e tno, k) e (tn no & l, k), e + c (Â ") (3) + '.. + C (d {(tno * L, k) de) To compensate for the effect of this drift and to estimate its value in degrees per symbol, the calculation block of the synchronization clock is modified in the manner shown in FIG.

  13, where the elements that are similar to those of FIG.

  with the same references, by the addition of a drift counter 29, and the introduction of cost coding tables in the coding device 21 addressed by the counter 29 to

  take into account the drift parameter. The calculation block represents

  FIG. 13 performs for each discrete value of the presumed frequency drift the sum of the last L costs.

  indexed by the same number of the sampling clock.

  This calculation is carried out by the adder 22 and the

  moire 23 in a similar way to that performed by the block of cal-

  Figure 10 except for the number of partial sums to be compared which is equal to N times the

  number nd discrete values of drift taken into account.

  For this purpose the memory 23 must contain as many stacks of registers

  There are many nd values of discreet drifts.

  The buffer memory 24 stores as before the sum of the maximum value costs, the latter being indexed at the same time with the number of the sampling clock and the value

presumed drift.

  In the diagram of FIG. 13, the presumed value of the drift is transmitted by the drift counter 29 inside the buffer register 26. The buffer register 26 possesses

  at the end of the reference symbol period the presumptive value

  of the drift and the number of the clock which gave the sum of the L last costs the strongest, that is to say one among the

  Nnd are. These values are transmitted cormmre on the fi

  10 to the buffer register 27. To enable the decoding of the symbols, the decoder 5 of FIG. 7 must receive the assigned differential phase elements of the correct offset clock number provided by the control logic 28 and the value of FIG. the frequency drift also contained in the buffer register 27 and supplied by the control logic 28. The value of the frequency drift is applied to an input of the decoder 5 to allow it to perform a translation of

  the differential phase of the symbols to be decoded.

Claims (9)

  1. Method for demodulating digital amplifier signals   constant envelope study and modulated in phase and / or frequency   continuously, digital signals being   by sequences of symbols of the same duration T and juxtaposed with each other in time, the symbols being transmitted by means of phase jumps and / or frequency, characterized in that it consists: - to detect (1) the phase of the modulated signal in the form of a variable amplitude signal as a function of the phase variations of the modulating signal;   - to sample (7), according to a sampling period-   equal to T / N, the phase of the modulated signal detected, at the inte-   each T symbol period by means of a pulse comb.   sampling samples obtained from N clock pulses   regularly spaced a time interval equal to T / N - to calculate (1; 8-14) the differential phase angle d0 separating each phase sample from a detected current symbol, of the sample of the same rank located in the detected symbol at the previous symbol time; - to code (21) each differential phase angle d0 by assigning it a coding cost depending on its amplitude; calculating (22, 23) the sums of the coding costs for the samples of the same rank belonging to a determined number L of consecutive symbols; - to identify (24, 25), among the N s obtained obtained the one that gives the largest result by memorizing the rank occupied in each symbol by the corresponding samples;   to take (26) as a symbol synchronization clock   the, to define the synchronization instants of the demodula-   the clock which in the pulse comb has the same rank as the rank of the stored sample; - and to decode (5) the differential phase angle which   has the same rank as the stored sample.   2. Method according to claim 1, characterized in that the coding cost to a maximum value when the angle of   Calculated differential phase corresponds to the instants of synchro-   the demodulator and a null value in the middle of the ln-   interval between the consecutive synchronization instants. 3. Method according to claim 2, characterized in that the law of variation of the coding cost between a zero value   and a maximum value is linear.   4. Method according to claim 2, characterized in that the law of variation of the coding cost between a zero value   and a maximum value is represented by a polygo-   niale. 5. Demodulator for implementing the method according to   any of claims 1 to 4, characterized in that   it comprises: a shaping stage (7) for detecting the phase of the modulated signal in the form of a variable amplitude signal as a function of the phase variations of the modulating signal and sampling the variable amplitude signal obtained according to the sampling period T / N, a calculation block (1) of the differential phase angle d0 separating each phase sample from a detected current symbol of the sample of the same rank located in the detected symbol at the symbol time previous, a storage block (3, 15) for storing for a period of L symbols each differential phase sample d0, an encoding device (2) 1 for encoding each differential phase angle provided by the calculation block, and angle of   differential phase of the same rank stored in the memory block   (3, 15) calculated L symbols rather, attributing them   a coding cost depending on their amplitude, an additional circuit   accumulator (22, 23) to subtract from one another the costs calculated by the coding device and separated in time from the duration of L symbols, and to add to the result of the   subtraction for the duration of L symbols, the costs of   obtained for samples of the same rank within   each symbol, a comparison circuit (24, 25) for identifying   proud, among the N s obtained obtained the one that gives the largest result, a buffer register (27) to memorize the rank occupied in each symbol by the sample which contributed to obtaining the largest result, a logic of order   (28) to select the synchronization clock whose pulse   in the line comb has the same rank as the rank of the stored sample and a decoder (5) to decode the angle   differential phase which has the same rank as the sample   Ion stored in the buffer register (27).   6. Demodulator according to claim 5, characterized in that the coding circuit (21) comprises a read-only memory.   programmable to memorize in table form the differences   the costs to be attributed to each differential phase angle calculated by the calculation block.   7. Demodulator according to claim 6, characterized in that it comprises a drift counter (29) for estimating the drift of the frequency of the carrier wave, to address the   cost tables according to the estimated drift.   8. Demodulator according to claim 6, characterized in   the drift counter (29) transmits the value of the   estimated bank to the decoder (5) through the buffer register (27)   and control logic (28) for performing a transla-   equal to the drift value of the differential phase symbols to decode.   9. The demodulator according to claims 8 and 9, characterized   ris en ris en en en en en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en sommes en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en   discrete number of drift provided by the drift counter (29).