FR2587861A1 - Allocator for distributed bus with asynchronous data sources - Google Patents

Abstract

The invention relates to an allocation device 1 for allotting consecutive allocation periods within a bus 3 distributed to several asynchronous data sources having different bit rates and being identified by tags Ei, so that an active source having requested authorization to transmit can transmit a data packet in a bus during an allocation datum. According to the invention, the tag Ei of an active source is stored in just one cell 70k of a tag memory 7 whatever the bit rate of the source. The reading of the tag is performed substantially at the frequency, reproduced in a tag frequency allocation circuit, of the packets to be transmitted, and is decided in particular as a function of active source priorities so as automatically to manage simultaneous allocation requests coming into conflict in respect of a same allocation period.

Description

Allocator for bus distributes a
asynchronous data sources
The present invention relates to an allocation device for allocating consecutive allocation periods in a distributed bus to several asynchronous data sources, each of the allocation periods being adapted to be occupied by a word, said tag, identifying one of active sources having requested permission to transmit data packets in a bus to a packet concentrator associated with the allocation device.

More particularly, the invention relates to an allocator for an asynchronous digital time division multiplexing system with distributed bus, of the type described in the French patent application.
FR-A-2,553,609.

 This allocator constitutes tag frames identifying active sources that have requested packet transmission authorization using frame memory. Each frame is composed of N consecutive time intervals, called allocation periods, each having a predetermined duration e likely to be occupied by a source tag. The frame memory therefore contains N label cells read cyclically at the frame period.

A first disadvantage of the frame memory is its large capacity. In fact, the number N of cells of the memory is equal to the ratio dM / dm, where dM and d respectively denote
m maximum and minimum flow rates of the sources. In other words, a request for transmission of packets by a source at the maximum bit rate requires a writing of the tag of this source in the N cells of the memory.

A second disadvantage of the frame memory is the difficulty of its management by a central processor receiving requests for transmission of the sources. To allocate a flow channel di to an Ei label source, it is necessary to
1) that the frame memory has at least no free cells, where ni is equal to di / dm when the ratio di / dm is an integer, and is equal to ni = 1 + integer part of (di / dm ) when the ratio di / dm is not an integer, and
2) that the cells storing the label Ei are as evenly distributed as possible in the memory in order to minimize the capacity of a queue in a packet-multiplexer serving as means for accessing the packet transmission bus by the source .

 This last constraint is extremely severe and constitutes a major handicap for this type of allocator. Indeed, failures and successive installations of various bit rate communications do not necessarily create free cells in the memory corresponding to the most appropriate allocation periods in the frame to control a regular packet transmission in source multiplexer packers. . A lack of equidistribution of allocation periods allocated to each active source thus offers a risk of queue overflow all the more critical that the flow rate of the source concerned is high.

 The present invention aims a dual purpose consisting on the one hand to remove the frame memory to replace it with a tag memory having a very low capacity independent of the values of the flow rates of the sources, and on the other hand, to delete the management the time distribution of the transmissions of labels in the bus distributed by the central processor by replacing it with a selective reading of the tag memory as a function of the bit rates of the active sources. In addition, the invention allows good continuity in the choice of multiplexed rates and an increase in the range of multiplexed source rates.

 According to the invention, a device for allocating consecutive allocation periods in a distributed bus to several asynchronous data sources, said sources having different data rates and being identified by respective tags, each of said allocation periods being able to to be occupied by at most one label of one of active sources having requested a data transmission authorization, said device comprising control means receiving transmission authorization requests accompanied by data rates of the active sources, a memory having cells for each memorizing a tag, means controlled by the control means for writing tags in the memory in response to transmission authorization requests, and means for reading stored tags for transmission in the bus during transmission; periods of allowance, is characterized in that the control means allocate priority words to said active sources and the means for writing write the label of each active source only in a single free cell of the memory regardless of the bit rate of the active source, and that the device comprises means for establishing periodic allocation requests respectively at tag frequencies substantially proportional to the rates of the active sources in a predetermined ratio, and means for selecting an allocation request of a priority source among those of sources active elements not yet satisfied at each allocation period, according to the priority words, so that the means for reading read out the memory cell containing the label of the selected priority source for transmission on the bus during said period allocation request, said allocation request satisfied with the priority source being erased to the state the next allocation request from the selected priority source.

 The notion of label frame according to the prior art mentioned above is eliminated according to the invention since in the memory, the tag of an active source is stored in only one memory cell and is read substantially at the frequency of the packets to be transmitted by the source through the means to establish.

 According to one characteristic of the invention, the means for establishing comprise several programmable frequency means respectively associated with the cells of the memory, each programmable frequency means being programmed by the control means as a function of the flow rate of the active source whose label is contained in the associated memory cell to provide allocation requests at the tag frequency of said source.

 Thanks to programmable frequency means, analogous to frequency synthesizers, the choice of tag frequencies and thus multiplexed source rates is carried out with great precision, including at high data rates. Such synthesizers produce a very wide range of tag frequencies and thus allow a very wide range of source rates.

 According to another characteristic of the invention, the means for selecting comprise means for maintaining each of the allocation requests as long as it is not satisfied, means for reading priority words associated with said unsatisfied allocation requests. , means for comparing priority words read between them in order to deduce among them the priority word assigned to a priority source and to satisfy the allocation request of the priority source by controlling through the means to read a reading of the memory cell containing the label of the priority source. The means for selecting thus have the role of automatically managing simultaneous conflicting allocation requests for an allocation period. However, preferably, priority is given to sources having high data rates, which avoids overflows in the queues. expectation corresponding to these high-flow sources.

Other advantages and features of the invention will appear more clearly on reading the following description of preferred embodiments of the invention with reference to the corresponding appended drawings in which:
FIG. 1 is a schematic block diagram showing the general organization of a distributed bus asynchronous digital time division multiplexing system already presented in FIG.
FR-A-2,553,609;
- Fig.2 is a timing diagram showing a distribution of tags in an allocation bus according to the invention;
FIG. 3 is a block diagram of an allocator according to the invention;
4 are timing diagrams of signals established by a time base in the allocator;
FIG. 5 is a block diagram of a tag frequency allocation circuit in the amplifier, one of frequency synthesizers in the allocation circuit being shown in detail; and
FIG. 6 is a detailed block diagram of a conflict resolution logic circuit in the allocator.

 With reference to FIG. 1, the organization of an asynchronous digital time division multiplexing system in which an allocator 1 according to the invention is included is first recalled. The asynchronous time system comprises a unidirectional bus 2 for distributed transmission of data packets from I data sources S1 to S1 to a data concentrator CON connected to an asynchronous time switching network (not shown). For example, the multiplexing system is a part of a corporate LAN or subscriber facility to connect to an Integrated Services Digital Switching (ISDN) network across the concentrator CON. Each source constitutes means of data transmission included in a terminal of the local network.

Each source is connected to the bus 2 through a PN1 to PMI packager-multiplexer. Each packet-multiplexer
PM1 to PMI is authorized to transmit a data packet in the bus 2 under the control of the allocator 1 included in the concentrator CON, via a unidirectional bus 3 distributed on each of the multiplexer-packagers.

 The sources S1 to SI respectively transmit data to the PM1 to PMI multiplexer packagers through digital channels VNi to VNI having respective rates d1 to dI. The rates d1 to d1 are different from each other in general, and are less than a predetermined maximum rate dH.

In practice, the bit rates of the sources exceed a given minimum bit rate dm, for example of a few hundred bits / s. The sources at SI are respectively associated with PRO1 control processors PROI which allow to report to a central processor 4 included in the concentrator CON of the source activations.The central processor 4 is connected to the PRO1 PROI processors through a star network bi-directional links 401 to 40I in which various signaling signals between each source and the processor 4 pass through so that the source requests a transmission authorization, that is to say an access to the bus 2 to transmit data and thus signals its activation at the beginning of a communication or so that the source signals its deactivation at the end of a communication. In the following, we consider the operation of active sources after the exchange of signaling signals at the beginning of a communication. At a given moment, sources are active and other sources are inactive.

Each packet-multiplexer PM1 to PF packets the digital signal transmitted by the digital channel VN1 1a to
VNI of the active source associated with #i SI. Each packet to be transmitted in the bus 2 consists of a block having a predetermined number of bits b = ke, where k is an integer, and a label E1 to E1 of source having e bits preceding the block. A label E i is a binary word representative of the number i of the source Si, where i is an integer varying from 1 to I.The bus 2 asynchronously carries the multiplexed packets delivered by multiplexer packers associated with several active sources simultaneously having received authorizations to transmit in the form of labels from the allocator 1 through the allocation bus 3.

 As shown in Fig.2, the transmission of tags in the bus 3 is divided into consecutive time intervals each having an allocation period equal to e. In each time interval, a second half-period 8/2 is adapted to be occupied by a label E. The tags E are multiplexed in the bus 3 by the allocator 1 as a function of the rates d1 to d1 of the active sources and an order of priority of these active sources, as will be seen in the following. In bus 2, a packet is transmitted by a source for a duration less than e, in response to the respective tag.

 For a maximum rate dH of the sources, the allocation period e is determined according to the transmission characteristics of the packet transmission bus 2 and the number of bits e and b, as indicated in FR-A-2 553 605. In the following, it is assumed that each packet comprises a label having e = 8 bits followed by an information field consisting of a block of b = 120 bits; the maximum source rate is dM = 124 Mbit / s and the minimum source rate is of the order of 500 bit / s. Knowing that only one packet at a time can not be transmitted during an allocation period e, it is at most equal to b / dM = 1201 (124.10), ie e <967.7ns; typically e is chosen equal to 933.3ns which corresponds to a clock frequency for the transmission of tag bits in second half-periods periods e such that h = 2e / e = 17.14 MHz.

 As shown in FIG. 3, the allocator 1 essentially comprises a tag frequency allocation circuit 5 for producing tag and therefore packet frequencies as a function of active source bit rates, a logic circuit of resolution of conflicts 6 to select an allocation request from a priority active source compared to those of other active sources # during an allocation period, a memory of active source labels 7 of the RAM type, a circuit of addressing and write control and reading 8 relating to the memory 7 in particular, and a time base 9.

The time base 9 contains a clock 90 at the frequency h = 2e / e of the tag bits in the bus 3, a frequency divider by 2e 91 to provide a clock signal e at the tag frequency, and a decoder 92 connected to the divider 91 to provide various logic signals specific to the operation of the other circuits in the allocator 1. As in FR-A-2 553 609, the bus 3 is composed of a digital line 30 transmitting the labels leaving an output register 71 of the memory 7, a digital line 31 transmitting a label synchronization signal e, complementary to the signal e, whose second half-periods in the state "1" frame the labels in line 30, the signal e in line 31 being produced from the signal
O through an inverter 93 and a delay line 94, and a digital line 32 transmitting the clock signal h to the label bit rate through a delay line 95. The delay lines 94 and 95 are intended to to phase the transmitted signals o and h in the bus 3 with the tags in the line 30 due to the processing of the logic signals in the allocator 1 between the detection of an allocation request at the output of the circuit 5 and the reading a tag in the output register 71. The various logic signals produced by the decoder 92 are pulse signals ho to h 2e-1 = h15 having pulses having a width of e / 4e and successively shifted by X / 2e , as shown in Fig.4, as well as other logic signals obtained by simple logic operations on the signals 0, o and ho to h15 and mentioned in the course of the following description.

 The memory 7 contains K cells of e = 8 bits 701 to 70R able to each store a label of any active source among all sources S1 to SI. The number K of cells is generally much smaller than the number I of sources and is chosen according to the average traffic of the sources. Typically, K is equal to 16 for several tens of sources. When the central processor 4 receives a transmission request from a source S1 via a link 401 to 401 in order to establish a communication, it allocates a free cell 70k of predetermined rank. k in the memory 7 at the source, where k is an integer between 1 and K; if all the cells in the memory 7 are occupied by active source tags, the processor 4 refuses the communication; according to another variant, the processor stores the label of the source in a queue in order to recall the source as soon as a cell in the memory 7 is free.

 To prevent the central processor 4 from accessing read memory 70, the search for free words is performed in a memory image of the memory 7, located in the central processor 4 and consisting of K words of 1 bit giving the state free or busy of each word of the same address of the memory 7.

 As will be seen below, at each cell 70k having a predetermined rank k in the tag memory 7 are associated one, 50k among K frequency synthesizers in the allocation circuit 5 and one, 63k among K word registers. of priority in the conflict resolution circuit 6.The label Ei of an active source Si, two frequency ratios Ai and Bi and a priority word Pi attributed to the source Si, in particular as a function of its bit rate d1, are transmitted by the central processor 4 via a data and addressing bus 41 to the circuits 5, 6 and 8 for writing in the cell 70ks in two programmable dividers in the synthesizer 50k and in the priority word register 63k These latter The circuits are writable during the second half-period of an allocation period e by respective addresses ADR and the write control signals CE also transmitted by the processor 4 through the bus 41.

 In particular, in the circuit 8, the label Ei and the address of the cell 70k are respectively loaded into a write register 80 and a write address register 81 during a first half-period of the period o During which a conflict resolution and a label reading take place, as will be seen in the following. Then during the second half-period of the period 0, the cell 70k is addressed by the register 81 through a read and write address multiplexer 82 and stores the label Ei exiting the register 80 under the control of a signal i.h8 provided by the decoder 92.

This marking operation of the cell 70k allocated to the source Si is simultaneous with that relating to the synthesizer 50k and to the register of the priority word 63k. Thus, during the second half-period of each allocation period e, the processor 4 can perform marking a label in the memory 7.

 The tag frequency allocation circuit 5 consists in producing a tag frequency fi corresponding to the bit rate di of an active source that has requested a packet transmission authorization request near the central processor 4, and more specifically, corresponding to the packet rate of this source in the bus 2, such that fi = di / b. In this case, the processor 4 selects one of K = 16 identical frequency synthesizers 501 to 50K included in the circuit 5. As will be seen in the following, the selection of a free synthesizer is performed during a marking the label corresponding to the source that requested an authorization to transmit.

Given the parameters indicated above, the range of frequencies to be supplied by a synthesizer 501 to 50K is between a minimum frequency f = d / b = 500/120 Hz and
m a maximum frequency fM = dM / b = 124.10 / 120 Hz, which corresponds to a ratio of fM / fm = about 250000.However, such a frequency range is impossible to obtain by means of a simple locking loop of because it is considerably wider than those for known voltage-controlled oscillators (VCOs), which, with certainty, are between a determined minimum frequency F and a
m maximum frequency FM = 3F
m
One, 50ks of the synthesizers in the circuit 4 is shown in detail in Fig.5. The synthesizer comprises a phase locked loop 51 to 54 followed by a programmable frequency divider 55. The phase locked loop comprises successively a voltage controlled oscillator (VCO) 51, a programmable frequency divider 52, a comparator of phase in the form of an exclusive-OR gate 53 and a low-pass filter 54. The gate 53 has an input connected to an output of the divider 52 and another input receiving a frequency signal FR / C transmitted by a clock of reference 42 included in the central processor 4, to all the synthesizers 501 to 50K The clock 42 comprises a crystal oscillator 43 producing a high frequency FR, followed by a frequency divider by an integer C 44 to produce the signal FR / C.

The frequency dividers 52 and 55 have respective division ratios A and B programmed by the central processor 4 and transmitted by the data bus 41 during a marking operation. The ratio A is between two limit values A
m and AN in order to get all the frequencies in the output frequency range of the synthesizers from f to fM for the
m frequency variation of the oscillator 51 between FM and
F, which results in the following relationships
fM FM / Am and f = F /
mmn
Typically, when the divider 55 is embodied as a 16-bit counter, the limit values of the ratio A are
A = 1 and AN = 216 = 65536 which corresponds in practice to frequencies f between f = FH / 3 / AN = 5.25 Hz, ie a minimum source flow d = f .b = 5.25.120 = 630 bit / s, and f i6 m, mf H = FH = 124.10 / 120 = 1.033.10 Hz. For example, the voltage controlled oscillator 51 is that of the company
TEXAS INSTRUMENTS, designated LS628, whose frequency variation range can be between F = FM / 3 = 0.344.10 Hz
6 m and FH = 1.033.10 Hz for a capacity 56 of about 1 nF.

The output of the oscillator 51 is connected both to the input of the frequency divider 55 and to the input of the frequency divider 52, so that the output frequency F of the synthesizer can be expressed by the relation
f = (FR / C) .B / A
For fixed values of C and B, an increment of one unit of A decreases the frequency f of
Af = f (A) - f (A + 1) = f (A) / (A + 1)
At low frequencies, characterized by f (A) small and A large, the increment Qf is small, whatever the combinations of B and C that approach f (A). Conversely, at high frequencies, f (A) is large and A small. We must therefore choose small FR and large C and essentially modify B to obtain low increments. Thus, it is of no interest to vary C it is simpler to fix the ratio C once and for all at a maximum value CH and therefore to choose a non-programmable frequency divider 44. Such a choice is superabundant at low frequencies but simpler about the values to be calculated by the central processor 4.

It remains to determine the frequency FR and the range of variation of the ratio B between values B and BM.
m latching phase lock loop (PLL) is written
FR / CM = F / B with FH / Fm = 3, which implies: B / B = 3.

mm
From the hooking condition, it is deduced that the theoretical minimum frequency of FR is equal to FM.

 In practice, the frequency FR is produced by a base clock 43 in the central processor 4. For example, the processor 4 is an Intel 88/45 processor card, for which the frequency FR is equal to 8 MHz, and the divider 43 is in the form of an integrated circuit INTEL 8254 of this same card, programmed at CM 64000.

Finally, a clock frequency of PR / CM = 125 Hz is obtained.

From this we deduce B M = FH / FR / CH = 1.033.106 / 125 = 8264 and B = Bu / 3 = 2755.

m
The dividers 55 and 52 are also made by circuits
INTEL 8254 which represents the double advantage of benefiting from their very strong integration and their immediate interfacing with the INTEL 88/45 card which constitutes the central processor.

To obtain a frequency f, expressed in Hz, at the output of a synthesizer, the processor 4 programs the dividers 55 and 52, each made in the form of a 16-bit counter, according to the following algorithm given by way of example . This algorithm is directly inspired by the preceding remarks. To obtain a frequency f such that FM> = f> = Fm, the ratio A is fixed at 1, and the ratio B varies only between B and BM; to get a
m H frequency f such that f <F, the ratio B is set to a value
m average (BM + B) / 2, and the ratio A varies only between A and
m
AN Such an algorithm has the advantage of simple programming of the processor 4.

When any source If requires a packet transmission authorization request via the link 40i, it transmits the respective rate di to the central processor 4 which deduces the label frequency fi = di / b. As already mentioned, the processor 4 selects a free synthesizer 501 to 50Ks such as the synthesizer 50ka or if all the synthesizers are already allocated to active sources, the processor 4 refuses the request of the source; according to another variant, the processor 4 marks the request of the source in a queue to subsequently allocate a free synthesizer. After the selection of the synthesizer 50ks the programming of its frequency dividers 52 and 55 is carried out as follows. The ratio A is first fixed at Ai = 1 and the ratio B is calculated according to the relation B i = fi / FR / CH; if the calculated value of the ratio B is greater than BM, the processor 4 indicates to the source via the link 40i that the transmitted bit rate is wrong since the frequency fi is then greater than f; as already said, if Bm = <Bi = <BM, the values Ai = 1 and Bi = fi / FR / CH are retained; if the calculated value of the ratio B is less than Bm, the processor 4 sets the value of B to Bi = (BM - + Bm) / 2 and calculates the value Ai = (FR / CM). (BM + B) / 2 /fi.Lorsque
the values Ai and Bi of the ratios A and B are calculated, the
central processor 4 loads these values into the dividers
programmable 55 and 52 of the selected synthesizer 50k via the bus
given 41.

According to a first example, for a source Si having a digital channel VNi carrying a video channel at a bit rate of
61 Mbit / s, the tag frequency is fi = 61.106 / 120 =
508.33 Hz; for A = 1, we deduce BM> fi / 125> Bm,
ie Bi = 4067. In a second example, for a source having a digital channel VNi + 1 carrying a data channel at a rate of di + 1 = 2400 bit / s, the label frequency is fi + 1 2400/120 = 20 Hz; for A = 1, we fled + 1/125 = 0.16 <Bm, and we
m therefore chooses Bi + 1 = (BM + Bm) / 2 = 5510 to deduce
Ai + 1 = 125.5510 / 20 = 34438.

Referring now to FIG. 6 is the conflict resolution logic circuit 6. The circuit 6 comprises K = 16 D-type flip-flops 601 to 60Ks two buffer registers 61 and 62 each having K parallel stages, K word registers of priority 631 to 63K each buckled on itself, K doors AND two inputs 641 to 64Ks a door OR to K inputs 65 and K logic circuits comparison and locking 661 to 66K
Each of the registers 631 to 63K is able to record one of priority words P1 to PK assigned respectively to the active K sources among the set of sources S1 to S1. Each priority word contains J = log2K = 4 bits p3, p2 , p1 and pOs where p3 and pO denote high and low bits
low priority word. According to certain criteria, and in particular according to the bit rates of the sources, the central processor
4 associates with each active source that has requested a request for
transmission in order to allocate intervals o in the bus 3 and
for which a free synthesizer 501 to 50K is selected,
a priority word whose bits are recorded in parallel in
the corresponding register 631 to 63K during the marking phase of the label of the source in the memory cell
corresponding 701 to 70K> as will be seen later. The priority words are respectively applied to the registers 631 to 63K through K n 4 wires of the data bus 41. The K priority words are all different and in practice, those having high binary values are attributed to the active sources having data rates. high in order to avoid congestion of the FIFO type queues included in the multiplexer-packagers associated with high-rate active sources. When two active sources have identical rates, the corresponding priority words differ by one unit. Thus, tag allocation requests for active sources associated with high bit priority words have priority over those for active sources associated with lower value priority words. , the priority word assigned to an active source during communication can be modified by the central processor 4 in order to keep the flow hierarchy in particular when other communications are broken and new communications are established.

 In FIGS. 3, 5 and 6, it is assumed that the cells 701, 70k and 70Ks the synthesizers 501, 50k and 50K and the priority word registers 631, 63k and 63K have been assigned to the active sources Si + 3, Si and Si + 1 by the processor 4, respectively, following requests for transmission authorization from these sources.

 Requests for allocation of the synthesizers 501 to 50K associated with active sources are characterized by a transition from the state "0" to the state "1" of the outputs 571 to 57K of the frequency dividers 55 in the synthesizers applying logic signals from frequencies fl to f K at clock inputs C of flip-flops 601 to 60K The inputs D of flip-flops 601 to 60K are permanently maintained at "1". At the beginning of a comparison cycle of the priority words, corresponding substantially at the end of a first half-allocation period @ / 2, in response to a signal O.h6 provided by the time base 9, one of the latches 601 to 60K associated with a priority source of which a request for allocation has been satisfied during the previous allocation period is reset by an RZ input.

 The other allocation requests stored in the latches 601 to 60K and thus not yet satisfied are loaded in parallel in the register 61, in response to the rising edge of the signal e. h8 provided by the time base 9 at the beginning of the second period of a first allocation period 0. The signal t.h8 controlling the register loading 61 is totally asynchronous of the transitions "O" to "1" of the signals to f K and thus passages to "1" outputs Q flip-flops 601 to 60K respectively connected to K inputs of the register 61. States of some outputs of the register 61 which correspond to a sampling of the outputs of latches being changed d the state, are then unstable for a period of time. To remedy this drawback, the following register 62 having K inputs respectively connected to the K outputs of the register 61 copied the contents of the register 61 in response to a signal e. h0 provided by the time base 9 at the beginning of a second allocation period s following the first allocation period already mentioned. The outputs of the register 62 which are in the state "1" thus indicate conflicting requests for allocation of the bus 2 during the same period e.

The K outputs of the register 62 are connected to first inputs of the AND gates 641 to 64K having second inputs connected to the outputs of the priority registers 631 to 63Ks respectively. Clock inputs C of registers 631 to 63K receive four successive pulses in a signal O (ho + h1 + h2 + hui) provided by time base 9 in order to successively apply bits p3 to p0 of priority words to second inputs of the gates 641 to 64R, following the copying of the allocation requests in the register 62.Only the gates 641 to 64K having received an allocation request are opened and successively apply the bits corresponding p3 to pO to the inputs of the OR gate 65 and first non-exclusive-OR gate entries 6611 to 661R included in circuits 661 to 66K
Resolving conflicting allocation requests during an allocation period o is based on the Nisnevich algorithm.

Applied to the invention, this algorithm consists in comparing the bit pj in each priority word with the logical sum of the bits pj of all the priority words contained in the registers 631 to 63K. The priority words for which a difference is noted are removed from the following comparison operations in which processes similar to the previous one are performed on the other bits P; 1 to pO respectively.Basing that the successive comparisons evolve from the high-order bits PJ = P3 to the low-order bits p0> at the end of the comparison cycle there remains only one priority word whose binary value is the highest. high and which is the priority source for the current allocation period. Thus, at the instant O.ho, the comparisons of the most significant and rank 1 bits p3 coming from the open gates 641 to 64K are carried out simultaneously with the sum of these bits; then, at the same time, the comparisons of P2 bits of rank 2 issuing from open gates 641 to 64K are carried out simultaneously with the sum of these bits; and so on until low order PO bits of rank J = 4. The logical sum of the bits of the same rank in the priority words is performed by OR gate 65 having an output connected to second inputs of comparison 661 to 661
Each of the comparison and blocking circuits 661 to 66K includes, in addition to the gate 6611 to 661K, a NAND gate 6621 to 662K having a first input connected to the output of the gate 6611 to 661, a D-type flip-flop. 6631 to 663K having an input D connected to the output of the gate 6621 to 662K and a complementary output Q connected to a second input of the gate 6621 to 662K, and an AND gate 6641 to 664K having a first input connected to the output Q of the flip-flop 6631 to 663K and an output connected to the input RZ of the respective flip-flop 601 to 60K Clock inputs C of the flip-flops 6631 to 663K and second inputs of the AND gates 664 to 664K respectively receive 0 signals. ho + hl + h2 + h3) and .h6 of the time base 9.

Prior to the comparison cycle, the flip-flops 6641 to 664K are reset by the signal O.h8 applied to their inputs RZ, simultaneously with the sampling of the outputs of the flip-flops 601 to 60K in the register 61. NAND gates 6621 to 662K are opened when the gates 6611 to 661K transmit the results of the comparisons of the most significant bits p3 with the sum of these bits. These first results of comparisons are sampled in the flip-flops 6631 to 663K under the control of signal @ .ho. The outputs Q of flip-flops 6631 to 663K which remain in state "1" after the pulse e. h correspond to equalities between the bits p3 in the respective registers 631 to 63K p3 and the sum of all the bits p3 and allow subsequent comparisons relating to the next row bits leaving the corresponding NAND gates 6621 to 662K open; in contrast to this, inequalities resulting in a "0" state at the gate outputs 6611 to 661K and flip-flops 6631 to 663K imply closure of the corresponding gates 6621 to 662K and thereby inhibit results of comparisons of the p2 to pO bits. priority words associated with these gates with the corresponding sums of bits and thus "remove" the corresponding priority words in the subsequent comparison operations. Processes corresponding to the previous one are performed relative to the bits p2, p1 and p0 in response to the signals of offset e.h1, # .h2 and O.h3 applied to registers 631 to 63K and to the comparison result sampling signals e. h1, # .h2 and O.h3 applied to 6631 to 663K flip-flops
At the end of these K = 4 comparison processes, a single flip-flop 6641 to 664K provides a Q output at state "1" designating register 631 at 63K containing the priority word of the highest priority source for the period of time. allocation e in progress. This state "1" makes it possible to select the read address of the cell 701 to 70K in the memory 7 having recorded the label of the priority source and corresponding to the synthesizer and the priority word register of same rank 1 to K, and thus satisfy the allocation request of the priority source by transmitting a label in the bus 3. Moreover, the output Q at the "1" state of the previous "priority" toggle 6641 to 664K resets the associated peer 601 to 60K through the associated AND gate 6641 to 664K in response to the e.h6 signal, and thus clears the allocation request that has just been selected and satisfied. An upcoming label from the source priority can only be transmitted at the earliest, after the next transition "O" to "1" of the associated logical signal f1 to
It should be noted that, as already stated, the change of priority words in the registers 631 to 63 is performed by the
K central processor 4 when the signal o is equal to "1" and therefore outside the run periods of the conflict resolution algorithm.

Referring back to Fig. 3, the control and descrambling circuit 8 comprises a read address encoder 83 having
K = 16 inputs respectively connected to the Q outputs of the flip-flops 6631 to 663K, and an output bus to log2e = 4 wires connected to the memory 7 through the address multiplexer 82. In response to the signal 8 ~ ho, the encoder 83 provides the address of the cell of the memory 7 for which the Q output of the flip-flop 6631 to 663K is in the state "1" in order to load the corresponding label of the priority source of the memory 7 into the output register 71, via a son bus 72, in response to a signal O.h7 provided by the time base 9. Then during the second half-period of the period 8, 11 tag is read serially in the register 71 and transmitted in line 30 of bus 3 to the rhythm of the signal eh

 Finally, it should be noted that sources may each offer variable data rates, which does not modify the operation of the allocator described above since a transmission authorization request in a link 401 to 401 issued by a source is always accompanied by the value of the rate at which the requested communication will take place.

Claims (14)

 1 - Device for allocating consecutive allocation periods (e) in a distributed bus (3) to several asynchronous data sources (S1 to SI), said sources having different data rates (d to dI) and being identified by respective labels (E1 to EI), each of said allocation periods being capable of being occupied by at most one label of one of active sources having requested a data transmission authorization, said device comprising control means (4) receiving the transmission authorization requests (40i) accompanied by the data rates of the active sources, a memory (7) having cells (701 to 70K) for each storing a tag, means (80, 81) controlled by the means of command for writing labels (Ei) in the memory in response to requests for transmission authorization, and means (83) for reading stored tags for transmission in the bus (3) during allocation periods (o), characterized in that the control means (4) assign priority words (Pi) to said active sources (Si) and the means for writing (80, 81) write the label (Ei) of each active source (Si) than in a single free cell (70k) of the memory (7) regardless of the bit rate (di) of the active source, and in that the device comprises means (5) for establishing periodic allocation requests respectively at label frequencies (f 1 to fK) substantially proportional to the rates of the active sources in a predetermined ratio (b), and means (6) for selecting an allocation request a priority source among those of active sources not yet satisfied at each allocation period (e), as a function of the priority words, so that the means for reading read out the memory cell (50k = 50i) containing the label (Ei) of the selected priority source (Si) for the transmitting on the bus during said allocation period, said allocation request satisfied with the priority source being cleared until the next allocation request for the selected priority source is established.  2 - Device according to claim 1, characterized in that the means for establishing allocation requests (5) comprises a plurality of programmable frequency means (501 to 50K) respectively associated with the memory cells (701 to 70K) each means with programmable frequency (50k) being programmed by the control means (4) as a function of the flow rate (di) of the active source (Si) whose label (Ei) is contained in the associated memory cell (70k) in order to provide allocation requests at the tag frequency (fi 3 fk) of said source  3 - Device according to claim 2, characterized in that each of the programmable frequency means (50k) comprises a first frequency divider (55) programmable first programmable division ratio A and a phase locked loop (51 to 54) including a second frequency divider (52) having a second programmable division ratio B interconnected between an output of a voltage controlled oscillator (51) connected to an input of the first frequency divider (55) and a first input of a comparator phase converter (53) having a second input receiving a clock frequency signal FR / C, said first frequency divider (55) providing allocation requests at a frequency (fk = equal to (FR / C) x ( B / A).  4 - Device according to claim 3, characterized in that the first divisional ratios A are programmed between the first limits Am and AM such thatA  m and AH such that A = F / f and AN = F iF / f, where Fm and FM designate minimum and maximum frequencies of the oscillator (51) and f and fM designate  m minimum and maximum label frequencies corresponding to minimum and maximum rates (dom, dH) of the sources (S1 to and in that the second division ratios B are programmed between second limits B and BM such that  m B / B = F IF  Mm Mm  5 - Device according to claim 4, characterized in that the first minimum limit A of the first report of  m division A is equal to unity.  6 - Device according to claim 4 or 5, characterized in that for a given tag frequency fi of an active source (Si) assigned to a free programmable frequency means (50k) the control means (4) calculate first and second frequency division ratios Ai and B i according to the following steps  a) Ai is set to 1 and the second ratio is calculated according to the relationship Bi = fi / FR / C  b) if Bi> BM> Ai and B i are not loaded in the first and second dividers (55, 52) of said programmable frequency means (50k)  c) if Bm = <Bi = <BM> Ai and Bi are loaded into said first and second divisors (55, 52);  d) if Bi <Bm> Bi is set to Bi = (BM + Bm) / 2, and Ai is calculated according to the relation A i = (FR / C) [NR] (BH + Bm) / 2 / fi, and the previous values of A 1 and B 1 are charged to said first and second dividers (55, 52).  7 - Device according to any one of claims 1 to 6, characterized in that the means for selecting (6) comprises means (60, 61, 62) for maintaining each of the allocation requests until it is not satisfied, means (63, 64) for reading priority words (P) associated with said unsatisfied allocation requests, means (65, 66) for comparing priority words read between them in order to deduce therefrom among them the priority word (Pi) assigned to a priority source (Si) and to satisfy the allocation request of the priority source by commanding through the means to read (83) a reading of the memory cell (70k) containing the label (Ei) of the priority source (Si).  8 - Device according to claim 7, characterized in that the means for maintaining comprise several means (601 to 60K) respectively associated with the memory cells (701 to 70K) for each detecting allocation requests at the frequency of the tag (fl-fK) corresponding to the source whose tag is contained in the associated memory cell, means (61) for sampling allocation requests detected at each allocation period (e), and means (62) for copy the allocation requests sampled at the beginning of an allocation period following the allocation period mentioned above.  9 - Device according to claim 8, characterized in that the allocation requests are in the form of predetermined transitions ("0" to "1") of logic signals (f 1 at said label frequencies, and in that each of the means for maintaining consists of a flip-flop (601 to 60K) having a clock input (C) receiving one of said logic signals.  10 - Device according to any one of claims 7 to 9, characterized in that the means for reading priority words comprise a plurality of shift registers (631 to 63K) looped on themselves and respectively associated with the memory cells ( 701 to 70K) for respectively registering priority words corresponding to the sources whose tags are contained in the associated cells, and means (641 to 64K) for successively transmitting in parallel bits of the same weight of the priority words to the means for comparing (65, 66) in response to unsatisfied allocation requests sampled at the beginning of each allocation period (e).  11 - Device according to any one of claims 7 to 10, characterized in that the sources (S1 to SI) are even more important than the priority words (P1 to PI) assigned to them have values high and in that the means for comparing (65, 66) comprises means (65) for performing the logical sum of bits of the same rank in the priority words (P), several means (6611 to 661K) respectively associated with the memory cells (701 to 70K) for simultaneously comparing the logical sum of bits of a given rank in the priority words with the bits at said given rank, said means for comparing performing said comparisons successively from the most significant bits (p3 ) up to the low order bits (p0) of the priority words, several means (6621, 6631 to 662K, 663) respectively associated with the memory cells (701 to 70Ky to inhibit simultaneous comparison results which have given rise to s inequalities and to keep results of the simultaneous comparisons giving rise to equalities in order to determine the priority word of said priority source having given rise to only equalities for all the bits of said priority word and several means (6641 664K) respectively connected to the means for inhibiting and keeping to clear the allocation request of said priority source in the means for maintaining (60, 61, 62).  12 - Device according to any one of claims 7 to 10, characterized in that the sources (S1 to SI) are even more important than the priority words (P1 to PI) which are attributed to them have high binary values and in that the means for comparing comprises an OR gate (65) simultaneously receiving in parallel bits of the same rank in the priority words (P1 to PK) and successively the bits of the priority words from from the most significant bits (p3) to the least significant bits (p0) of the priority words, and associated with each of the memory cells (70k); a non-exclusive-OR gate (661k) having an input connected to an output of the OR gate and an input successively receiving the bits of the associated priority word (Pk = Pi)> a NAND gate (662k) having an input connected to the output of the NOR gate (661k) , and a flip-flop (663k) having a data input (D) connected to the output of the NAND gate (662k) and a complementary output (Q) connected to another input of the NAND gate (662k).  13 - Device according to any one of claims 1 to 12, characterized in that the priority words assigned to the active sources having cleaned flow rates have high binary values.  14 - Device according to any one of claims 1 to 13, characterized in that sources (S1 to operate each with variable rates.