FR2587498A1 - Detector of digital phase and/or frequency over a wide range - Google Patents

Abstract

A detector of digital phase and frequency of a phase-lock loop comprises a logic gate 140, 142 interconnected with two bistable devices 20, 22 clocked respectively by a digital input signal V and a digital reference signal R so as to produce a square wave whose duty factor corresponds to the difference in phase and frequency between the two signals. The duty factor of the square wave repeatedly sweeps over values lying between a minimum and a maximum when the phase and frequency differences vary monotonically. The square wave is integrated 36 so as to produce a repeating saw-tooth wave. In order to increase the range, a circuit is provided which produces a constant level signal as the peak of the saw-tooth is approached and which repositions the bistable devices by producing a multiple of the previous range.

Description

 The present invention relates generally to circuits making it possible to compare the phase difference and, or alternatively, the frequency existing between two digital input signals and, more particularly, it relates to a method and a circuit making it possible to increase the interval of linear phase modulation of a phase detector and, alternatively, digital frequency in a phase locked loop through the use of a circuit which responds to the maximum detector interval by producing an output signal which s 'adds to the detector output signal when repositioned.

 A circuit for determining the phase difference and the frequency difference between two digital input signals is of general utility for signal analysis and is particularly important for digital telecommunications and frequency synthesis. In a digital phase lock loop, for example, an input signal is applied to a phase detector for comparison with a reference signal. The error signal, which is a function of the instantaneous phase difference and, alternatively, of frequency between between the input signals, is filtered and applied to the control of a voltage-controlled oscillator (vu0). The output signal of the VCO, which constitutes the output signal of the phase lock loop, is applied as a reference signal to the phase detector in order to cause the phase and, or alternatively, the frequency of the VCO to "lock" "on the phase and, or alternatively, frequency of the input signal.

In some applications, phase lock loops are used for signal demodulation, as discussed in Gardner,
Floyd M., Phase Lock Techniaues, second edition, 1979, John Wiley & BR <
Sounds, Chapter 9. In other applications, phase lock loops are used for signal demodulation (Gardner, Chapter 9, sucra) or frequency synthesis, as described in the United States patent. n04 360 788.

 In all cases, a conventional phase and, or alternatively, digital frequency detector comprises a pair of flip-flops, or other bistable devices, connected together and with a logic gate in a feedback circuit. The logic states of the two flip-flops are determined both by the two digital input signals whose frequency and, or alternatively, phase difference is to be detected and by the reaction gate. The flip-flops being initially repositioned, the data terminals of these are connected on a logic "1" level, and the clock terminals are respectively connected on the two digital input signals.

The output of each flip-flop is positioned on a logic "1" level upon detection of a positive transition in its input signal.

Thus, if the input signal applied to the first flip-flop has the first positive transition, the first flip-flop is positioned on a logical level "1", then the second flip-flop, at a positive transition in its input signal is positioned on a logical level "1". Immediately after the second flip-flop has become positioned, the two flip-flops are however repositioned by the logic gate which responds to the output signals of the two flip-flops, and both remain repositioned until the first flip-flop or the other flip-flop , detects a positive signal transition on its input.

 The output signals of the two flip-flops are therefore square waves having utilization coefficients which correspond to the difference in phase and, or alternatively, in frequency between the two input signals. If the first signal is ahead of the second signal, only the first flip-flop develops a square wave, the utilization coefficient corresponding to the amount of phase advance and, or alternatively, of frequency existing between the two input signals . If the second input signal is early, only the second flip-flop develops a square wave, the utilization coefficient corresponding to the amount of phase advance of the second input signal compared to the first. The two square waves are combine in a difference circuit, and the result is integrated to produce a sawtooth approximately centered on zero, i.e. the sawtooth has a certain polarity when the first input signal is early and the opposite polarity when the second input signal is early.

The sawtooth has an amplitude which corresponds to the phase difference and either the frequency existing between the two digital input signals and has a fixed period of 3600. As the phase difference and either the frequency between the two input signals increases monotonically, the detector output signal is a sawtooth signal train having a number of sawtooth cycles which corresponds to the number of complete cycles of phase difference and, or , frequency between the two digital input signals.

 A main object of the invention is therefore to propose a method and a circuit making it possible to increase the detection interval of a phase and, or alternatively, digital frequency detector.

 An object is to provide a method and a circuit making it possible to increase the maximum average output signal of a phase detector and, alternatively, digital frequency by producing the output signal of the detector at a peak value when the difference in phase and, or alternatively, frequency between the input and reference signals is a predetermined quantity repositioning the internal circuit, and adding the phase difference and, or alternatively, additional frequency to the output signal of the detector.

The following description, intended to illustrate the invention, aims to give a better understanding of its characteristics and advantages; it is based on the accompanying drawings, among which
- Figure 1 is a block diagram of a digital phase lock loop according to the prior art of the type in which it is possible to incorporate the frequency detector and, or alternatively, phase of the invention;
- Figure 2 is a circuit diagram of a phase detector and, or, digital frequency according to the prior art with respect to which the invention offers an improvement;
- Figures 3 (1) to 3 (5) are waveforms illustrating the operation of the phase detector and, alternatively, the conventional digital frequency of Figure 2;
- Figure 4 is the output characteristic of the phase and, or alternatively, conventional frequency detector of Figure 2;
- Figure 5 is the desired characteristic of the phase detector and, or alternatively, improved digital frequency
according to the principles of the invention;
- Figure 6 shows time domain diagrams of the waveforms according to the invention; and
- Figure 7 is a circuit diagram of the invention.

The invention aims to improve the Linear phase modulation interval of a digital phase locked loop of the type described in United States patent 4,360,788 and in United States patent application America No. 629 555 filed July 10, 1984 by Cok, which loop was incorporated into frequency synthesizers manufactured by the company John
Fluke Mfg. Co., Inc., of the United States of America.

 In FIG. 1, the conventional phase locking loop, generally designated by the reference 10, comprises a phase detector 12 of a type to which the invention is applied, a filter 14 and a voltage-controlled oscillator ( vC0) 16 connected in a loop. The phase detector 12 has an input which receives an input signal F. and a second input which receives a reference signal F r and it produces a signal corresponding to the difference in phase and frequency between the two input signals.

The detector signal is filtered by the filter 14 and is applied, as a control input signal, to the VCO 16. The output signal from the VC0 16 is returned via a programmable frequency divider 18, as the reference signal F to the detector phase 12. As described in detail in U.S. Patent No. 4,360,788 cited above, the signal produced by the VC0 16 is controlled so as to have a frequency which is a multiple or a sub- multiple, according to the programming of the frequency divider 18, of the input signal Fi and a phase having a predetermined relationship, as a function of the offset polarization incorporated in the detector 12, with respect to the phase of the signal Entrance.

 It should be understood that, while a particularly important application of the phase detector of the invention consists of a phase locking loop such as that presented in FIG. 1, the phase detector has many other notable applications in the signal processing and signal measurement.

 The relatively low maximum average output signal of the phase detector and, alternatively, the conventional frequency on which the invention gives an improvement can be fully understood before the invention can be appreciated. A conventional detector, represented in FIG. 2, comprises a pair of flip-flops 20 and 22 which, by way of illustration, are flip-flops of type D. In a flip-flop of type D, a logic level applied to the terminal D is trans - applied to the output terminal Q as soon as the application of a rising clock pulse to the clock terminal occurs. Each D-type flip-flop 20 and 22 also has an output terminal Q 'which produces the complement logic of the output terminal Q, and a repositioning terminal R which, in response to a signal of logic level "0", or signal "low", reposition the output terminal Q on a logic level "0". By way of illustration, it is assumed that flip-flops 20 and 22 operate on the basis of positive logic, that is to say that a level "1" is defined as being a "high" voltage and a level logic "O" is defined as a "low" voltage.

 A NAND gate 24 has two inputs respectively connected to the output terminals Q of flip-flops 20 and 22 and an output terminal which is connected to the repositioning terminals R of the two flip-flops. The input terminal D of each of the flip-flops 20 and 22 is connected on a logic "1" level and the two clock terminals are respectively connected on a first variable (input) signal V and a second signal (reference ) to stare.

The input signal V can correspond to Fi and the input signal R can correspond to the signal F r of FIG. 1, although the two signals V and R can be arbitrary. In addition, while the two signals V and R are, in the general case, digital or square wave signals having variable and different frequencies and phases, the signal R can be a reference signal having a frequency and a phase fixed.

The output signals Q of flip-flops 20 and 22, res
respectively designated by 26 and 28 are applied to filters 30
and 32 so as to produce Q and L output signals and then to a
addition circuit 34. The output signal of addition circuit 34 is typically taken on average or filtered in an integrator 36.

When the detector circuit 12 is applied to a phase lock loop, the output integration is carried out by the normal phase lock loop filter, such as 14 in FIG. 1.

 From a general point of view, as regards detector 12, the output terminal Q of each flip-flop 21 or 22 is positioned on a logic level "1" following the positive transition of its clock signal d input, due to an input signal V or an input signal R. However, if the two flip-flops 20 and 22 are positioned, the output signal from the NAND gate 24 applies a logic level "0" to the repositioning terminals R of each flip-flop, so that the two output terminals Q are repositioned on logic level "0". Thus, one or the other of the flip-flops 20 and 22 will be positioned according to that of the input signals V and R which will first have a positive transition; the two flip-flops will reposition as soon as the positive transition of the second of the input signals V and R arrives. The two flip-flops 20 and 22 therefore produce square waves with coefficients of use which correspond to the difference in phase and frequency between the two input signals; if the input signal V is ahead of the input signal R, the flip-flop 20 dominates and produces a square wave while the flip-flop 22 does not; if the input signal R is early, flip-flop 22 dominates and produces a square wave while flip-flop 20 does not.

 We will explain in more detail the operation of the detector 12, and the way in which it is related to the improvement provided by the invention, in relation to FIG. 3 which shows typical waveforms produced inside the detector. phase and in relation with FIG. 4 illustrating the output waveform.

 Figures 3 (1) and 3 (2) respectively represent input signals V and R applied to the two clock terminals of flip-flops 20 and 22. These two input signals are at different frequencies and may have different use coefficients, although the use coefficients do not matter since each flip-flop 20, 22 responds to a posterior flank. Figures 3 (3) and 3 (4) are waveforms of output signals for the signals on lines 26 and 28.

 It is assumed that the two flip-flops 20 and 22 are initially repositioned by the first positive transition 38 'of the input signal V, so that the outputs Q of the two flip-flops 20 and 22 are at logic level "0", as shown in 40 'and 42' in Figures 3 (3) and 3 (4). The following positive transition of the input signal R at 44 'in FIG. 3 (2) causes the output terminal Q of the flip-flop 22 to be positioned on a logic level "1", as shown at 46' in FIG. 3 (4). At the appearance of the following positive transition of the input signal V, as indicated at 48 'in FIG. 3 (1), the output terminal Q of the flip-flop 20 begins to position itself on a logic level "1", and gate 24 responds almost immediately by repositioning the two flip-flops, which brings the output Q of flip-flop 22 to a logic level "0", as indicated at 50 'in FIG. 3 (4).

It is clear that this cycle of events is repeated on the appearance of the positive transition of the input signal R in 52 'and of the input signal V in 54', and is repeated again on the appearance positive transitions of the R and V input signals at 56 'and 58'. During this time, the flip-flop 22, which is "dominant", produces a square wave whose utilization coefficient decreases at the same time as the decreasing difference in phase and, or alternatively, in frequency between the two input signals R and V, and that the output of
The other flip-flop 20 is at a logic level "0".

 After the appearance of the positive transition of the input signal V at 60 ′, the frequency of the pulses applied to the clock terminal of the flip-flop 20 is however such that there will be two pulses, a å positive transition at 58 'and the next with positive transition at 60', before the appearance of the next pulse of the input signal R on the positive transition 62 '. The effect of the second successive pulse in 60 ′ is therefore to position the output of flip-flop 22 on a logic level "1" since the two flip-flops 20 and 22 were previously repositioned before the positive transition 60 '. Then, a positive transition of input signal R, at 62, reposition The output Q of flip-flop 20, and the sequence continues with flip-flop 20 validated and flip-flop 22 disabled, as shown in Figures 3 (3) and The sequence begins again when the phase and frequency difference between the input signals V and R varies, one of the flip-flops being always validated and producing a square wave which has a coefficient of use corresponding to the difference in phase and, or alternatively, frequency, and the other rocker being invalidated. The choice of the rocker validated at any time depends on that of the input signals V and R which is in advance.

 As mentioned, the output lines 26 and 28 of the flip-flops 20 and 22 pass through optional pass filters 30 and 32 to arrive at the difference circuit 34 whose output signal is taken on average or filtered by the integrator 36.

 The difference signal, filtered by the integrator 36, is a sawtooth, represented in FIG. 3 (5) which goes through "0" when the "dominance" is transferred between the flip-flops 20 and 22, as indicated in the region represented by Figures 3 (1) to 3 (3) and is repeated with a period of one complete cycle (210 of phase-frequency, as shown in Figure 4. When the two input signals V and R found within a single cycle, positive or negative, of mutual synchronization or of "locking", the detection characteristic is said to be in the "active region", as indicated in FIG. 4. When the two signals input are outside the active region, the phase detector 12 produces a sawtooth which has a maximum average signal (see the dashed lines in Figure 4) which has an amplitude worth half the amplitude peak of the sawtooth and a polarity which depends on the one of the two signals which leads.

 Referring now to FIG. 5, on which is presented the desired characteristic output signal of the phase detector and, or alternatively, digital frequency, in contrast with the output signal present in FIG. 4 which corresponds to a conventional detector. In FIG. 5, the zero axis 100 defines the level of the zero current. Point 102 of the horizontal zero defines the point at which the input signal V is tuned in phase with the reference signal R. To the right of point 102, the input signal V is ahead of the reference signal R and, conversely, to the left of the zero point 102, the input signal V delays on the reference signal R.

 When the phase shift increases between the input signal V and the reference signal R, the current increases until the slope 104 reaches the normal output level 106. There is a slight discontinuity around the normal output point 211S 106 , as will be explained below, then the current increases up to the peak output point 108 at point 4 which is substantially twice the level of the normal output signal 106. When the phase shift increases beyond 41r . there is a discontinuity which causes the current to drop from the peak output level 108 to the normal output level 106. When the phase shift continues to increase, the current begins to increase again towards the peak output level 108 and repeats all of it indefinitely the 211.

 The discontinuities are due to the existence of different time delays in the flip-flops 20 and 22 relative to the discontinuity 100 of the zero level. The discontinuity in the normal output level 106 is due to the difficulty in adapting the current levels coming from flip-flop 124 and flip-flop 20.

 Conversely, if we examine the situation for which the input signal V delays on the reference signal R, the phase detector and, alternatively, digital frequency operates in a conventional manner in that the current increases in the negative direction until the negative peak output level 110 is reached, a discontinuity existing at this point since the phase shift increases and causes the current level to fall back to the zero level 100.

 Since the electronic components of the detector do not function in an ideal manner, there are certain discontinuities and disturbances which appear on the normal output level 106 and the zero level 100. To avoid the operation at one or the other of these two points , it is desired that the operating level of the detector be positioned far from these two points and, in the preferred embodiment, it is positioned at operating level 112. In the preferred embodiment, this operating level 112 is chosen to halfway between the positive peak output level 108 and the negative peak output level 110.

 With the level chosen for the preferred embodiment, it is possible to obtain a maximum interval for the phase detector and, or alternatively, frequency for both the advance phases and the delay phases. Another advantage is that, by placing the operating level as far from the discontinuities as possible, namely halfway between them, the percentage of disturbance is reduced to a small part of the difference valid for large phases .

 Reference is now made to FIG. 7, where the flip-flops 20 and 22 are presented, which are normally part of a phase detector and, alternatively, a conventional digital frequency. The input signal V is also applied to the clock input of a D flip-flop 124 which is connected by its rest input to the preposition input of flip-flop 20 (while qut: cec ] was not mentioned previously, type D flip-flops are conventionally provided with prepositioning inputs). The input signal V is also supplied to a D type flip-flop 126 whose output Q ′ is connected to the prepositioning and repositioning inputs of flip-flops 20 and 124 respectively.

 The flip-flop 124 is connected by its output Q to the input D of the flip-flop 126 and to the clock input of a monostable multivibrator 128. The output Q 'of the flip-flop 124 is applied to an OR gate with inputs negative 130 whose output is applied to a pulse extension circuit 132, which consists of a resistor 134 connected to the input D of the flip-flop 124 and a capacitor 136 connecting the resistor 134 to earth 138 .

 The flip-flop 20 is connected by its input Q to an AND gate 140 which applies its output to the input of an NI gate 142.

The AND gate 140 is connected by its other input to the Q output of the flip-flop 22. The NI gate 142 is connected by its second input to the Q output of the monostable multivibrator 128. The output of the NI gate 142 is applied to the inputs of repositioning of flip-flops 20 and 22. The output Q of flip-flop 20 is also connected to the addition circuit 34 and, from there, to the integrator 36.

The addition circuit 34 also adds signals from the outputs Q of the flip-flops 22 and 124.

 The flip-flop 126 delivers an output signal Q to a repositioning suppression device and group rejection 144 which is constituted by a capacitor 146 connected to the repositioning input of flip-flop 126 and, by a resistor 148, at the output Flip-flop 22.

 Referring now to Figures 6 and 7, in relation with which we will explain in terms of time domain diagram the operation of the detector according to the invention. Since the operation of the detector for which the input frequency V is ahead of the reference frequency R by an amount less than 261t is substantially identical to that of the conventional detector, we will focus The discussion on the area for which the phase shift is approaching of 2tri.

 When the phase shift approaches #, the coefficient of use of the output signal Q of the flip-flop 120, as represented by the pulse 114, approaches 100;: (pieine width) and, conversely, the output signal Q 'approaches 0 % (zero width).

This causes the output of the OR gate with negative inputs 130, via the pulse extension circuit 132, to keep the input D of the flip-flop 124 on level "1" until the next previous edge of the input signal V has changed state flip-flop 124. When flip-flop 124 changes state, the output signal goes to level "1". Simultaneously, the output signal Q 'of flip-flop 124 goes to level "0", so that the negative OR gate 130 remains on level "1" and maintains level "1" on input D of flip-flop 124 .

 Thus, at point 2>, the output signal Q of the flip-flop 124 is being delivered to the addition circuit 34, where it is added with the output signal Q of the flip-flop 20.

 Simultaneously, the output signal Q of the flip-flop 124 is supplied to the clock input of the monostable multivibrator 128.

The transition of flip-flop 124 causes the state of the monostable multivibrator 128 to change, which leads to the production of an output pulse which, via the NI gate 142, reposition flip-flops 20 and 22.

 When the flip-flop 20 has been repositioned, the output signal Q goes to level "0", so that its contribution to the addition circuit 34 is zero. When the phase shift increases beyond 21Ç, the pulse width of the output signal Q of the flip-flop 20 increases and is added to the normal output signal of the output Q of the flip-flop 124.

 When the phase shift increases from 2 + to 4f, and to which 8, the output of flip-flop 124 remains on level "1" and the effect of flip-flop 20 superimposes the effect of a conventional detector on that of the invention.

 So far, the relationship has been described for the case where the input signal V is constantly increasing relative to the reference signal R. When the phase shift decreases so as to bring the input signal V closer to the signal with reference R, the operation is slightly different. When the phase shift goes from more than 2t to less than 21t (FIG. 5), the coefficient of use of the pulses of the output signal Q of the flip-flop 20 decreases up to the coefficient of use of O%; and the pulses coming from the output Q of the flip-flop 22 see their coefficients of use increase. When a predetermined width of pulse (coefficient of use) is reached, in the manner established by the capacitor 146, this allows that the repositioning signal applied to flip-flop 126 is sufficiently eliminated with regard to the input signal V applied to the clock input of flip-flop 126 so that the output Q of flip-flop 126 goes to level "1" .

 When the Q output of flip-flop 126 is at level "1", output Q 'goes to level "0", which has the effect of repositioning flip-flop 124 and prepositioning flip-flop 20. Repositioning of flip-flop 124 does switch to "O" its output Q and change to "1" the output of flip-flop 20. At the same time, after the time constant RC of the repositioning suppression circuit and group rejection 144, flip-flop 126 changes state again and this causes output Q to go to level "0". Then, the phase and / or frequency detector 12 operates in the same way as the conventional detector.

In the description, the sole preferred embodiment of the invention has been presented and described, but, as previously noted, it should be understood that the invention can be used in various other combinations and environments and is able to undergo modifications or variants within the above-mentioned conceptual limits. For example, it is possible to cascade additional flip-flops so as to produce an increased interval by doubling the characteristic above the zero level 100 also in the negative direction. Furthermore, as is readily apparent to those skilled in the art, it would be possible to add additional stages when necessary to further increase the interval using an approach analogous to that presently described:
Of course, those skilled in the art will be able to imagine, from the circuit whose description has just been given by way of illustration only and in no way limitative, various variants and modifications not departing from the scope of the 'invention.

Claims (4)

1. Phase and / or digital frequency detector circuit intended to determine phase and frequency differences between an input signal (V) and a reference signal (R), characterized in that it comprises:  means for receiving the input and reference signals;  means (20, 22) serving to produce, in a proposable manner, square waves whose utilization coefficient corresponds to the phase and frequency difference between the input and reference signals, the utilization coefficient repeating with each cycle of said phase and frequency difference; and  means responding to a predetermined coefficient of use by producing an output signal representative of the latter and by repositioning said means for producing square waves. 2. Circuit according to claim 1, characterized in that it comprises means (36) for integrating said square waves in order to produce a sawtooth whose shape corresponds to the coefficient of use of said square waves, and means (34) serving to add the output signal of said means responding to a predetermined coefficient of use constant at the peak amplitude of said sawtooth before the repositioning of said means for producing square waves. 3. Circuit according to claim 1, characterized in that it comprises additional means responding to an additional predetermined coefficient of use by producing an additional output signal representative thereof and by repositioning said means for producing waves square, and additional means making it possible to add an output signal of said additional means responding to a constant additional predetermined coefficient of use at the peak amplitude of an additional sawtooth before the repositioning of said additional means of production square waves 4. A circuit according to claim 2 or 3, characterized in that said means serving to integrate said square waves comprise means making it possible to produce a positive sawtooth for the input signal being in advance of the reference signal and a a negative sawtooth for the input signal lagging behind the reference signal, and said means responding to said predetermined coefficient of use include means for adding constant output signals for the early and late signals.