FR2529733A1 - DEVICE FOR FREQUENTLY SERVICING A CLOCK ON AN OUTER SIGNAL WITH HIGH AVERAGE FREQUENCY BUT HAVING IMPORTANT GIGE - Google Patents

Abstract

THE PRESENT INVENTION CONCERNS A FREQUENCY CONTROL SYSTEM OF A CLOCK ON A VERY PRECISE MEDIUM FREQUENCY EXTERNAL SIGNAL BUT INCLUDING A SIGNIFICANT JITTER. THE LOCKER SYSTEM CONSISTS OF AN ANALOGUE PHASE LOOP AND A DIGITAL FREQUENCY LOOP. THE PHASE LOOP INCLUDES A CPH PHASE COMPARATOR AND AN F FILTER AND THE FREQUENCY LOOP INCLUDES A CF FREQUENCY COMPARATOR AND A P PORT THESE TWO LOOPS CONTROL AN OSCILLATOR CONTROLLED IN OCT VOLTAGE VIA A DEVICE. ANA SWITCH WITH AN ANALOGUE INPUT AND A DIGITAL INPUT. THIS SWITCHING DEVICE INCLUDES AN EC SAMPLER-ENCODER, A CD COUNTER-DECOUNTER, A RE REGISTER AND A DIGITAL ANALOGUE CONVERTER CNA. THE COUNTER-DOWN-COUNTER IS INITIALIZED BY THE PHASE LOOP AND ITS COUNTING AND DOWN-COUNTING INPUTS CONSTITUTE THE SWITCH CIRCUIT INPUT ASSOCIATED WITH THE FREQUENCY LOOP. THE PRESENT INVENTION APPLIES TO CLOCKS OF TELEPHONE CENTERS.

Description

The present invention relates to n servocontrol device

  This type of device is particularly useful in digital telephone exchanges of the more commonly used Coded Pulse Modulation (KIC) type.

  nally known as the more general term central time.

  In telephone exchanges of this type, a central clock is used, which can be synchronized by a clock signal from another central office and which makes it possible to know the origin of the different samples received from this other central unit to guard against failures. , this central clock is duplicated This central clock is mainly composed of a controlled oscillator OCT, controlled by a quartz, which can be enslaved on the external clock extracted from a channel MIC or a reference oscillator chosen among three

  external clock signal from another central office generally

  significant jitter resulting from all the electronic interactions

  tromagnetic line with the medium traversed.

  In some equipment, the servo-control of the oscillator is done in frequency as follows. The input signal on which

  must be enslaved the clock is counted, as well as the signal of the opscil-

  OCT Controlled Laminator The result of the counters, which rotate permanently, is read regularly by a calculator of this central unit, via an interface. The difference in the results is compared.

  by the calculator unlike at the time of the previous reading.

  If the difference has increased, is the oscillator controlled OCT is-

  too slow and if the difference has decreased, it is that the controlled oscillator is too fast The calculator then corrects the frequency of this oscillator by changing the contents of a register which is connected to the control input of the oscillator The frequency-controlled loop being a very slow loop, the short-term stability of the clock signals will be that of the oscillator of the hundredth and non-octane clock. the reference oscillator It will be convenient to use a controlled oscillator of very high stability. When the central clock is not to be slaved to an external signal, the loop can

then simply be open.

  The main disadvantages of such a central clock are as follows. The frequency-controlled loop controlled by

-29,733

  a calculator is too slow to compensate for the

  the oscillator, due to temperature fluctuations for example.

  The central clock is comuinded by a calculator which itself requires

  site a clock to operate and conmme in the distribution system

  bution, a single clock distributes its signal to both branches, there can be problems difficult to solve in case of failure If the computer used for the control of the clock is a microprocessor used to all the general tasks of the equipment centra 7 iss , the control of the clock could be disturbed by the processing of another task (software errors) Moreover, the design of such a central clock, both on the material level (large number of covers) and on the software plan, is too complicated and therefore too expensive, especially in the case of small central offices, and more

  unreliable in the case of large central.

  It would therefore be interesting to have an autonomous central clock module that is not dependent on a microprocessor and external software. A purely automatic operation communicating with the processor only for slow tasks, such as the processing of alarms, would therefore be necessary. desirable, however, if it is physically easy to

  phase locked loop, it is much more difficult to

  it is absolutely necessary to make the clock signal independent of variations

phase of the external signal.

  A hardware design of a frequency locked loop has already been described (French Patent Application No. 80 07674

  lodged on 4 April 1980 by the plaintiff and entitled: "Loop

  frequency locked logic "), but it was in fact a phase-locked loop capable of compensating for phase jumps due to the operation of the selectors and which could not function

  correctly in the presence of too much phase noise.

  A true frequency loop can only be achieved using meters that measure the frequency; it is necessarily a slow loop requiring a very stable oscillator.

  can simply make the circuit simply by using a comparison

  numerical meter that compares the contents of meters to

  which acts directly on the control of the oscillator OCT.

  Indeed, in this case, we can verify that the looping of the loop

  could require dozens of hours.

  Thus, the object of the present invention is therefore a device

  rapid coupling of a clock, constituted for example by an oscillator

  voltage controlled transmitter, on an external reference signal having a very precise average frequency but may have a significant jitter and any phase compared to that of this clock. According to the invention, the attachment of this clock begins with a phase loop comprising a phase comparator receiving at its first input the reference signal followed by a

  low-pass filter, then by a switching circuit which controls the oscillator

  voltage controlled terminal, and closing on the second input of the phase detector After detection of the locking of this phase loop by a latching detector circuit, the phase loop is disconnected at the switching circuit and a loop of

  frequency is connected in its place.

  The invention will be better understood and other features

  will appear with the following description and accompanying drawings

  o: Figure 1 is a block diagram according to the present invention; Figure 2 shows the phase loop and the system for detecting its attachment; FIG. 3 represents the frequency comparator of the frequency loop according to one of the features of the present invention; Figures 4a and 4b show a timing diagram describing the operation of the phase comparator;

  FIG. 5 represents a time diagram describing the function

  frequency comparator; and

  FIG. 6 represents a timing diagram describing the function

of the frequency loop.

  FIG. 1 represents a schematic diagram according to the present invention. It comprises a relatively fast latching phase loop, which makes it possible to make a fast first approach to the frequency FS of the output signal S, provided by the OCT output oscillator. on the frequency FE of the reference signal E and performs a first phasing of these two signals, and a slow-coupling frequency loop with variable time constant with the frequency difference FE Fs, which acts after the loop of phase and which makes it possible to free the clock signal obtained from phase fluctuations or

  jitter of the reference clock signal.

  The phase loop comprises a phase comparator C 4 receiving on its input denoted E the external signal or input signal E serving as reference, and on its input denoted AS the output signal S of the phase loop provided by an oscillator controlled voltage and controlled by a quartz OCT This comparator provides a low-pass filter F a measurement of the phase difference E AS between the reference signal E and the output signal S of the loop After integration by the filter F, this analogical information supplied could be used to control the oscillator controlled in voltage OCT. In order to be able to introduce a digital frequency loop which can also control this controlled oscillator, one interposes in this phase loop, after the low-pass filter F, an ANA switching circuit attacking the control input of the output oscillator This switching circuit

  comprises an EC sampler-encoder receiving, from the filter F, an analog signal

  and providing a digitized signal to a synchronous counting and asynchronous display countdown counter When the system is in configuration

  phase loop, the up / down function is inhibited and the function circuit

  It transfers the binary elements present on its

  input after each receipt of a pulse on its "load" display input.

  These bits are transmitted to a buffer register RE

  then to a DAC digital-to-analog converter that provides information

  analog input to the control input of the output oscillator.

  It is the control circuit CP which supplies the sampler-encoder EC with its sampling frequency in the form of a signal of period T 1,

  noted T 1 This signal is only transmitted in phase loop configuration.

  During this operating phase, this clock signal of period T 1

  is also transmitted to the display input load "of the counter-

  upcounter This control circuit CP also provides the register RE a clock signal of period T 1 when the system is in phase loop configuration, but in frequency loop configuration, it is a clock signal of greater period TO which is transmitted to the clock input of this register and which controls the load of this register These two types of clock signals are obtained from a first clock signal of period T 1 and a second clock signal of period TO both provided by an auxiliary clock H and generated from the output signal S of the controlled oscillator OCT All these clock signals of the same period will bear the same reference, T 1 or TO, without distinction of their relative phases The first period T 1 provided is relatively small, of the order of ten times that of the signal supplied by the controlled oscillator, while the second period To supplied is much larger, of the order of 10 times that of this osci This control circuit CP is itself controlled by a lock detector DV of this phase loop which receives from the phase comparator C information on the state of this phase loop. After detection of this lock, it is this circuit that makes the decision "phase loop configuration" or "frequency loop configuration" Its output signal is not only supplied to the driver circuit, which then provides the desired clock signals to the various circuits making up the switch circuit, but is also transmitted to the gate P controlling the transfer of counting and counting signals provided

  by the frequency comparator and intended to be received, in accordance with the

  frequency loop, by the corresponding inputs of the counter-

down counter.

  The frequency loop comprises a digital frequency comparator Cf receiving on its input denoted FE the external signal or input signal E taken as frequency reference and, on its input denoted Fs, the output signal S supplied by the controlled oscillator in

  OCT voltage This comparator receives from the other hand

  the second clock signal of period T O It is during a number, variable over time, of these clock periods T O that will be carried out the respective counting of the number of periods of

  two input signals, then the comparison of these numbers.

  The frequency generator supplies to a gate P, controlled by the lock detector DV, a pair of signals each intended, after they have passed this gate, respectively to the counting and counting inputs of the up-down counter CD. upstream, the rest of this frequency loop is common with the phase loop: there is the RE register followed by the DAC digital-to-analog converter

  supplying its control signal to the OCT output oscillator.

  The control of the output oscillator is therefore performed by the

  ANA switching circuit The latter comprises two inputs, an analog input

  logic constituted by the input of the sampler-encoder and associated with the phase loop, and a digital input constituted by the counting and down counting inputs of the up-down counter and associated with the frequency loop. is ordered first from

  the phase loop then by the digital frequency loop.

  FIG. 2 represents the detail of the phase loop as well as

  possible realization of a DV locking detector.

  The phase converter shown is the one described in the French patent application No. 78 30542 filed October 27, 1978 by the Applicant and entitled "Digital Phase Comparator" It provides, on the output com Dlémentée of the flip-flop BI, a pulse up durge proportional to the phase difference of the two input signals if the input signal from the output oscillator is delayed with respect to the reference signal and, on the output of the flip-flop B 2, a duration pulse dw proportional to this phase difference in the opposite case The signals up and dw provided are represented in FIGS. 4a and 4b, the input signal E being taken as a phase reference. In FIG. 4a, the output signal S is late for this input signal In FIG. 4 b, the output signal S is in advance on this input signal. This phase comparator is followed by a filter F comprising a circuit known as "charge pump". "whose entrances These outputs are connected to the outputs of the phase comparator C +. This diode circuit is followed by a

  threshold integrator using an operational amplifier.

  If it is the pulses up which are present at the output of the phase comparator Cf, it will appear at the output of this integrator an output voltage which will increase, at each appearance of these pulses, a magnitude approximately proportional to the duration of If these impulses are present at the output of this phase comparator C +, this integrator will have a decay at each occurrence of these pulses. In the context of a phase loop of known type, this integrator would directly control the output oscillator From the introduction of the switching circuit ANA, the analog signal provided by this integrator is first digitized

  then converted back into an analog signal so that at the digital

  sation, it is found identically output to control the output oscillator This scan step is defined by the choice

  the number N of bits provided by the sampler-encoder.

  This is followed by a CD down-counter which also has N data inputs and N outputs which, in phase loop configuration, functions as a register and retransmits at its output the binary information present on its input. It is followed by the register of

  storage RE at N data inputs and N outputs then by converting

CNA digital / analog weaver.

  During the locking of the phase loop, the frequency of the output oscillator is prepositioned with respect to the frequency FE of the reference signal E received at the input of the loop. also to a pre-loading of the register RE and especially of the up-down counter CD to a value approaching that necessary to obtain the identity of the input and output frequencies of the loop This locking or preloading being performed, it is necessary to detect it to find out if we can

  toggle the system into a frequency loop configuration.

  A simple embodiment of a DV lock detector system is provided in FIG. 2. It comprises, at the input, an AND gate receiving from the phase detector the up signal and the complement dw of the signal d 1 represented in FIGS. a and 4 b This AND gate is followed by an integrator RC and by a voltage comparator CO, receiving a reference voltage on its other input, then by an inverter whose output is connected to the storage input S of a flip-flop B 3 of the RS type, the input R of this flip-flop B 3 being driven by the output of an AND gate P 5 with two inputs, an input of

  control and an initialization input including a timer.

  As soon as the duration of the slot, up or dw, is lower than a certain value, that is to say as soon as the comparator detects that the signal supplied by the integrator RC has exceeded a certain value, it is decided that the loop The detector then provides a logic level I on its output and the RS flip-flop will receive a logical level O on its input S. In phase loop configuration, the EC sampler-encoder, the CD up-down counter and the register R are driven by a signal

  megahertz high frequency clock (T 1) in configuration.

  frequency loop, the EC sampler-encoder is useless and will no longer receive clock signals; on the other hand, the register will have to be controlled by clock signals with a much lower frequency, of the order of the hertz or the tenth of hertz (T 0) It is the pilot circuit CP which will carry out this management of the signals of clock, which it receives from the auxiliary clock H, from the binary signal received from the output Q of the flip-flop B 3 of the lock detector A possible embodiment of this pilot circuit CP is represented in FIG. control unit which controls the AND gate 5, via the inverter 16, the AND gate P 6, via s of the inverter I 8, and the AND gate P 7 in a direct way the AND gate P 5 receives the signal T and retransmits it, via the inverter I 7, to the sampler-encoder EC, and directly to the up-down counter CD and to the input of the AND gate P 6 La AND gate P 7 receives the signal T and transmits it to the input of the O

  OR gate P 8 This OR gate P 8 receives the outputs of AND gates P 6 and P 7.

  Its output is transmitted directly to the clock input C of the register R. After Rs detection of the locking of the phase loop, it is necessary to switch to frequency loop configuration The appearance of the logic 1 at the output of the detector of locking DV controls the unlocking of the two doors AND P 3 and P 4 of the door P These then become transparent and transmit respectively on the

  counting and counting inputs "Comp" and "Dec" of the counter-

  CD down counter pulses provided by generators G 1 and G 2

  respectively, as will be seen with reference to Figure 3.

  The frequency comparator CF represented in FIG. 3 receives the reference signal E at the frequency FE and the loop output signal, supplied by the internal clock OCT, at the frequency FS II comprises a first counter CFE with m bits. receiving on its clock input the reference signal at the frequency FE and a second counter CFS with m bits receiving on its clock input the loop output signal at the frequency FS at the end of each reference period T of the signal supplied by the auxiliary clock, the contents of these counters are transferred respectively into the RFE and RFS registers each controlled by the output of a flip-flop of type D, D 3 and D 4 respectively. These flip-flops receive on their input D the signal to the reference period T 0, associated with this frequency loop, and on their other input the output of an inverter, I 3 and I 4 respectively, receiving the first the signal at the frequency F E and the second the signal at the frequency FS The m bits provided by each of these registers are transmitted to a subtractor ST This subtractor supplies the m bits of the result to a first comparator C receiving on the other hand on its first input A in addition to two, the value -4, and to a second comparator C +, on the other hand receiving on + iime its second input B, in addition to two, the value + 4 The mn bit element or binary element of sign S is also transmitted, via an inverter I 5, to a NAND gate P 2 and, directly, to a NAND gate P 1, if S = 0, this gate P 2 is transparent and the door locked door; and conversely if S = lo A pulse generator Gi associated with the gate P1 and a pulse generator G 2 associated with the gate P 2 transmit, every TO O seconds, a

  impulse to the counting or down counting inputs of the

  down counter if their order entry, receiving the outputs of the

  AND gates P1 and P2, is at logic level 1.

  An AND gate PS detects whether one or the other of the outputs of the NAND gate P II or P 2 is at logical level 0 Its output is applied to the inputs D of the flip-flops D 1 and D 2 which receive on their input D clock C, via an inverter II, I 2, respectively a signal at the frequency FE and a signal at the frequency FS and which provide the reset pulses R counters CFE and CFS So at the end of each reference period TO, if one of the doors P1 or P2 has as output a logic level 0, the generator G 1 or the generator G 2

  will transmit to the counting or down counting input of the

  counting down a pulse that will increment and decrement the counter-

down counter of a binary unit.

  The operation of this frequency loop can be represented diagrammatically by the time diagrams represented in FIGS. 5 and 6. The diagram of FIG. 5 represents the variation over time of the difference n E n S of the contents of the counters CFE and CFS, and the FIG. 6 shows the frequency of the signal provided by the OCT output oscillator, the reference frequency FE being taken

  origin and the chosen unit being the same reference frequency.

FE.

  At the instant t = 0 where one goes into a frequency loop configuration, it can be posited that the output frequency of the controlled oscillator is written F 50 = FE (l + k) (1) At a time t between O and T 0, the content of the counter CFE is written n E = F Et and the content of the counter CFS is written n S = F So O t Taking into account equation (1), the difference n E n S of the contents of these two counters is written n E n S n Ek At the instant t = To, the register RFE will be loaded with the contents, at this moment, of the counter CFE and will thus contain the value n'El = FET O (2) and the RFS register will load with the contents, at this moment, of the counter-CFS and will therefore contain the value n's 1 = Fso T (3) Of the three relations (1), (2), (3 ), one can extract the expression of the difference n'El n'si = -n'Elk contained in the subtractor ST to

the instant t = TO.

  In FIG. 5, is the variation in time of the difference ns ns of content of the counters for the case where the frequency FS is greater than the frequency E E, sci for k> 0, for

  the moment t = Tenl this value is here less than -4 and the comparison

  When the binary sign S is equal to 1, the gate P z will transmit to the generator G 1 a logical l and the latter will then search, at time t = To, an impulse to the countdown input Dec of the countdown-counter CD The contents of the counter-countdown will then be decremented by one binary unit, which will be

  will affect the content of the PE register and the output of the conver-

  DAC digital / analog weaver The frequency provided by the output oscillator will decrease by one unit which will be noted at FE.

  the instant t = T 0, the output frequency will be equal to FS = FE (l + k-e).

  The slope of the graph n E n S which was OE k will therefore grow by a unit n E '' lu TO and will be equal to TO (ka) If at time t = 2 T 0, the value n 'E 2 n'52 = n'E 2 (ka) is still less than four, the FS frequency of the output oscillator will be further decremented by one and we will have F 52 = F (l + k-2 a) A Whenever one or the other of the outputs of the 52 Er gates P1 or P2 passes to logic level I and the output of the counter is decremented or incremented by one unit, the OR gate P 5 provides on the inputs D The DI and D 2 flip-flops are logic I and the CFE and CFS counters are reset as soon as these flip-flops receive a clock signal through the inverters Il and I 2 Si, respectively, at the end of a time. TO after this reset, the content n E n S of the subtracter ST is smaller in absolute value than the value chosen as the threshold, 4 in the case of FIG. 3, no pulse, no reset or increment mentation or decrement is supplied by the pulse generators GI and G 2 and the count continues to perform It can thus continue for several periods T O without

  there is a reset This number of periods TO O without reinitiali-

  Moreover, the frequency will be increased as the frequency FS supplied by the output oscillator OCT approaches the reference frequency FE. In FIG. 6, the different values assumed by the output frequency F have been reported. 50, FSI, E 52 Frequency hopping is always FE but it's all one and then two

then three periods T 0.

he

  In fact, this description is very schematic and does not

  orders of magnitude of the input variables are not taken into account.

  phase loop, the reference frequency FE and the output frequency of the loop Fs are already very close and it will be necessary to wait a large number of periods for the difference in the number of crossings to be significant Since this number is in the order of 10, it is not possible to use counters that can count such a large number of pulses. M = 4 binary counters, for example, which will be rotated and which, for example, will be selected. each turn will integrate the new phase difference At the end of a TO time sufficiently large but less than the smallest half-beat period T Bmin of the phenomenon, the difference of the contents of these two counters will be sampled. This sampling will be carried out by sending on the inputs D of the flip-flops D 3 and D 4 a pulse having a period of TO, these two flip-flops receiving on the other hand, on their clock input C and respectively through the inverters I 3 and I 4, the reference signals FE and the output of the loop F $ The registers RFE and RFS will then be loaded at the value n'E and y S respectively If the difference is not significant E n's after of this TO time, the CFE and CFS counters will be allowed to run for 2 T 0, 3 TO p To O until this difference n 'n'S is significant, i.e.

  E sinfctvcetà to say above 4 This threshold of 4 results from

  the error made on the counting of the values n E and n S known to 1 close.

  The error made on the difference n E nu is therefore 2 and it will therefore be necessary to choose a threshold at least equal to 3 4 seems a good choice For a number m of binary elements, a binary element of sign and n 1 bits of value, at the output of the subtractor, the difference does not need to be between 4 and 2 ml or

  between -4 and -2 m-1 so that a change of frequency can be decided.

  We will choose a value of m at least equal to 4.

  To locate orders of magnitude, with a truncated frequency elece command giving a relative range of variation of

LF -7

  frequency 107 and an EC sampler-encoder at N = 10 elements

F -10

  binary, we obtain a relative incrementation a = 10, the order of magnitude of the phase noise of the controlled oscillator OCT used The frequency provided by this oscillator is of the order of eight megahertz For this range of relative variation of the output frequency, the largest value kmax of the magnitude k is of the order of kmax = 1000 a and is coded on N = 10 bits For such a difference, the maximum latching time is of the order of ten o'clock

(about three hours for k 10 a).

  Although the present invention has been described in the context of a particular embodiment, it is clear that it is not limited to the said example and that it is capable of modifications or modifications.

  variants without leaving his domain.

Claims (4)

  1 device for frequency servocontrol of a clock on an external signal, this clock being constituted by a voltage controlled oscillator (OCT), this device allowing the fast hooking of the output signal (S) of this oscillator on a signal external reference unit (E ') of medium frequency which is very precise, but has a large jitter and of any phase relative to that of this clock, characterized in that the attachment of this clock starts with a phase loop comprising a phase comparator (C +) receiving on its first input the reference signal (E) followed by a low-pass filter (F) and then by a switching circuit (ANA) which uses the voltage-controlled oscillator (OCT) ), and closing on the second input of the phase detector, and in that, after detecting the locking of this phase loop, by a latching detector circuit (DV), the phase loop is disconnected at 5 switch circuit level (ANA) while being replaced instead a frequency loop.   2 Frequency control device according to the   cation 1, characterized in that the frequency loop comprises a digital frequency comparator (Cf), receiving on its first input the external reference signal (E), and a gate (P), as well as the switching circuit ( ANA) and the controlled oscillator (OCT) both being part of the phase loop, and in that this switching circuit (ANA) has an analog input associated with the loop   phase and a digital input associated with the frequency loop.   3 Frequency control device according to one of   Claims I or 2, characterized in that this needle circuit   Ana (ANA) is controlled by a pilot circuit (CP) receiving from an auxiliary clock (H) two types of clock signals, a first of period (T 1) of short duration associated with the operation in a phase loop and the second period (To) of greater duration associated with the frequency loop operation, this pilot circuit (CP) being controlled by the locking detector circuit (DV), which also controls the door   double (P) of the frequency loop, this latch detector circuit   lage (DV) emitting, after detection of the locking of the phase loop, a signal allowing the pilot circuit to inactivate the input   switching circuit (ANA) and making the gate (P) transparent   annuity. 4 Device for acceleration of frequency according to one   any of claims I 3, characterized in that the circuit   switching system (ANA) comprises a (chantilo) neurodecoder (EC), receiving an analog signal from the filter (F) of the phase plug, followed by a meter counter (CD) whose two inputs, c 1 the counting and that of decompression receive each one a digital signal of the door (P) of the frequency loop, this counter-cumounter having its   output connected to the input of a re-ISter (RE) followed by a cover   digital / analogue weaver (DAC) whose output is the output 0 of this switching circuit ANA).   Frequency control device according to one   any of claims 1 to 4, characterized in that the comparison   frequency converter (Cf) comprises a first counter (CFE) receiving on sc input the reference signal (E) and a second counter (CFS) receiving on its input the signal (S) supplied by the controlled oscillator (OCT), each of these counters (CFE, CFS) being connected to a register (RFE, PRS), each of these registers being connected to an input of a subtracter (ST), this subtractor providing at each end of the   second period (T 0) provided by the auxiliary clock (H) an exchange   (n E n) of the beat frequency between the reference signal   (E) and the output signal (S) to a first and a second compa-   (C, C +), this first comparator (C) receiving on its other input (A) a chosen binary value less than -2 and this second comparator (C) receiving on its other input (B +) a binary value chosen greater than + 2, the output of the first comparator (C) being connected to the input of a first NAND gate (PI) receiving on the other hand, on its other input of the subtracter (ST), the sign bit (s) ) and the output of the second comparator (C +) being connected to a second NAND gate (P 2) receiving on the other hand on its other input, the subtracter (ST), the sign bit (s) complimented by an inverter (15), the outputs of the doors being each supplied to the control input of a generator (G 1, G 2), the first generator (GI) sending on a double gate input (P) a down-counting pulse at the time of receipt of a clock signal (To) if its control input is at logic level O and the second generator (G 2) approx on the other input of the double gate (P) a counting pulse at the time of receipt of a clock signal (T 0) if its control input is at logic level O and in that a AND gate (PS) receiving the outputs of the NAND gates (P 1 i and P 2) provides via inverters (II, I 2) and flip-flops (D 1, D 2) a reset information of counters (CFE, CFS).