FR2507799A1 - MICROCOMPUTER - Google Patents

Abstract

A. TABLETOP MICRO-COMPUTER. B. MICRO-COMPUTER CONTAINING A CENTRAL UNIT CPU 1, A ROM DEAD MEMORY 2, A RAM RAM 3 AND A SECOND RAM RAM 12 CONNECTED TO A DISPLAY DEVICE 13 ON CATHODIC TUBE 23, THE LOWER ADDRESS INPUTS AND HIGHER BETWEEN THE CENTRAL UNIT CPU 1 AND THE SECOND RAM 12 RAM BEING INVERTED. C. THE INVENTION CONCERNS COMPUTING.

Description

i

" Microcomputer ".

  The present invention relates to a micro-

  computer and in particular a microcomputer that includes a CRT display. Recently, tablet PCs are

  are developed to a very large extent.

  computers generally use an 8-bit CPU with 16-bit addresses so that the CPU can directly access a memory zone at 64 K positions, that is, between hexadecimal addresses OOOOH up to FFFFH, each position containing 8-bit data (i.e., one byte) Thus in a home computer of the above type that uses an 8-bit microprocessor, one can have 32K of positions in the memory area, for example as a read-only memory (ROM) area for registering a control program and / or a BASIC interpreter, the other address or memory parts among the 32 K positions that can be used as RAM areas (RAM) However when using a microcomputer

  with a cathode tube display or control device

  For example, for a video or graphics display of 640 x 400 points, a bit being allocated to a point requires a random access memory RAM, video of 32 K bytes or less It is necessary to have a RAM RAM area. As a result, there are few or no RAM RAM areas for user programming.

  memory area and to avoid such disadvantages, we have

  provided to provide several sets of memories that are selectively connected to the CPU microprocessor under the control of the program of the system However, as the switching of different sets of memories must be done according to the program, this switching is complex and the speed

  In addition, the establishment of the program is

  Such a program is a relatively complex operation since it is necessary to do the work with

  and extreme care to avoid mistakes.

  It is an object of the present invention to provide a microcomputer overcoming the disadvantages of the prior art solutions, including a tabletop microcomputer for combination with a CRT display, and having a video buffer memory area for the computer. cathode display which is integrated into an input / output zone

output of the microcomputer.

  The invention also aims to create a

  microcomputer in which the address area directly

  accessible by the user for programming

  not be diminished, by assigning a memory area-

  video buffer to an input / output address area of the micro-

  computer or a video buffer area for displaying

  cathodic chase controlled by the entry / exit instructions

CPU microprocessor.

  For this purpose, the invention relates to a micro-

  computer which includes a central processing means

  with N-bit data and information

  of m-bit addresses, a bus, a read-only memory for recording

  register a control program and which is connected to the central processing unit by the bus, a first RAM as a work area connected to the central processing means

  by the bus, a second RAM, separate for the display

  video display connected to the central processing by bus

  and intended to be accessed by input / output instructions

of the central processing means.

  The present invention will be described in more detail with the aid of the accompanying drawings, in which: FIGS. 1A and 1B are diagrams

  explain the operation of the central processing unit

  the microcomputer according to the invention.

  FIG. 2 is a block diagram of a micro-

  computer corresponding to an embodiment of the invention.

vention.

  FIGS. 3A and 3B are diagrams for explaining the assignments of the memory addresses of the

microcomputer according to Figure 2.

  FIGS. 4A-4D are diagrams for

  explain the connection between the central processing unit

  and the video buffer according to the invention.

  DETAILED DESCRIPTION OF A PREFERENTIAL EMBODIMENT:

  According to the drawings, and in particular FIG. 2, a microcomputer according to one embodiment of the invention comprises a central processing unit (CPU) 1 which can for example be Zilog's Z 8 OA microprocessor (brand) or the microprocessors NSC-800 from National Semiconductor

  (brand) Hereinafter the microprocessor CPU 1 will be the micro-

  processor Z 8 QA which will serve to illustrate the invention.

  The microcomputer according to the invention also comprises a ROM 2 which stores a control program and a BASIC interpreter program, and which contains for example 32 K 8-bit address positions ranging from the address OOOOH to the address 7 FFFH as shown in Figure 3 A The microcomputer also includes a RAM RAM 3 which allows registration of the user program

  and which is also a working area for the middle

  processor 1 As shown in FIG. 3B, the

  RAM 3 also contains 32 K address positions.

  its 8 bits from the 8000 H address to the FFFFH address It should be noted that the position numbers

  8-bit addresses are only given as examples.

  ple and the invention is not limited to these particular cases.

  A 4 to 8-bit data bus, an 8-bit lower address bus, SL, and an 8-bit 5-bit address bus

  are connected to the data terminals D 0 -D 7 at the address terminals

  its A 0 -A 7 and the respective address terminals A 8-A 15 of the microprocessor CPU 1 of the read-only memory ROM 2 and the

  RAM RAM 3 for the exchange of information.

  To order the reading of the information from

  the ROM 2 and RAM 3 RAM, the micro-

  CPU 1 provides a memory request signal MREQ and / or a read signal RD at the respective inputs of the OR gate 6 to derive a memory signal MEMR which is supplied to the respective reading terminals R of each

  ROM 2 and RAM 3 memory. In the same way, for

  to kill an enrollment operation in the RAM 3, a signal WR is generated by the microprocessor CPU 1 and a

  registration signal WR and / or the request signal for

  MREQ are provided at the respective inputs of the OR gate 7. This latter circuit gives a MEMW memory registration signal which is supplied to the registration terminal W of the

RAM memory 3.

  In the computer according to the invention as

  shown in FIG. 2, there is a maximum of 256 external I / O (input / output) ports 11 which can be connected to the microprocessor CPU 1, each port being identified by a port number N between OOH and FFH.

  have a number of I / O ports, 11 less than 256, for example

  ple, we can have ports numbered from 80 H to FFH.

  A set of external I / O (input / output) devices such

  that a keyboard 21 and a tape cassette 22 can

  connected to each I / O port 11 with a maximum of

  256 external I / O devices for each port To facilitate

  In order to understand the invention, only one I / O port shown in FIG. 2 will be described hereinafter. The I / O port 11 consists of the DO-D data terminals 7 connected to the data bus 4 and the terminals address A -A 7 connected to the bus

  In the same way, as indi-

  As previously for the ROM 2 and RAM 3, the microprocessor CPU 1 controls the reading and the writing of information by the I / O port 11. Thus, the microprocessor CPU 11 generates an I / O request signal ( input / output) IORQ and the I / O request signal and / or RD read signal are provided at the respective inputs of the OR gate 8 which in turn provides an I / O read signal (input / output)

  IOR at the reading terminal R of port I / o 11 Of the same ma-

  the I / O request signal IORQ and / or the signal of

  WR are provided by the microprocessor CPU 1 to the respective inputs of an OR gate 9 which in turn provides a registration signal I / O, IOW to a registration terminal.

  W port I / O 11 Reading and recording information

  between the I / O port and the microprocessor 1 are

like this.

  By way of example only, it will be described

  after the working instructions of a microprocessor Z 80 A for the exchange of data between an external I / O port, 11 and the CPU 1 microprocessor (and consequently, the RAM 3) It is first noted that the microprocessor Z 80 A has at least A, B, C, D, E, H and L general registers and the transfer of 8-bit data between an external I / O port 11 and one or more of these registers is via the bus of The corresponding address information is transferred by the 16-bit address bus formed from the address bus of greater than 8 bits, 5 H and the address bus smaller than 8 bits, 5 L. use the following I / O instructions: I-1 IN A, n This instruction transfers the 8-bit data of an input port with the reference N (n between

  O and 255) to register A of the CPU microprocessor.

  IA OUT n, A This instruction transfers the 8-bit data from register A of the microprocessor to an output port designated by the port number n It should be noted that with its instructions the 8-bit data of the register A appears on the times on the

  data terminals DO-D 7 and on the address terminals A 8-A 15.

  Under these conditions, the 8-bit address terminals A 0-A 7 receive the address information and indicate the port number N as shown in FIG. 1 A. II-1 IN r, (C) This instruction transfers the data to a port (identified by the port number n) designated by the register pair BC to a register r, the register r being one of the registers A, B, C, D, E, H, L II-A OUT (C), r

  This instruction transfers the data from the re-

  at the port (identified by the port number n) designated by the pair of BC registers In Figure 1B, the data

  corresponding to the register r appears on the data terminals.

  born D-D; the register C contains the information of the AOA address terminals 7 corresponding to the port number N and the

  register B contains the information of the address terminals A 8-

  A 15 corresponding to the I / O device (input / output) connected to the designated port As there are 8 information bits in the C register, a maximum of 256 I / O devices can be connected (i.e. O and 255 devices) on each

port as has been indicated.

  It is clear from the above discussion that the following block transfer instructions are also used in the CPU 1 microprocessor:

III-1 INIR, INDR

  For these instructions, a set of data bytes i.e. blocks of data can be transferred from a port N to the main memory In this case, the pair of registers BC is used to determine the number port (C register) and the number of bytes to be transferred (B register). The data block is transferred to a memory position

  whose address is determined by the pair of HL registers.

  For example, the position of the last address to which the data is to be transferred is stored in the pair of

HL registers.

  Register B is then used as a counter; this register counts down to zero In particular, the value contained in the register B is decremented permanently by one unit and during each decrement of one unit, it

  There is a transfer of a byte from the block When the magnitude

  registered in register B is equal to zero, all bytes

  of the data block were transferred to the remaining I / O port.

dot designated by the C register.

III-2 OTIR, OTDR

  For these instructions, a block of data can be transferred from the main memory to a port I / o designated by the register C. The pair of registers HL and the

  register B are used in the same way as that described in

te above.

  As an example of the instructions above, the following program can be used to perform this transfer:

LD HL, 08 FFH

LD BC, FF 03 H

  OTDR Using this program, the last address of the main memory to which the

  data is loaded into the HL register pair by the

  load truction LD, ie the last address O 8 FFH The port number N is loaded in the register C that is 03 H and the number of bytes to be transferred is loaded in the register B ie FFH The value loaded in the register B is then decremented continuously until this value is equal to zero; during each decrement of one unit, one byte of the data block at the 0800 H 08 FFH addresses of the main memory is

  transferred to the port designated by the port number 03 H

  that the quantity recorded in register B is equal to

  zero, all bytes in the data block are transferred.

  According to one characteristic of the invention, there is provided a random access memory RAM 12, which is distinct as

  buffer used in the display of the results processed

  and, as shown in Figure 3 B, it is assigned 32 K memory addresses corresponding to the addresses OOOOH up to 7 FFFH (example) To facilitate the transfer of

  data between the RAM RAM 12 and the micropro-

  Z 80 A (Figure 2), the lower 8-bit address terminals A 0A 7 of the RAM video memory 12 are connected to the upper address bus 5 H corresponding to the higher 8-bit address terminals. A microprocessor

  CPU 1 of ROM 2 RAM and RAM 3.

  In the same way, the 8-bit address terminals A 8-A 15 of the RAM video memory 12 are connected to the bus

  of lower addresses SL corresponding to the terminals

  its lower, 8-bit A 0-A 7 of the microprocessor CPU 1 of the ROM 2 and the RAM RAM 3 In addition, an I / O read signal, IOR and an I / 0 registration signal IOW from the respective OR gates 8 and 9 are

  supplied to a reading terminal R and to a registration terminal

  W respectively of the video memory RAM 12 to control the read and write operations The data terminals D-D 7 of the video memory RAM 12 are also connected to the data bus 4 To display the contents of the video RAM RAM 12, there is provided a control screen 13 on the 13 connected to the video RAM RAM 12 for sequentially reading the data of the video memory RAM 12 and provided these data to the display device tube

cathodic 23.

  In the microcomputer according to the invention, represented in FIG. 2, ROM memories 2 and live

  RAM 3 are associated with the memory control areas

  microprocessor CPU 1 while the RAM RAM 12 is associated with a zone I / 0 (input / output) of the microprocessor In this way, RAM video RAM

  12 can be addressed by the pair of BC registers of the micro-

  CPU 1 processor in response to the I / O instructions as

  mined previously, for example for instructions II-1

  and II-2 Thus, as a result of this allocation for the

  ROM 2 and RAM 3 and RAM 12, the work area or zone

  programmable memory that can be used in the RAM memory 3 is not

  through the RAM video RAM area, which allows

  the user to have a larger area of pro-

  gram Plus like the RAM video RAM area

  12 can be up to 32 K bytes, we can perform a function

  For example, it is important to note that the instructions or commands provided by the microcomputer CPU 1 to the ROM 2 and RAM 3 memories may be similar to those

  used in a conventional microcomputer and the instruc-

  I / O or commands 1-1, I-2, II-1, II-2, III-1 and III-2 can easily be used in RAM RAM 12 In other words, it is important to to have a separate RAM memory 12 which is accessed by the instructions I / O CPU microprocessor 1 As a result, RAM RAM 12 can be considered as a

  another I / O port or other I / O device.

  It should also be noted that as

  have been examined, the connections between the

  less than 8 bits A-A and the higher address

  The 8-bit A 8-A 15 of the RAM RAM 12 are inverted or are exchanged with respect to those of the CPU 1 microprocessor and the ROM 2 and RAM 3 memories.

  4 A-4 C at least when the micropro-

  The CPU 1 processor is a Z 8 QA microprocessor. Accordingly, the transfer of the blocks of a 256-byte unit can be done between the RAM RAM 3 and the RAM video memory 12 in response to the instructions I / O, III-1 and III-2 For example, the OTDR program above can be used to perform this transfer Under these conditions, the recorded value

  in the register C denotes the video RAM RAM 12.

  With such a program, one can easily transfer directly

  Data RAM 3 RAM to RAM

  RAM 12 video without any buffer or analog device

  As shown in Figure 4D, the addresses below

  8-bit A 0-A 7 of the microprocessor CPU 1 stored in the register C correspond to the respective address positions of the I / O port 11 or the video memory RAM 12 while the I / O instructions I-1, I -2, II-1, II-2, III-1, III-2 can be used in video RAM 12 so

  analogous to a conventional microcomputer.

  It should be noted that in the present invention

  tion, it is useless to first choose a set of

  then access this set The speed of execution of the program is not diminished and it is not necessary

  that the programmer prepares a complex program.

Claims (1)

CLAIMS) Microcomputer with a central processing unit CPU (1) with N-bit data and m-bit addresses, a bus (4), a ROM ROM (2), for recording a control program , this memory being also connected to the central processing unit CPU (1) by the bus (4), a first random access memory RAM (3) as a working area connected to the central processing unit CPU (1) by the bus (4) and a second random access memory RAM (12) for the video display (13, 23), this memory being connected to the central processing unit CPU (1) by the bus, and this memory being intended for be accessed by the I / O (input / output) instructions of the central processing unit. 20) A microcomputer according to claim 1, characterized in that N is equal to eight and m is equal to sixteen. Microcomputer according to Claim 2, characterized in that the central processing unit CPU (1) is the microprocessor Z 80 A. Microcomputer according to Claim 3, characterized in that the bus comprises a bus of addresses and the CPU (1) CPU has terminals, addresses greater than 8 bits (A 8-A 15) and address terminals less than 8 bits (A-A 7) and the second RAM memory (12) has address terminals greater than 8 bits connected to the lower address terminals than 8 bits of the CPU (1) via the bus. 8-bit lower address terminals are connected to the upper 8-bit address terminals of the central processing unit (1) via the address bus. A microcomputer according to claim 4, characterized in that the address bus has an address bus greater than 8 bits (5 H) for connecting the upper address terminals to 8 bits of the central processing unit. a CPU (1) at the address terminals less than 8 bits of the second random access memory RAM (12) and a lower address bus (5 L) at 8 bits for connecting the lower address terminals to 8 bits ( Ao-A 7) of the central processing unit (1) at the address terminals greater than 8 bits of the second random access memory RAM 12.   6) A microcomputer according to claim 1, characterized in that the bus comprises a data bus and the central processing unit (1) has data terminals and the second random access memory RAM (12) comprises data terminals. connected to the data terminals of the unit   CPU (1) through the data bus.   Microcomputer according to claim 1, characterized in that it comprises a display means for   display a video image in response to the video data   stored in the second RAM RAM (12).