FR2504341B1 - Circuit de reproduction de donnees - Google Patents
Circuit de reproduction de donneesInfo
- Publication number
- FR2504341B1 FR2504341B1 FR8206653A FR8206653A FR2504341B1 FR 2504341 B1 FR2504341 B1 FR 2504341B1 FR 8206653 A FR8206653 A FR 8206653A FR 8206653 A FR8206653 A FR 8206653A FR 2504341 B1 FR2504341 B1 FR 2504341B1
- Authority
- FR
- France
- Prior art keywords
- data reproducing
- reproducing circuit
- circuit
- data
- reproducing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
- H04N5/94—Signal drop-out compensation
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Television Signal Processing For Recording (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56059437A JPS57176512A (en) | 1981-04-20 | 1981-04-20 | Data reproducing circuit |
JP56065810A JPS57181419A (en) | 1981-04-30 | 1981-04-30 | Data reproducing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2504341A1 FR2504341A1 (fr) | 1982-10-22 |
FR2504341B1 true FR2504341B1 (fr) | 1987-06-05 |
Family
ID=26400484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8206653A Expired FR2504341B1 (fr) | 1981-04-20 | 1982-04-19 | Circuit de reproduction de donnees |
Country Status (4)
Country | Link |
---|---|
US (1) | US4477842A (fr) |
DE (1) | DE3214370C2 (fr) |
FR (1) | FR2504341B1 (fr) |
GB (1) | GB2101853B (fr) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58205906A (ja) * | 1982-05-26 | 1983-12-01 | Victor Co Of Japan Ltd | メモリ回路への書き込み方式 |
US4667318A (en) * | 1982-10-21 | 1987-05-19 | Victor Company Of Japan, Ltd. | Data producing device in a signal reproducing apparatus |
JPS59112391U (ja) * | 1983-01-17 | 1984-07-28 | 日本ビクター株式会社 | 再生装置におけるアドレスデ−タ伝送装置 |
US4591925A (en) * | 1983-04-06 | 1986-05-27 | Ampex Corporation | Encoded dropout compensator system |
JPS60370A (ja) * | 1983-06-16 | 1985-01-05 | Victor Co Of Japan Ltd | 円盤状情報記録媒体の欠陥検査装置 |
JPS6052960A (ja) * | 1983-09-01 | 1985-03-26 | Sony Corp | デイスク再生装置 |
JPS6083264A (ja) * | 1983-10-14 | 1985-05-11 | Nippon Gakki Seizo Kk | フレ−ム同期したカウンタ回路 |
NL8303567A (nl) * | 1983-10-17 | 1985-05-17 | Philips Nv | Inrichting voor het weergeven van videosignalen. |
US4675749A (en) * | 1984-03-16 | 1987-06-23 | Pioneer Electronic Corporation | Disc player system with digital information demodulation operation |
JPH0634296B2 (ja) * | 1985-05-27 | 1994-05-02 | キヤノン株式会社 | ドロツプアウト検出装置 |
US5019906A (en) * | 1985-10-17 | 1991-05-28 | Ampex Corporation | Time base corrector memory arrangement and memory control |
JPS6329362A (ja) * | 1986-07-22 | 1988-02-08 | Hitachi Ltd | 映像信号再生装置の時間軸変動補正回路 |
JPS63200239A (ja) * | 1987-02-14 | 1988-08-18 | Victor Co Of Japan Ltd | 誤り訂正方式 |
JP3180525B2 (ja) * | 1993-09-20 | 2001-06-25 | 松下電器産業株式会社 | 映像再生装置 |
KR100366309B1 (ko) * | 2000-09-29 | 2002-12-31 | 삼성전자 주식회사 | 디지탈 영상표시기기의 절전회로 |
JP4118536B2 (ja) * | 2001-07-03 | 2008-07-16 | 株式会社東芝 | クロック遅延設定方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3938082A (en) * | 1974-09-19 | 1976-02-10 | General Electric Company | Receiver for bi-polar coded data with bit time interval detection used as the data validation discriminant |
US4037257A (en) * | 1976-02-02 | 1977-07-19 | Xerox Corporation | Data clock separator with missing clock detect |
US4276656A (en) * | 1979-03-19 | 1981-06-30 | Honeywell Information Systems Inc. | Apparatus and method for replacement of a parallel, computer-to-peripheral wire link with a serial optical link |
JPS5639642A (en) * | 1979-09-10 | 1981-04-15 | Hitachi Denshi Ltd | Decoding circuit |
-
1982
- 1982-04-15 US US06/368,247 patent/US4477842A/en not_active Expired - Lifetime
- 1982-04-19 FR FR8206653A patent/FR2504341B1/fr not_active Expired
- 1982-04-20 GB GB08211381A patent/GB2101853B/en not_active Expired
- 1982-04-20 DE DE3214370A patent/DE3214370C2/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2101853A (en) | 1983-01-19 |
GB2101853B (en) | 1985-03-13 |
DE3214370A1 (de) | 1982-10-28 |
FR2504341A1 (fr) | 1982-10-22 |
DE3214370C2 (de) | 1985-07-18 |
US4477842A (en) | 1984-10-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |