FR2497616A1 - Offset dither digital generator - has counter incremented for each repetition of analogue signal to be digitised, with counter output connected to D=A converter - Google Patents

Abstract

The digital dither generator produces a sequence of dither voltages to be combined with an analog input signal before it is digitised by an m-bit quantiser, the dither generator comprising a clock pulse generator for producing a pulse at a repetition rate equal to that of the analog input signal. There is an n-bit unit for converting a digital signal to an analog dither value and an n-bit unit for counting the clock pulses, the outputs of the counter being coupled to the control inputs of the digital-to-analog converter. There is a summer for combining the analog input signal with the analog dither value, the output being coupled to the input of the m-bit quantiser.

Description

 The present invention relates to the field of analog-digital converters and more particularly to an apparatus and a method for improving the precision and resolution, or separating power, of a digital indicator.

 During the process of converting analog signals to digital signals, certain errors are introduced into the digital output signal. Typical sources of errors are the well-known suppression errors, proportionality factor errors, linearity and non-monotonicity errors. Another source of error concerns the quantification process itself.

 Known as a quantization error, this error occurs when a continuous signal is applied to a quantizer. The continuous signal is quantified by compartmentalizing it into discrete ranges. All the analog values which are in a determined range are represented by the same digital code, which corresponds to an analog input value of intermediate nominal range.

 A cutoff point, designated at n, is defined as the analog input voltage at which it is also likely that the digital output code will be either n or n + 1. Therefore, there is an inherent quantization error less significant bit (BMS) in the analog-to-digital conversion process. Previous methods of reducing this error voltage have involved increasing the number of bits in the output code.

 In accordance with the present invention, a digital vibration generator produces a sequence of vibration states. This sequence of vibration states is transformed into analog voltages which are added with an analog input signal before it is transformed into a digital signal by a quantizer. Vibration states have two exceptional characteristics. The first is a bit inversion scheme in which the same sequence of vibration states is used to obtain maximum resolution of the quantizer. The second characteristic resides in the inclusion of a vibration component which is equal to the analog equivalent of an integer number of BMS in order to statistically improve the accuracy of the quantizer.

 Therefore, one of the objects of the present invention is to provide a means for improving the accuracy of a quantizer.

 Another object of the present invention is to provide a means for improving the resolution of a quantizer.

 The invention, with regard to both its organization and the operational method, as well as other advantages and aims which characterize it, will be better understood if reference is made to the description which follows and to the appended drawing, given by way of example. However, it is understood that the embodiment described in no way aims to limit the invention, because it is given only by way of illustration to allow those skilled in the art to fully understand the principles and the mode of application in a specific practical case, which allows modifications to be made without departing from said principles.

 The single Figure of the appended drawing shows a block diagram of a circuit arrangement intended to improve the precision and the resolution of a digital indicator according to the present invention.

 If we now refer to the single Figure of the drawing, we see that the analog signal which must be converted into digital or digital signal is introduced into the system by an input line ioe which applies it to the summing amplifier or adder 50. This input signal is also applied to a generator 10 of clock signals which effectively generates a clock pulse at the end of each repetitive period of the input signal. The output of the clock pulse generator 10 is applied to the clock input (CK) of the counter 30.

 The counter 30 also receives a reset pulse by the input line 20. The reset pulse is applied to the reset input of the 3G counter so as to allow the system to start up. This reset pulse can be caused by a phenomenon external to the numbering or encryption system, for example a circuiting sequence. The counter 30 can for example be a conventional counter with binary output. a classic five-bit counter has only been shown for explanatory purposes. In the circuit shown, the HQ output is that at AU B.NE (least significant bit), while the sort 24 is that of the BPS (most significant bit) of the counter output word.

 The outputs of the counter 30 are connected directly to the data inputs of the digital-analog converter 40 (DAC). This DAC converter 4C can be of any type commercially available, and the number of outputs which it comprises must naturally correspond to the number of bits of the output word of the counter 3C. Therefore, a 5-bit C is shown. The output of this converter C 40 is applied to an input of an adder device 50, the other output of which receives the original analog input signal. The adder device 50 may include an operational amplifier, a resistive network, or similar components.

 The output of the adder amplifier 50 is applied to the input of a waveform indicator or coder 60. The latter can be constituted by any waveform indicator of conventional type, comprising a quantizer , a clock pulse generator and suitable accumulators for precisely accumulating successive samples of the quantized signal. For illustrative purposes only, an 8-bit quantizer was used in the waveform indicator 60.

The latter displays the quantization error mentioned above, ie h BMS. The 8-bit quantizer proposed as a non-limiting example operates at a maximum input voltage of 10 Volts. In such a quantifier, the analog input analog input in BMS of the digital output word is 39.1 millivolts.

The output lines of the counter 30 are connected to the inputs of the CN 40 so that the latter produces output voltages in accordance with the table below.
Counter status DAC output (in millivolts)
00000 0
00001 19.5 - F BMS
00010 9.8 - 1/4 BMS
00011 29.3 - 3/4 BMS
00100 4.9 - 1/8 BMS
00101 24.4 - 5/8 BMS
001io 14.7 - 3/8 BMS
00111 33.6 - 7/8 BMS
01000 78.2 - 2 BMS
01001 97.7 - 2 h BMS
01010 88.0 - 2 1/4 BMS
01011 107.5 - 2 3/4 BMS
01100 83.1 - 2 1/8 BMS
01101 102.6 - 2 5/8 BMS
01110 92.9 - 2 3/8 BMS
01111 111.8 - 2 7/8 BMS
10,000 39.1 - 1 BMS
10001 58.6 - 1 4 BMS
10010 48.9 - 1 1/4 BMS
10011 68.4 - 1 3/4 BMS
10 100 44.0 - 1 1/8 BMS
10101 63.5 - 1 5/8 BMS
10110 53.8 - 1 3/8 BMS
10111 72.7 - 1 7/8 BMS
11000 117.3 - 3 BMS
11001 136.8 - 3 rd BMS
11010 127.1 - 3 1/4 BMS
11011 146.6 - 3 3/4 ssMS
11100 122.2 - 3 1/8 BMS
11101 141.7 - 3 5/8 BMS
11 110 132.0 - 3 3/8 BMS
11111 150.9 - 3 7/8 BMS
After receiving a reset pulse, the counter 30 returns to its initial state (00000). At the end of each repetition period of the continuous analog input signal, a clock pulse is generated by the clock signal generator 10. This clock pulse is applied to the clock input of the binary counter 30 which produces the 32 counter states shown in the table above.

Each repetition of the input signal determines a discrete individual output of the digital-analog converter 40. It can be seen from this table that the output of the DAC converter 40 is caused to pass through 32 vibration states, each of which is gradually added to the input signal before the 8-bit quantization process that takes place in the waveform indicator or coder 60.

 We will understand more clearly the operation of the circuit according to the present invention if we refer to the single Figure of the accompanying drawing during the reading of this description. The counter is reset to zero by any external means (not shown) and its output returns to its initial state (00000). The initial repetition of the analog signal is added to the output of the cNA converter 40, which is zero at this time, and encrypted by the encryptor or waveform indicator 60. Of course, this process should produce a digital output signal based on the resolution and accuracy of the eight-bit quantizer of said waveform indicator or encoder 60.

(D0] , où A désigne la séquence initiale des valeurs analogiques d'entrée et Do la séquence initiale des valeurs de sortie. Au terme de la première répétition du signal analogique d'entrée, le générateur 10 de signaux d'horloge engendre effectivement un signal d'horloge et l'applique au compteur binaire 30.So, we have the expression (A]

(D0], where A denotes the initial sequence of analog input values and D denotes the initial sequence of output values. At the end of the first repetition of the analog input signal, the generator 10 of clock signals effectively generates a clock signal and applies it to the binary counter 30.

The output of the latter increases by one unit to go to 00001. As shown in the table above, the digital-analog converter 40 transforms this counter output into an analog equivalent of h BMS of the quantizer of the circuit. This analog value is added to the analog input signal in adder 50 to form the sequence CA + h 3MS). This sequence is converted into digital values in order to provide the digital sequence [D1]. The FD0i and tD13 sequences can be added to each other to constitute a new D0 + 1 sequence]
The effect produced by the above process is essentially that it doubles the resolution or definition of the eight-bit quantizer. It can be proved, by appropriate mathematical manipulation, that the new sequence tDC + 13 is equal to the digital output produced by a nine-bit quantizer operating on the analog sequence (A + 1/4 BMS. The quantizer now has 512 (29 )
8 instead of 256 (2) effective quantification levels. Therefore, this resolution has been doubled. If this sequence is repeated several times, the output of the quantizer will be equal to the 10-bit quantization of the analog input (A + 3/8 BMSJ. It follows that after a determined number of repetitions (2R) the number of effective quantification levels (Q) will be as follows 2 2 (M + R) (1)
where M = number of bits of the quantizer
R = exponent of the power of two, equal to the number of repetitions.

For example, in a preferred embodiment, the above sequence is repeated eight times to give
Repetitions = 2R
8 = 2R
R = 3
So the number of effective quantification levels is as follows
Q = 2 (M + R)
Q = 2 (8 + 3)
Q = 211
As a result, the original 8-bit quantizer now has the effective resolution of an 11-bit quantizer. Similarly, the quantization error was reduced by 9 BMS from an 8-bit quantizer to
(1 - 2) BMS (2)
The present invention also compensates for errors occurring in the location of each of the cut points in the quantizer.

For example, the first cut point may not occur at exactly + 4 BMS or the differences between cut points may not be equal or change uniformly. The present invention compensates for the above-mentioned vibration sequence by integer multiples of a BMS. This can be seen from Table 1 where, after the first eight repetitions, the next eight repetitions are compensated by two BMS, the eight following are then compensated by 1 BMS and the last eight repetitions are compensated by 3 PMS. Thus, in the preferred embodiment shown in the single Figure of the appended drawing, the location errors of the four adjacent cut-off points are weighed together in the combination of the 32 digital sequences generated by the quantizer. Assuming that the cut point errors are randomly distributed, the effective error will be reduced by a factor equal to the square root of the number of cut points crossed by the compensated sigr.al. Thus, in the example above the errors are reduced by a factor of 2.

 It will be noted in the foregoing description that it has not been overloaded by the inclusion of large amounts of detail and information relating to subjects such as circuit layout, timing, and the like, since such information is well known to those skilled in the art. Consequently, it will be clear to the latter that many changes and modifications can be made to the particular embodiment of the invention which has been described above, without however departing from the basic principles of the invention, taken in its broadest aspect.

Claims (7)

R E V E N D I C A T I O N S 1. Digital vibration generator, intended to generate a sequence of vibration voltages to be combined with an analog input signal before it is transformed into a digital signal by an m-bit quantizer, this generator being characterized in that he understands  a) clock pulse generating means for producing a pulse at a repetition rate equal to that of the analog input signal;  b) n-bit means for converting the digital signal to an analog vibration value;  c) n-bit counter means for counting said clock pulses, the outputs of this counter means being applied to the control inputs of said digital-analog converter means, and  d) summing means for combining the analog input signal with said analog vibration value and the output of which is applied to the input of the m-bit quantizer. 2. An analog-digital converter system characterized in that it comprises  a) m-bit quantizing means for converting an analog input signal to a digital output signal;  b) clock pulse generating means for producing a pulse at a repetition rate equal to that of said analog input signal;  c) n-bit means for converting a digital signal into an analog vibration value;  d) n-bit counter means for counting said clock pulses, the output of which is applied to the control inputs of said digital-analog converter means, and  e) summing means for combining the analog input signal with said analog vibration value, the output of which is applied to the input of said m-bit quantizer. 3. A generator according to either of Claims 1 and 2, characterized in that said n-bit counter means comprises a binary n-bit counter. 4. A generator according to Claim 3, characterized in that the 2 output states of said n-bit binary counter generate a corresponding number of said analog vibration values which are constant at each repetition of said analog input signal. 5. A generator according to Claim 3, characterized in R that after 2 repetitions of the analog input signal, the number Q of effective quantization levels of the m-bit quantizer is equal to 2 (M + R) 6. Generator according to Claim 3, characterized in that the first output state of the n-bit binary counter makes said n-bit digital-analog converter means capable of producing a vibration voltage equal to zero; that the second output state produces a vibration voltage equal to d BMS (least significant bit) of the quantized output; that the third output state produces a vibration voltage equal to 3/4 of BMS of the quantized output) that the fifth output state produces a vibration voltage equal to 1/8 of BMS of the quantized output; that the sixth output state produces a vibration voltage equal to 5/8 of BMS of the quantized output; that the seventh output state produces a vibration voltage equal to 3/8 of BMS of the quantized output, and finally that the eighth output state produces a vibration voltage equal to 7/8 of BMS. 7. A generator according to Claim 6, characterized in that the ninth to sixteenth output states of said n-bit binary counter make said digital analog converter means capable of producing a vibration voltage greater than 2 BMS in each of said first to eighth states ; that the seventeenth to twenty-fourth output states produce a vibration voltage greater than 1 BMS in each of the above first to eighth states; that the seventeenth to twenty-fourth output states produce a vibration voltage greater than 1 BMS than each of said first to eighth states, and that the twenty-fourth to thirty-second output states produce a vibration voltage greater than 3 BMS to each of said first to eighth exit states.