FR2490899A1 - DECODING APPARATUS FOR CODES REPRESENTED BY A CODE TREE - Google Patents

Abstract

IN THIS APPARATUS, SERVING TO DECODER A CODE OF VARIABLE LENGTH REPRESENTED BY A CODE TREE AND IN WHICH A MEMORY WITH DECODING TABLES 16 IS READ AND MEANS DECIDE WHETHER THE DATA READ ARE FINAL OR INTERMEDIATE, MEANS ARE PROVIDED FOR. INPUT 24, 26, 36 INTRODUCING, FOR INTERMEDIATE DATA, A GIVEN NUMBER OF BITS TO BE ENTERED, FROM AN ENTRY CODES TRAIN, AND MEANS 22 PROCESSING THE INFORMATION OF INTERMEDIATE DATA TO DETERMINE THE ADDRESS OF MEMORY 16, TO WHICH THE ACCESS MUST BE MADE. APPLICATION IN PARTICULAR TO THE DECODING OF VARIABLE LENGTH CODES.

Description

The present invention relates to an apparatus for

  to decode a variable length code represented by

a network or a code tree.

  A known code of variable length represented by a code tree is for example the modified Huffman code. This code is obtained by encoding a black and white path length of an image scanned, using the Huffman coding system, as described for example in the article by R. Hunter et al. International Digital Facsimile Coding Standards ", Proceeding of the IEEE, July 1980, vol. 68, No. 7, pp. 854-867, Chapter IV "One-Dimensional

  Coding Scheme "(a one-dimensional coding system).

  decoding of this modified Huffman code

  is to select one of two branches at each node of a code tree depending on whether a "1" or an "O" is detected for individual bits of the input code, ultimately leading to level of an endpoint indicating

  a decoded result. To achieve this decoding, it is necessary to

  to access a decoding table memory for each

  that bit of input data and decide, for each

  of the memory, whether the endpoint is reached or not.

  This increases the number of processing steps, including time-consuming memory access, and the

  treatment of decisions, which means that the overall duration

  treatment bale becomes relatively long. It's for-

  that the decoding method of the prior art, mentioned above, is disadvantageous by the fact that it can not be

  implement only through the use of a micropro-

  high-speed terminator or wired logic circuit.

  Although it is not intended to be used for the facsimile code, a method for increasing the decoding rate for the Huffman code is described in the United States Patent number

  3,883,847, entitled "Uniform Decoding of Minimum-

  Redundancy Codes "(Uniform Decoding of Redundancy Codes)

  minimal). According to the decoding method described in this

  vet, the data of a predetermined number of bits are inserted

  using an input code train to access a main memory with decoding tables for reading and, in the case where the decoding is not completed by means of reading, an address of a secondary memory with decoding tables, which must then be accessed, is determined by using the read-out data, and then subsequently inputted multi-bit input data have access to the secondary memory with tables of decoding, which makes it possible to obtain a decoded result. This method increases the decoding speed, but uses two decode table memories and therefore has the disadvantage that the capacitance

  overall memory is important.

  An object of the present invention is to provide a decoding apparatus capable of high speed decoding of a variable length code represented by a

  code tree, without implementing the deco operation.

  bit-wise, and whose decoding table memory

  used has a low capacity.

  In accordance with an aspect of the present invention, the decode table memory has an area for storing the final data and a region for

  storage of the intermediate data. The final data

  include at least one information indicating the completion of

  decoding and information indicating the result of the decoding, and the intermediate data include at least

  information indicating incomplete decoding, information

  indicating the number of bits to be inserted

  then from a train of input codes and information

  on which the address of the table memory is based

  decoding, which must then be accessed. It happens

  provides access to and readout of the decoding table memory, and decision means determines whether the data read out of the decoding table memory is final data or intermediate data. In

  the case of final data, the information given in the

  as the result of the decoding is delivered by the decoding apparatus. In the case of intermediate data, the data

  are introduced from the code train of

  with a number of bits which is determined by the informa-

  intermediate data indicating the number of bits

  to be introduced later, and the data entered

  information and intermediate data for the

  determining the address of the memory with decoding tables

  ge, which must then be accessed, are treated as

  to provide the address, which must be accessed

  later, then access to the address of the decoding table memory is then achieved. These operations are repeated until the final data is read

  out of memory to decoding tables.

  By determining, from the data extracted by reading, the number of bits of the code to be introduced

  subsequently and by determining the address of the memo-

  to decode tables, which must then be accessed by exploiting the data entered by such a predetermined number of bits and the information extracted by reading,

  it is possible to decode both a code having more than one

  binary bits without the need to select one of two branches at each node of the code tree, and it is possible to reduce the number of access repetitions to the decoding table memory, which allows high speed decoding. In addition, there can be repeated access to the same decoding table memory and therefore this memory can be used efficiently and can be given a small size. In addition, when the decoding of a code is completed, a first bit of the code stream

  input indicates the leading bit of the next code.

  In accordance with another aspect of the present invention,

  the final data present in the decoding table memory include information indicating the completion

  decoding, information indicating the result of the deco-

  and information indicating the number of bits in front of

  to be introduced afterwards, and the intermediate data

  clue information indicating incomplete decoding and

  information on which is based the address of the memo-

  re to decoding tables which must be accessed later. After the decoding table memory has been read, decision means decides, with respect to the data extracted by reading, whether it is final data or intermediate data. In the case of final data, the information of the data indicating the result of the decoding

  has been released and the subsequent data are introduced

  firing of an input code train by the number of bits specified

  informed by the information extracted from the reading,

  indicating the number of bits to be introduced next.

  In the case of intermediate data, the subsequent data

  res are introduced from the input code stream by a fixed number m of bits (m being an integer greater than or equal to 2), and the data entered and the information of the data extracted by reading for the determination of the address of the decoding table memory, which must then be accessed, are processed, then the result of the operation is used to achieve access

  to the decoding table memory. These operations are repeated

  for the successive decoding of the codes of the input code stream. The number of bits to be inserted into the final data is then provided by L- (n-1) .m, where L is

  a decoded code length and n is the number of repetitions

  access to the decoding table memory.

  By way of example, we have described below and illustrated

  schematically in the accompanying drawings a form of embodiment

the object of the invention.

  Fig. 1 is a diagram showing a portion of a decoding table for the modified Huffman code, at

  by means of a bit-by-bit decoding method using an ar-

code.

  Figure 2 is a diagram showing the operational phases

  decoding an input code "11011" indicative of a white path length 64, through the use of

  of the decoding table shown in FIG.

  FIG. 3 is a block diagram illustrating a

  decoding wire described in the patent filed in the United States

of America under No. 3,883,847.

  Fig. 4 (4A, 4B) is a diagram showing an example of a decoding table for blank codes, which is used in the decoding apparatus according to the present invention.

present invention.

  Figure 5A shows an example of the final data format. Figure 5B shows an example of the intermediate data format.

  Figure 6 is a diagram showing the operational phases

  decoding an input code "11011" indicative

  of a length of white course 64, with the use of

  of the decoding table shown in FIG.

(4A, 4B).

  Figure 7 shows a block diagram of an example of

  the decoding apparatus according to the present invention,

  reading the decoding table of Figure 4 (4A, 4B).

  Fig. 8 shows an example of a part of the decoding table for white codes, for use in another embodiment of the apparatus

  decoding according to the invention.

  Figure 9 is a diagram showing the phases

  procedures for decoding an input code "11011" representing

  of a length of white course 64, with the use of

  the decoding table in Figure 8.

  Fig. 10 shows a block diagram representative of another embodiment of the decoding apparatus

  according to the present invention using the table of deco-

of Figure 8.

  Fig. 11 shows a block diagram representative of another embodiment of the decoding apparatus according to the present invention, using the decoding table of Fig. 4 (4A, 4B) and constructed using

a microprocessor.

  Fig. 12 is a flowchart showing an exemplary operation of the decoding apparatus shown in

Figure 11.

  Figure 13, (13A, 13B) is a diagram, corresponding to

  to that of Figure 4 (4A, 4B), showing an example

  a decoding table for a black code.

  Figure 14 is a graph showing the relationships between different decoding systems and the capabilities of

  memory decoding tables required for these systems.

  Figure 15 is a table showing the relationships between different decoding systems and the required times

  to access the decode table memories.

  FIG. 16 is a table showing the relationships between the decoding table memory capabilities and the required access times in each decoding apparatus, in the case where the capacity of the decoding table memory

  age and the access times to the memories required in the first

  The first embodiment of the present invention is

each represented by 1. -

  In order to facilitate a better understanding of

  present invention, we will first provide a descrip-

  of the conventional bit-by-bit decoding method. Figure 1 shows a portion of a modified white code tree of Huffman code, based on the conventional decoding method

  bit by bit, the code tree constituting a table of deco-

  dage. A root 1 is subdivided into two branches 4, each of which reaches a node 2. The node 2 is subdivided into two branches 4, each of which is again subdivided into two branches 4 in each node 2. In this way, the nodes are reached. 3. On top of branch 4, at each node 2 and before it is subdivided, an address <XX> of the decoding table is shown.

  data (XX) of the decoding table or a length par-

  run [XXI. The X's of this address and this data take

  the shape of any of the characters 0, 1, 2, 3, ...

  9, A, B, C, D, E and F; indeed "XX" represents hexadecimal numbers with two digits. However, in the case of the path length, the X indicates a decimal number. A lowercase letter "c" indicates an additional extension

of the code tree.

  Fig. 2 shows an example of decoding a code "11011" representing a white path length 64, which is inputted as an input code stream.

  (data stream) in the decoding table of FIG.

  The decoding procedure begins with the preparation of (00) as initial data. The first bit "1" of the input data is introduced by being added to the initial data

  (00) so as to obtain a jump address <01>. Data

  born (04) of the jump address are read out.

  From the data (04), it is checked whether or not an end node of the code tree has been reached. The data (X2 = 0, X1 = 4) are represented as binary numbers and the fact that an end node has been reached or not is decided according to the fact that the most significant bit of "X2X1l "i.e.," 00000100 "is" 1 "or" 0 ". In this case, since the most significant bit is "0", it is decided that the end node has not been reached (in the case where the most significant bit is "1" it is is decided that the end node has been reached). Then the next bit "1" of the input data is added to the data (04) so as to obtain a jump address <05>. In this way one of the two branches is selected for each node 2 depending on whether each one-bit data is "0" or "1". Then, the access to the decoding table, the decision of the endpoint and the formation of a jump address are similarly repeated at each application of a bit of the input data, which

  allows to finally arrive at the endpoint.

  Thus an address <21> is reached and its data (Ci), that is to say "11000001" is read. Since the most significant bit of this datum is "1", it is decided that the end node has been reached, and the path length is decoded using the datum (Ci) of this end node. That is, the bit data that succeeds the most significant bit of the data (Cl = 11000001) indicates a termination code or a recovery code. When

  o this bit is "1", this indicates the recovery code and the time

  course is obtained by multiplying 64 by a number of

  6 digits of lower order, that is "000001" (a binary number) = 1 (a decimal number) in this case. When the data of the order bit immediately below the most important data bit of the data

  reads "0", this indicates the termination code and the

  their six lower order bits of the data indicates the

  In the prior art, it was necessary to

  re to access the decoding table for each bit of data and make a decision about the data, as described above. This inevitably entails

  a reduction in the decoding speed.

  Referring to Figure 3, we will give a brief

  description of a decoding method described in the patent

  deposited in the United States of America under No. 3,883,847. The input data is inputted into an input register 210, from which only K bits of the input data are transferred into a register 211. The K-bit data thus applied to the register 211 are incremented by 1 in an adder 212, whose output signal is used in

  as an address for access to a memory at deco-

  principal 214 through a circuit of

  213 and a door of inhibition 281. When the

  The decoded code from the memory 214 is a decoded result, the decoded code is output from a register 217 to an output conductor 243 through an inhibit gate 241 and an OR gate 242. in addition to the number of bits used in the introduced K-bit data is output from a register 216 to a bit rate multiplier 218 via an inhibit gate 283 and an OR gate 286. The input 210 is controlled by the bit rate multiplier 218 in accordance with

  number of bits thus used to introduce the quantity

  corresponding titer of the input data in the register 211. On the other hand, in the case where the K bits of the data entered in the register 211 do not constitute a code, the register 217 delivers a signal indicating that there has no issue of a decoded result when accessing the main table memory. This signal causes

  inhibition of the inhibition gate 283 and the positioning

  The output signal of the flip-flop 285 is sent to the inhibit gates 241 and 281 to inhibit them. In addition, the output signal from the register 217 is applied via the gate 286 to the multiplier 218 in order to drive the latter, by introducing the K bits of the input data.

  in the register 211 through the register 210.

  Unnecessary bits in the data of the register 211 are mas-

  By the output signal delivered to the register 216 in a decoder 260 so as to remove the required bits A. The output signal from the decoder 260 is incremented by 1 in an adder 261 and the summed result is used as an address to access a secondary-table memory 250 via an addressing circuit 251. In this in this case, the addressing circuit 251 is controlled by the output signal from the register 217 so as to determine which tables of the secondary table memory 250 are accessed. When memory 250

  is read, the decoded result is issued from a regis-

  272 to the output conductor 243 through gates 292 and 242 and the number of bits used for

  decoding is sent from a register 271 to the multiplier

  218 through the gate 286. Upon detecting the end of the input data by a detector 221, a flip-flop 222 is set and its output signal is sent to an inhibit gate 224 so that to close the latter, which stops the operation of

this decoding apparatus.

  The decoding apparatus according to the above-mentioned United States patent is of the type which

  realizes access to the main memory at table 214

  several bits of the input data and in which it

  There is no check to see if each bit is

  coded or not; therefore, the number of required accesses to the memory is small, which allows high-speed decoding. However, this apparatus requires the provision of the first and second memory tables 214 and 250, which

  causes an increased size of memory.

  Figure 4 (4A, 4B) illustrates an example of a

  decoding wire for use in the decoding apparatus according to the present invention; it is a decoding table using a white code tree of the modified Huffman code. In this case the length of the data (XX) is eight bits, the memory address <XX> is eight bits and the number of branches to be selected at a time, that is to say the number of bits of code to be decoded at once, is 1, 2 or 4. It goes without saying that the length of the data, the length of the memory address and the number of branches to be selected at a time are arbitrary. Similarly, the number of branches to be selected at a time can be set or limited by

  specific way to for example two. The reference figures

  1 to 4 are identical to those used in FIG. 1, but data during the course of the decoding is indicated by an internal node 5. Here the number of branches to be selected at a time is selected so as not to exceed number of branches 4 from the root 1 or the inner node 5 to the nearest end node 3. In fact in FIG. 4 (4A, 4B) the end nodes 3 closest to the root 1 are those having the addresses <07>, <08>, <OB>, <OC>, <OE> and < OF> on a

  line 61 and these are the fourth ones from the root 1.

  By examining the internal nodes on line 61 for example, an address <03> reaches the closest endpoint 3 at an address <10> which is a branch close to the address <03> and the number of chosen branches is equal to one. However, in the case of an <00> address, there is no endpoint before a second branch, that is, a branch on line 62, for example when an <13> address is reached . That is why the number of branches chosen from the <00> address to the nearest endpoint is two. The (FF) and (EF) data indicate an EOL line synchronization signal and the

  data (8F) indicate a decoding error.

  The data (XX) is stored in each address <XX> of a decoding table memory succeeding the decoding table of FIG. 4 (4A, 4B). [XXI indicates the course length and then X is a decimal number. The decoding memory has a zone for storing the final data and a zone for storing the intermediate data. In this embodiment the decode table memory is an eight-bit word memory and the final data and the intermediate data are each eight bits. The format of the final data is as shown in Figure 5A. When the least significant bit B1 is "1", this indicates an endpoint 3, that is to say a final data. The B2 bit succeeding the least significant bit B1 indicates the type il of the decoded code; in this example, it indicates whether the result

  decoded is a termination code or a recovery code.

  The six bits B3 to B8 are information indicating the

  decoded sultat, that is, the length traveled. When the bit B2 is equal to "1", the information of the decoded result is the termination code and, as indicated by the reference numeral 44, the bits B3 to B8 have the

  respective weights 20 to 25. When bit B2 is "0", the information

  The value of the decoded result is the recovery code and, as indicated by the reference numeral 45, the bits B3 to B8 have the respective weight 2 to 2. The format of the intermediate data is as shown in FIG. 5B. . When the most significant bit

  weak B1 is "0", it represents the internal node 5, that is,

  to say-that it indicates that the data is an intermediate

  in the course of decoding. The second bit B2 indicates the number of bits to be entered next from the input code stream. When bit B2 is "0", a bit is inserted and when bit B2 is "1", two bits

  are introduced. Bits B3 to B8 represent information

  to determine the address of the memory at tables of

  decoding, to which access must then be made.

  Fig. 6 shows an example of decoding in the case where "11011" indicating the white path length 64 is inputted as input to the decoding table of Fig. 4 (4A, 4B). The decoding operation of this case will be described with reference to FIG. 6. (00) is prepared as initial data. As previously described, the number of branches to be selected first, that is to say the number of bits to be introduced at the start of the decoding of each code, is four and four bits "1101" ( "OD" in the hexadecimal system) of the input data is added to the initial data (00) in order to obtain the jump address <OD>. AT

  from the jump address is read its data (34).

  By detecting the least significant bit B1 of the representation

  Binary "00110100" of this data, it is decided whether or not an endpoint 3 of the code tree has been reached. Since the least significant bit B1 is

  "0", this data is an intermediate data and its deco-

  has not been completed. From the second bit B2 = 0 of the binary representation of the read data (34), it is decided that the number of branches to be selected next is one. Then the next "1" bit of the input data is introduced and it is added to a data item, in which the bits B1 and B2 of the read data (34) have been made equal to "0", which allows obtain a jump address <35X. AT

  from the jump address is read its data (07).

  Since the least significant bit B1 of the

  binary presentation "00000111" of the data is "1", it is

  decided that a nodeSfinal of the code tree was reached.

  From the bit B2 = 1 of the read data, it is decided that the

  data is the recovery code. Thus the information of the result

  coded state B8B7 ... B = 000001 means a path length equal to 64, which is obtained by multiplying the result

  decoded ("1" in decimals) by 64.

  Fig. 7 illustrates an embodiment of the decoding apparatus of the present invention, based on the example of the modified Huffman code decoding table shown in Fig. 4 (4A, 4B). The operation of this apparatus will be described below in connection with the case where the input data "11011" is introduced as in the case of Figure 6. For the start of the decoding operation, a start signal The decoding is delivered as a high level "1" from a conductor 11 to a decoding completion detection circuit 12, for example for a certain time interval. As a result of the rise of the output signal from a line 32 delivering the output signal of the detection circuit 12, a flip-flop 14, indicating whether the input data is a white data or a black data, is reduced to the initial state to prepare white code decoding and simultaneously a memory address flip-flop 15 is reset. For the code of

  Modified Huffman, the operation of decoding a code of fac-

  similarly begins with a white code. A memory address

  from the flip-flop 15 is used to effect

  kill the reading of a memory 16, in which is located

2490E99

  stored in the decoding table of FIG. 4 (4A, 4B), and the initial data (00) extracted by reading is delivered to a data flip-flop 17. In the circuit 12 for detecting the completion of the decoding, the signal The above mentioned decoding start provides a low level in an output line 18 through an OR gate 33 and an inverter 34. Simultaneously the output signal from the inverter 34 produces a low level. in an output line 38 via a circuit 39

  lengthening of the pulses, constituted by a line

  late and an AND gate. Data selectors 19, 20 and 21 are respectively connected to the side b, by means of these levels. As a result of the operation indicated above, the data selector 20 is connected to a memory of

  23, immediately after the start of the operation.

  decoding ration. The initial data memory 23 is controlled by an output signal "" (indicating white code decoding) from the flip-flop 14 so as to set a value 4 in an input data counter

  24 through the selector 20. The clock signals

  The input from a terminal 25 is applied to the counter 24 and, in synchronism with these clock signals, a four-bit input data "1101" is input into a serial-to-parallel converter of the input data. from a conductor 27. Then the input data "1101" is sent by the serial-parallel converter 26

  to an eight-bit adder circuit 22, after which the

  serial-parallelizer 26 of the input data is ream-

  born in the initial state. That is, its input state is made equal to "0000", while its outputs are kept unmodified, ie, remain "1101". Meanwhile, the least significant bit B1 = 0 of the initial data (00) introduced into the data flip-flop 17 as previously described is applied to the decoding end detection circuit 12 to provide a high level. in the output line 18 through the OR gate 33, which causes switching of the selectors 19 and 21 on the side a. As a result, the bits B8 to B3 of the initial data (00) are applied by the flip-flop 17 to the eight-bit adder 22 via the selector 21. This initial data (00) and the input data "1101" from the serial-parallel converter 26 are summed in the eight-bit adder circuit 22 so as to provide a jump address <OD>. The selection

  20 is switched on the side a by the extension circuit 39.

  pulses after switching the selectors 19 and

  , that is after the exit of the <OD> jump address.

  Jump address <OD> is issued to the flip-flop

  bistable memory address 15. The read signal

  in a signal transmission line 28 has access to the memory 16 in order to read the data item (34) corresponding to

  the jump address <OD>, which is sent to the bistable flip-flop

  Therefore, in this case, B1 = O and B2 = 0. Since the least significant bit B1 is "0", this data is not a final data, but a

  intermediate data. Therefore, the data selectors

  19 to 21 are maintained on the side a by the decoding end detection circuit 12. The bit B2 = 0 is delivered as an address to a next data memory 36 for reading the content "1" which in turn is accounting in the counter 24 of the input data via the selector 20. By therefore, the next "1" bit of the input data from the conductor 27 is fed into the serial-to-parallel converter of the input data 26 in synchronism with the input clock signal. The output signal of the serial-to-parallel converter of the input data 26 changes to the state "0001" and the input signal to the eight-bit adder circuit 22 goes to the state (01). Bits B8 to B3 of the output signal (34) from the flip-flop

  bistable data 17 are applied to the circuit

  Eight-bit neur 22. (01) and (34) - "B2B1" are summed by the eight-bit adder circuit 22 to provide a jump address <35>, which is sent to the memory address bistable flip-flop 15 From the address <35> of the memory 16 is read a data (07) which is sent to the flip-flop of the data 17. Therefore the bits

  B1 and B2 both go to state "1".

  Since the least significant bit B1

  is "1", the end decoding detection circuit 12 de-

  that the data is a final data, that is to say

  that an end node has been reached, and the output signal de-

  tected switches the data selectors 19 to 21 on the b side. Since bit B2 is "1", a data selector 29 is switched to the MC side and bits B8 to B3 present in the data flip-flop 17 are applied to the six higher order bits of a flip-flop.

  bistable of delivery of the length of the course.The result is

  that the value "000001000000", that is to say the length of travel "64" is delivered, which ends the operation of

  decoding. In the modified Huffman code, when a length of

If the path length is greater than 63, this length is represented by a combination of a recovery code and a termination code. For example, a white path 80 is represented by a white path 64 + a white path 16. Therefore, the decoding for a recovery code is always followed by a termination code of the same color as the preceding code, which is accomplished in the decoding apparatus according to the present invention such that the decoded result of the recovery code, i.e.

  final data, always provides "1" as the next bit

  diatement the least significant bit B1, and the bit

  B2 = 1 of the final data is sent to the circuit 12 for detecting

  In this case, the least significant bit B1 = 1 is sent to the gate 33 and the decoding operation for

  next code starts with the white code. In the case of the

  white course 64, as explained above, the data is decoded in the form of a white path 64 + white 0. In the case where the decoded data is a termination code or end, the B2 bit of the final data is "0" and the bit B1 = 1 is delivered through the inhibit gate 35 to the flip-flop 14 to invert the latter, by changing the reading of the decoding table memory 16 from the table of code decoding

  blanks to a black code decoding table and reciprocal-

  is lying. Simultaneously the bistable latch of memory addresses

  re 15 is reset to decode the next input data in the same manner as in the case

input data "11011".

  Figure 8 shows part of the decoding table.

  of the modified Huffman code in another form of reali-

  of the decoding apparatus in accordance with this

  invention. In Figure 8 the parts corresponding to this

  4 (4A, 4B) are marked with the same reference numerals. In this case, the data length is 10 bits, the address memory is eight bits and the number of branches to be selected at a time, that is to say the number of bits of a data item. input to be introduced later in the case of unfinished decoding, is set to four. Similarly, in this case, X is a digit of a hexadecimal number and if the assignment of the bits in the case of each digit of the datum (XXX), which is converted into the form of the binary representation, is chosen as (Bi.B8B7B6B5XXB4B3B2B1), then the bit

  B1 indicates the end or continuation of the deco-

  dage; bits B2 and B3 indicate the number of initial data bits to be introduced after the end of

  the decoding operation, that is to say when the data ex-

  read-through is a final data; bit B4 indicates whether the decoded data is a recovery or termination code at the end of the decoding operation; and bits B5 to B10

  indicate an address data in the case of

  intermediate and the decoded result in the case of the final data. "X" is "1" or "0" and this is not used to

the decoding operation.

  FIG. 9 shows an example of the decoding procedure in the case where the decoding table of FIG. 8 is used and the data "11011" indicating the length of the white path 64 is introduced as data

  input. This operation will be described later.

  Fig. 10 shows another embodiment of the decoding apparatus according to the present invention, which uses the modified Huffman code decoding table, shown in Fig. 8. In Fig. 10, the parts corresponding to those in Fig. The data selector selects whether the value of the input data counter 24 is set to a fixed number of the input data from a control memory 35. a fixed number of bits or the number of data from a circuit 37 for setting the initial number of bits. The number setting circuit 37

  initial bit parameter sets the number of initial input

  for a code to be decoded later at

  firing output data B2 and B3 located in the data flip-flop 17 and this number is not fixed. The fixed bit number setting memory 35 is used to input a fixed number of input data during

decoding.

  We will describe the operation of the device

  shown in Figure 10 in relation to the case of the introductory

  input data "1101000" shown in FIG.

  9. In order to start the decoding operation, a decoding start signal is applied via the conductor 11 to the decoding end detection circuit 12 so as to reset the flip-flop 14 to the initial state. intermediate of the signal transmission line 32, by placing the decoding table memory 16 in the read state of the white code. Simultaneously, the memory address bistable flip-flop 15 is also reset so as to deliver data (000) from the memories 16 in the direction of the data flip-flop 17. On the other hand the detection circuit 12 the end

  decoding system delivers low levels in the output lines

  18 and 32 by means of the decoder start signal so as to switch the data selectors 20 and 21 to the

  side b as in the case of Figure 7. In this function

  The data selector 20 is connected to the circuit 37

  setting the initial number of bits. The circuit 37 of

  setting of the initial number of bits is reset to the initial state

  by the decoding start signal so as to position-

  enter an input count data "4" in the counter 24 of the input data. The first four bits "1101" of the

  input data is applied to the serial-to-converter

  parallel of the input data 26 from the driver 27 in synchronism with input clock pulses from the terminal 25. The data entered can be

  be represented by (OD) in hexadecimal notation.

  Then the serial-parallel converter of the data of

  26 delivers the input data "1101" to the addi-

  In the meantime, the least significant bit B1 = 0 of the initial data (000)

  in the data flip-flop 17 is applied to the circuit

  cooked decoding end decoding 12 so as to provide

  a high level in the output line 18 through the intermediary

  OR gate 33, causing the switching of the selec-

  21 on the side a. Therefore bits B10 to B5 of the initial data (000) are inputted from the data flip-flop 17 into the eight-bit adder circuit 22 via the data selector 21. The input data "1101 ", i.e. (OD), and the initial data (00), i.e. (000) -" B4B3B2B1 "are added to provide the jump address <OD>, who

  is delivered to the bistable latch of memory addresses 15.

  The data selector 20 is controlled by the pulse extension circuit 39 by being switched to the a side after the data selector 21, i.e. after the jump address <OD> has been issued. Under the effect of the signal delivered in the signal transmission line 28 by the eight-bit adder circuit 22, a datum (AOO) (B10B B8B7B6B5XXB4B3B2B & '101OOOOOOOO in binary representation) corresponding to the jump address <OD> is read. out of the shift table memory 16 to be introduced into the data flip-flop 17. This data is an intermediate data for an internal node since the least significant bit B1 is "O". The decoding end detection circuit 12 maintains the selectors of

  data 20 and 21 in the "unfinished" state (on the a side).

  Therefore "4" is introduced by the memory 35

  of setting the fixed number of bits in the data counter.

  input 24 and four "1000" bits of the input data

  following are introduced into the series-parallel converter

  the input data 26 in synchronism with the impulse

  input clock. The output signal of the converts

  series-parallel data input 26 goes to state

  "1000" and the input signal to the add-on circuit

  eight-bit neur 22 becomes "00001000" (08 in the representation

  hexadecimal representation). Bits B5 to B1o of the output signal

  from the flip-flop of data 17 are deli-

  to the eight-bit adder circuit 22 so as to send another input signal (A0) thereto. In the

  hut bit adder circuit 22, (08) and (Ab) are added.

  to each other so as to provide a jump address <A8>, which is sent to the bistable latch of memory addresses 15. Simultaneously, the data (049) (B10B9B8B7B6B5 XXB4B3B2B1 = 0000010010 "O" according to the binary representation) is read out of the decoding table memory 16 to be introduced into the data bistable flip-flop 17. The least significant bit B '= "1" indicates that this data is a final datum, c' that is, an end node has been reached at the end of the decoding operation The data selectors 20 and 21 are switched by the end decoding detection circuit 12 on the b side ("end") Since bit B4 is "1", data selector 29 is switched to the MC side, i.e., the output signal from data selector 29 is fed into

  as a recovery code in the flip-flop 31 of output

  of the length traveled so as to obtain "000001000000" according to the binary representation, to have the path length "64", which ends the decoding operation.

  A datum B3B2 = "00" of the flip-flop of data

  17 is sent to circuit 37 for setting the initial number

  tial of bits, where the "00" is incremented by one to provide a value "1", which represents a difference between the fixed number of bits of the input data "4" and the number of bits

  "3" of the data "000" which has not been used for deco-

  input data "11011000". The value "1" is

  applied as initial data to the data counter.

  24. In this example, since the bit

  B4 of the final data read is "1", the circuit 12 for detecting

  The end of decoding operation resets the memory address flip-flop 15 while maintaining the flip-flop 14 in an unchanged state, i.e.

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  now the decoding state of the white code. From the memory 16 is read the data (000) which is introduced into the flip-flop of the data 17. Then, when entering the data in the serial-parallel converter of the input data 26, the decoding of the next input data is done in the same way as in the case of the "1101l" input. In the case where the bit B4is "0" when the final data is read, the decoding end detection circuit 12 inverts the flip-flop 14 so as to switch the reading of the decoding table memory 16 over the reading of the black code table and reset the flip-flop of memory addresses 15. In the embodiment described above in connection with Figures 8 and 10, the data is introduced in steps of a fixed number bits, four bits in the case of this example, during decoding, and these bits of the introduced four-bit data, which were not used for decoding, that is to say the three bits " 000 "in the example

  above, are used for the decoding immediately following

  efore. Therefore the decoding resumes using these three bits and a bit of the following data (the fixed number

  bits, that is, four bits in this example).

  The decoding apparatus according to the present invention

  can be formed by using not only a

  cabled logic as shown in Figures 7 and 10, but also a general purpose circuit, provided with a memory access function and a decision function and

  for calculating data, such as, for example, microproces-

  sor. Referring to Figure 11, we will give a

  an example of the decoding apparatus using a microprocessor in connection with the case of the decoding table of FIG. 4 (4A, 4B) used. To a bus 41 is connected a microprocessor 42, a serial-parallel converter 43, a memory and reception buffer 44, a

  program memory 45, an output port 46 and the memory

  In this memory 16 is stored the decoding table of FIG. 4 (4A, 4B), 1

  that is, the data represented by (Xx) is stored

  at each address represented by <XX>. The microprocessor 42 has several general registers 47,

  accesses the program memory 45 in sequential order

  in order to introduce the instructions read into the

  within an instruction register 48, decode these instructions

  in a decoder 49 and performs various input / output control operations and decisions based on the decoded results. The logical addition and decision operations are performed by an operator 51 in connection with

  data from the general register 47. The results of the

  are stored in the general register 47. The memory

  with decoding tables 16 and the program memory 46 can

  can be constituted by a memory. An input code stream is introduced into the serial-parallel converter 43 from the conductor 27. At each application of e.g. eight bits, an interrupt signal is applied.

  through a transmission line of interrup-

  tions 52 to an interrupt circuit 53 of the microprocessor

  42. When receiving the interruption signal, the micropro-

  processor 42 stores an eight-bit serial data from

  of the serial-parallel converter 43 in the memory

  receiving buffer 44. The output port 46 serves to deliver

the decoded results.

  Referring now to a flow chart such as that shown in Figure 12, an example will be described.

  the operation of the decoding apparatus mentioned above.

  above. The operation starts with a processing step S1, during which the number of initial input bits, i.e. the number of bits to be entered first from the input code stream, "4 in this example, is set in a general register 47a and a

  initial address data for the table-top memory

  Step 16, i.e. (00) in this example, is set in a general register 47b. During the next processing step S2 is checked whether, for example, all the bits of the eight-bit input code entered in a general register 47c from the receiving buffer 44 have been used or not. In the case where the input code has already been used, the operation proceeds to a phase or no S3 processing, during which the next eight-bit data is introduced from the receiving buffer 44 into the register General 47c. During a processing step S4, the data corresponding to the number of input bits "4" positioned in the register 47a during the processing step S is transferred from the register 47c to a general register 47d. During a processing step S5, the data thus transferred to the general register 47d and the initial address data item (00) positioned in the register 47b during the processing step S1, are added one

  to another to provide an address. This address is used

  for access to the decoding table memory 16 at the

  during a S6 treatment step. During a treatment step

  S7 it is checked whether the least significant bit B1 of the data read out of the decoding table memory 16, is "1" or not. When the bit B1 is not "1", the data read is an intermediate data and the next address data and the number of bits of the input code

  to be introduced then are positioned. That is,

  say that, in the example described above, it is checked during processing step S6 if the bit B2 of the data read is "1" or not. If the bit B2 is not "1", then the number of bits of the input code to be entered next is "1" and, during a processing step S, the bits B3 to B8 of the read data. Out of the decode table memory 16 are set as address data in the general register 47b and, simultaneously, the number of bits of the input code "1" is set in the general register 47a. In the case where it is decided, during a processing step S8, that the bit B2 is "1", the number of bits of the input code to be entered next is "2", and in one step Sio the bits B3 to B8 of the read data are loaded into the general register 47b and simultaneously the number of subsequent bits of the input code "2" is loaded into the general register 47a. After the processing steps S9 or S, the operation returns to the processing step S2 so as to repeat the procedure indicated above, When at the S7 processing step it is decided that the least significant bit B1 is "1", the data read out

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  of the decoding table memory 16 is a final datum

  and the operation goes to treatment step Sil, during

  which is verified if the bit B2 of the data is "1" or not. If it is decided that the bit B2 is "1", the data is a recovery code and n (in decimal number) represented by the bits B3 to B8 of the data must be multiplied by 64 to provide the path length ( no processing S In the case where it is decided during a processing step S11 that the least significant bit Bi is "0" and the read data is a final code, the bits B3 to B8 of the data are obtained in the form of the path length at a processing step S 13. The decoded result obtained during

  the S12 or S13 treatment step is delivered as a

  This is decoded by the output port 46 (FIG. 11) during a processing step S14. Then it is checked during a processing step S15 whether the decoding has been completely completed or not. This can be decided on the basis of the input code data or the decoded data, as in

  the case of the prior art. When it is decided that the deco-

  is not yet completed, the operation proceeds to the processing step S16 'where, when it is decided that the

  decoded code is a termination code, ie when

  it is decided during the processing step S11 that the bit B2 is "0", the next decoding operation is switched between the decoding of the white code and the decoding of the black code

  and vice versa, then the operation returns to the step of

  S1. In the case where it is decided during processing step S15 that the decoding is not yet completed and that

  bit B2 is "1" during the processing step Si, the operation

  tion returns to step S1 without going through

S16 treatment.

  An example of the decode table for black codes is shown in Fig. 13 (13A, 13B) in the same manner as in Fig. 4 (4A, 4B). As will be understood from this table, there is an end node at a second branch from root 1, so that the number of input code bits to be introduced first is "2 ". As can be seen from FIGS. 4 (4A, 4B) and 13 (13A, 13B), these decoding tables

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  contain unused addresses (for example <OA> and

  <OB> in FIG. 13 (13A, 13B)> and consequently the

  moire to decoding tables is not used effectively in this respect. The decoding table memory is made in such a way that such useless addresses are

  can not exist, it is possible to reduce to sup-.

  plement the capacity of the memory.

  Since the embodiment of Fig. 7 uses an eight-bit word memory as an offset table memory 16 and eight bits as information of the decoded result and as data for the determination of the address at which the access must be made afterwards,

  so that the number of input bits to be introduced

  for each code, "4", is set in the memory 23. However, it is possible to adopt an arrangement such as in the case where the number of bits to be introduced at a time, including the number of bits to be introduced first, is "2" or less, the

  number of bits to be introduced is always determined

  born by the information that determines the number of bits of

  in the data read from the table memory of

  16. By choosing for the number of bits constituting

  killing a word of memory decoding tables 16 a value greater than 8, it is possible that in the case o

  the number of bits to be introduced at a time, including

  taken the number of bits to be introduced first,

  is greater than two, the number of bits to be inserted

  in accordance with a maximum number of input bits is still always determined by the information which determines the number of input bits in the data read from the

memory with decoding tables 16.

  Thanks to the decoding apparatus according to the present invention, described above, it is possible to reduce the

  required capacity of the decoding table memory. The

  Figure 14 shows memory capacities required for different

  decoding methods. The abscissas represent the decoding methods. The abscissa 1 indicates a decoding method using a code table and according to which the codes of the stored code table are sequentially

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  products to be compared to an entry code for ob-

  keep a decoded result based on the coincidence between the codes. The abscissas 2, 3 and 4 each represent the case of the use of the method described above in connection with FIG. 7, the abscissa 2 representing the case where the number of bits of the input code is chosen at a preferred value for each node of the code tree, the abscissa

  3 illustrating the case where the number of bits to be introduced

  both is chosen equal to either "1" or "2" or "4", and the abscissa 4 represents the case where the number of bits to be introduced at a time is chosen to be equal. either "1" or "2". The abscissa 5 marks the

  bit-by-bit decoding method described above with reference to

  Figure 6. The abscissas 6 to 10 each illustrate

  the case of the use of the decoding method described above.

  10 for the abscissa 6 to, the fixed number of bits to be introduced at a time.

  is chosen to be equal to "2", "3", "4", "5", "6",

  tively. The abscissas 11 to 17 each illustrate the case of the use of the decoding method referred to above with reference to FIG. 3. For these cases 11 to 17, the number of bits to be introduced at a time is chosen as being equal. at 7, 8, 9, 10, 11, 12 and 13 respectively. The ordinate represents the storage capacity. Curve 63 identifies the case of using a 1-bit 16-bit memory and curve 64 identifies the case of using an 8-bit one-bit memory. It can be seen from FIG. 14 that the memory capacity required for the apparatus of FIG. 7 is equal to the smallest of the memory capacities required in the methods of the prior art, and is equal in particular to approximately 1/3

  of the smallest capacity in the case of the use of

  In the apparatus shown in FIG. 10, an increase in the number of bits to be introduced first causes an increase in the required memory capacity, but the memory capacity is less than or substantially equal to memory capacity

  necessary in the case of Figure 3.

  Figure 15 shows the memory access times, which are required for the different decoding methods. The abscissae identify the same processes as those mentioned above in connection with FIG. 14 and the ordinates represent the number of accesses. Curves 65 and 65 'each indicate a maximum access time, bursts 66 and 66' average access time and curves 67 and 65 '.

  67 'a weighted average access time taking into account the

  the appearance of different codes; curves 65 ', 66' and 67 'illustrate the case of using a 16-bit word memory and the other curves illustrate the case of using an eight-bit word memory. In FIG. 15 it is noted that the number of necessary actions in the apparatus according to the present invention is clearly less than the number of actions required in the case of the bit-by-bit decoding method identified at the abscissa 5, and

  only slightly higher than in the case of

  3. Considering the weighted average access times which represent the most usual values, the apparatus according to the present invention is

  fairly close to the apparatus of Figure 3.

  On the basis of the data indicated above, the

  Figure 16 shows the capacity of memory at deco-

  time and access times in each of the different

  the memory capacity to decode tables and the

  number of accesses in the apparatus of FIG. 7 being representative--

respectively by 1.

  As previously described, in accordance with

  the present invention, the number of bits to be in-

  troduits then is determined by reading out of the

  decoding table memory, by an addition or an operation

  analogous representation of the data read out of the table memory

  decoding and the code introduced is implemented to de-

  terminate the address to which access must then be made, then access to the same decoding memory is performed using the address. This reduces the capacity of the memory and the number of accesses and therefore allows high-speed decoding with reduced hardware. Furthermore, in accordance with the embodiment of FIG. 7, in the case of decoding a code, the bit of

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  header of the input code becomes the first bit of the next code,

  which facilitates further processing.

  Although, in the foregoing, the address, which is then accessed, is obtained by adding to one another the data read out of the decoding table memory and the input code, it is also possible to obtain this address by other operations applied to these data,

  such as subtraction and multiplication.

  In the foregoing, since the forms of

  of the present invention have been described as being

  applied to the decoding of the modified Huffman code, the

  the code type, that is, the code is a recovery code or a termination or termination code, is included in the final code, but in the case of a Huffman code simple, the information indicating the type of code is not necessary. In addition the present invention

  can also be applied to the decoding of codes

  variable form represented in a general way by a

code tree.

  It is clear that one can bring

  many modifications and variants to the subject of the invention

  without departing from the framework of the latter.

Claims (11)

  1. Apparatus for decoding a time code   variable means represented by a code tree, in which a read device with access to a decoding table memory (16) for extracting data from it by reading, decision means decides whether the data extracted by reading are either data final, either   intermediary data and, in the case of final data,   the, information indicating the result of the decoding in the final data and output by output means (31), and, in the case of intermediate data, the decoding table memory (16) is read on the basis of the data   address present in the intermediate data,   in that the decode table memory (16) has an area for storing the final data including information indicating completion of the decoding and information indicating the decoded result, and an area for storing the data. intermediates including information indicating uncompleted decoding,   information indicating the number of bits to be inserted   from a train of input codes and information   tion to determine the address of the decoding-table memory to which access must be made, and   input means (24, 26, 36) are provided for   in the case of intermediate data, outputting data from the input code stream by means of the number of bits indicated by the information of the intermediate data indicating the number of bits to be inputted and means (22) for processing data. addresses for processing, in the case of intermediate data, the information of the intermediate data for determining the address of the decoding table memory, to which access is to be made, and the data introduced by the means input to get the memory address to tables from   decoding, to which access must be made later.   Decoding apparatus according to claim 1, characterized in that the information indicating the number of   bits to be introduced is chosen as a   variable less than the number of branches starting from a root or an internal node and ending at the endpoint   the closest to it in the code tree.   Decoding apparatus according to claim 1,   characterized in that the number of bits to be introduced is   first feed for each code of the input code stream is stored in an initial data memory provided   independently of the decode table memory (16).   Apparatus for decoding a variable length code represented by a code tree, in which a reading device has access to a memory   decoding tables (16) to extract data from   read-out means, decision means decides whether the read-out data are either final data or intermediate data, and, in the case of final data, information indicating the result of the decoding in the final data is delivered by output means (31), and, in the case of intermediate data, the decode table memory (16) is read on the basis of the address data present in the intermediate data, characterized in that the table memory decoding circuit (16) includes a zone for storing the final data including information indicating completion of the decoding, information indicating a decoded result and   information indicating the number of bits to be in-   products first for each code, and a zone intended for   storage of intermediate data including information   an indication of incomplete decoding and information for determining the address of the decode table memory to which access is to be made, and that input means (24, 26, 35) are provided; ) for inputting data of a fixed number of bits m (m being an integer greater than or equal to 2) from the input code stream in the case of the intermediate data, means (22) of   processing addresses to process, in the case of   intermediate information, the information to determine the address of the decoding table memory to which access   be done, and the data introduced by the means of   to obtain the memory address at deco-   to which access must be made afterwards, means of 2490E99   (12) for repeatedly activating the reading means, the input means, the decision means and the address processing means until the final data is extracted by reading, and second input means (24, 26, 37) to introduce, in the case of final data, a data of the input code stream by means of the   number of bits indicated by the information indicating the name   number of bits to be entered first.   5. The decoding apparatus according to claim 4, characterized in that the information indicating the number of bits to be introduced first is L- (n-1) m, where L is the length of the decoded code at this time and m is the   number of accesses to memory at deco- dage (16) for decoding.   6. Decoding apparatus according to claim 4, characterized in that it further comprises means for storing a fixed number m, namely the number of bits which are introduced in the case where the decision means decide that the data extracted by reading is a given intermediate.   7. Decoding apparatus according to one of the claims   4, characterized in that the final data comprises information indicating the type of a decoded code. Decoding apparatus according to claim 7,   characterized in that the output means (31) is arranged   in such a way that in the event that the means of   decide that the data extracted by reading is a final data, the destination of the information of the decoded result of the final data is modified in accordance with   the information of the final data indicating the type of code.   9. Decoding apparatus according to one of the claims   1 or 4, characterized in that the means (22) for processing   Addresses are means of achieving an addition operation.   10. Decoding apparatus according to one of the claims   1 or 4, characterized in that, in the final data and intermediate data formats, the same bit is assigned to the information indicating the completion of the 249OE99   decoding, and the information indicating the uncompleted state of the decoding.   11. Decoding apparatus according to one of the claims   1 or 4, characterized in that, in the formats of the final data and the intermediate data, the allocation   bits to the information of the decoded result and the   information to determine the address of the decode table memory (16) at which   access must be effected, overlap each other at least cally.