FR2466951A1 - Animal deterrent ultrasound generator - has swept pseudo-random frequency generator using shift register control - Google Patents

Abstract

The device has control of the frequency of the oscillator by using a shift register circuit whose last stage is coupled back to the first via a coincidence gate. Further inputs to the gate are taken from other stages in the register. The output power is high and is derived from a variable frequency, e.g. between 18kHz and 40kHz, variable output local oscillator. This supplies a power amplifier and one or more output transducers. The generator overcomes the fall in efficiency in keeping animals away, due to their becoming familiar with constant frequencies or regularly swept frequency ranges, by varying the sweep rate and changing the frequency in a pseudo-random fashion.

Description

 The invention relates to an ultrasound generating apparatus for moving pests away from a protected area.

 The technical system of the invention is that of the construction of electronic devices for removing pests from a protected area.

 It is known that ultrasonic waves of a certain frequency make susceptible animals susceptible to ultrasonic frequencies.

 Many ultrasound operators have been proposed for this purpose.

 U.S. Patents 2,922,999, U.S. 3,058,103, U.S. 3,879,702 disclose such devices that emit ultrasound on a fixed frequency or by scanning frequency ranges and continuously or periodically.

 Experience has shown that rats and other pests end up accustoming to periodically emitted ultrasound even if they are emitted by scanning a frequency range.

 To overcome this drawback, it has been proposed to emit intermittent ultrasonic pulses which appear randomly and whose duration is also random.

 U.S. Patent 3,872,472 discloses an ultrasound generator apparatus for hunting pests which includes an oscillator. variable frequency which is controlled by a sawtooth voltage. so that the frequency increases and decreases at a constant speed. This patent contemplates the possibility of providing the apparatus with random timers of a known type as well as a random voltage generator, but gives no description of these random devices.

An object of the present invention is to provide an ultrasound generator apparatus for effectively expelling undesired animals by avoiding habituation effects.
Another object of the present invention is to provide an ultrasound generating apparatus which emits at varying frequencies with scan rates, irregularly varying frequencies, and intermittently and non-periodically transmitting using a sequence generator. pseudorandom
Another object of the invention is to provide an ultrasound generating apparatus which can emit high power ultrasound having a powerful effect, avoiding the effects of deterioration by heating.

 An apparatus according to the invention comprises, in known manner, an electronic oscillator which delivers a periodic voltage having a controllable frequency of between 18 kHz and 40 kHz, a power amplifier, one or more electroacoustic transducers which are excited by said amplified periodic voltage, a gate interposed between the oscillator and the transducers, which chops the emission, andmeans for varying the frequency of said oscillator and for controlling said gate.

 The objectives of the invention are achieved by means of an apparatus in which the means for varying the frequency and for chopping the transmission comprises a pseudo-random sequence generator which comprises a shift register whose last stage is looped back. on the first through a colncidence gate whose inputs are connected to the output of several stages of the register, so that each of the stages of the register cyclically takes binary values that succeed each other within each cycle in a program order irregular and pseudo-random.

 The pseudo-random sequence generator is interconnected with a circuit comprising a capacitor associated with a window comparator and a resistance scale which are alternately incorporated in the charging and discharging circuit of said capacitor by two series of logic gates whose inputs are connected to the different stages of the shift register, which gates have, for each series, an input which is connected to the output of said window comparator and which alternately validates one series then the other whenever one of the two thresholds of the comparator is reached, so that the voltage across the capacitor oscillates sawtooth arcs exponential whose slope is variable.

 The output of the window comparator is connected to the control terminal of the registers shifts and controls the shift whenever the lower threshold of said comparator is reached.

 The oscillator of an apparatus according to the invention comprises a capacitor associated with a window comparator with adjustable thresholds and the sawtooth voltage which is delivered by the control sequence generator, via auxiliary circuits, said thresholds .

 The power amplifier of an apparatus according to the invention is composed of four transistors mounted in switches and the transducers are interposed in a diagonal of the bridge thus formed.

 The invention results in a novel ultrasound generating apparatus for hunting undesirable animals.

 An apparatus according to the invention has the advantage that it avoids the accustomed animal ultrasound emitted.

 Indeed, firstly these ultrasounds are not transmitted on a single frequency but with a frequency that varies during each sequence with a different speed and apparently unpredictable from one emission to the next. In addition, the duration of the transmission sequences varies, as the duration of the silences that separate two emissions and the variations in duration are also unpredictable. As a result, the animals are completely frightened by these emissions, which shake their nervous system and can not become accustomed to them, which causes them to escape.

 The device therefore remains effective even over a long period of use.

 The use of a pseudorandom sequence generator composed of a shift register and a few common doors and components, makes it possible to obtain both a variation of the sweep rate of the frequency ranges and of irregular duration variations. .

 Although the sequences are not entirely random but are programmed, as the cycle repeats after a rather high number of pulses, for example every fifty pulses, the animals can not memorize an entire cycle and the effect of Surprise is the same as if the sequences were completely random but it can be obtained with simpler and more reliable circuits.

 The following description refers to the accompanying drawings which represent without any limiting character an embodiment of an apparatus according to the invention.

 Figure 1 is a block diagram of an apparatus for hunting pests.

 FIGS. 2 to 8 are diagrams of the principal circuits and electronic components of the apparatus according to FIG.

 Figure 1 shows an electronic oscillator X which emits on a variable frequency between 18 and 401 (ho, which depends on the control voltage of the oscillator.) The mark 2 represents a gate through which the signals emitted by the oscillator pass through. The mark 3 is a power amplifier and the mark 4 represents one or more electroacoustic transducers, for example piezoelectric transducers, which are excited by the signals delivered by the amplifier and which emit ultrasound.

 It has been found that if the ultrasound is emitted continuously, even under a modulated frequency, or even chopping at a constant periodicity, the animals end up accustomed to ultrasound and the device loses its effectiveness.

 To avoid this habituation, a device according to the invention comprises a circuit 5 which is a generator of pseudo-random sequences, ie an intermittent pulse generator which is the duration of the successive pulses and the duration of the intervals which separate the pulses. are not regular but reproduce cyclically after the emission of a relatively high number of pulses, all fifty impulses in our case.

 Such a pseudo-random digital pulse generator is easier to build than a less reliable analog random generator. It avoids habituation of the animals, because since the same cycle starts again after a high number of pulses, the animals can not keep in memory the whole cycle.

 The voltage delivered by the generator 5 controls the oscillator I and varies the frequency thereof.

 Pulses exited by 5 control the gate 2 and they determine the duration of the intermittent ultrasonic emissions emitted by the transducers 4.

 A device according to the invention further comprises power supply circuits 6, and current control circuits 7 which block the generator 5 and the gate 2 if an intensity threshold is exceeded.

 I1 also comprises logic circuits for commissioning and testing 8 which control the starting of the oscillator 1 and the gate 2.

 FIG. 2 represents blocks 6 and 7 of FIG.

 Terminals B1 and B3 are powered by the mains with an AC voltage of 220V. B2 is land. The power supply circuits comprise a switch Il, I2, a transformer T1, a rectifier 9, a filter C1, an output terminal S1 which powers the power stage, a diode D1, a capacitor C2, a voltage regulator 10 and an output terminal s2 which supplies the electronic control circuits.

 During high power ultrasonic emissions, the energy is mainly supplied by the capacitor C1 which varies its charging voltage.

 On the other hand, the diode DI avoids the voltage fluctuations of the capacitor C2 which can only be discharged by the control circuits which consume little, hence a better regulation of the supply voltage of the control circuits and a better stability of operation .

 The control circuits comprise logic operators which must be positioned in a determined state, as soon as power is applied, in order to control the pseudo-random sequences.

 A device according to the invention comprises a circuit which understands the level of a voltage at a threshold.

 When the device is turned on, the DC voltage delivered to terminal S2 charges a capacitor C3 through a resistor R1. When the voltage across C3 reaches the voltage present across R3, a signal appears at the output S3 of the circuit 11. This signal appears only after a certain delay due to the time constant RI.C3 and this delay between switching on and the appearance of the voltage an S3 is used to preposition the control circuits.

As soon as the voltage S2 is established, a light indicator, a light-emitting diode D3, lights up
The circuit 11 also serves as a circuit breaker intended to avoid the deterioration of the circuits in the event of a short circuit.

The excitation current of the transducers is provided by the terminal
S1 through a circuit L1 which limits the current to a value greater than that required by the transducers. In case of a short-circuit, the current being limited, it is the voltage present on the terminal S1 which will then decrease, causing a decrease in the voltage across C3. When the voltage across C3 becomes lower than that across R3, the circuit changes state and the voltage at S3 momentarily disappears by blocking the device.

 The signal S3 disappears for a time determined by R1.C3; then signal S3 reappears automatically If the short circuit has disappeared; otherwise there is disjunction again.

 Fig. 3 shows the semi-random sequence generator 5 which generates binary logic signal sequences which succeed each other within each sequence in a pseudo-random order.

 FIG. 3 represents a shift register composed of six successive stages E1 to E6. The marks P11, P12, P13, P14, P15 and P20 designate the outputs of each stage which can be in the state O (low state) or in the state 1 (high state). The terminal S3 is the output terminal of the comparator 11 of FIG.

 The terminal S5 is the terminal which receives the successive pulses which cause the transfers of the binary number present in each register in the following register. These transfers occur at the rising edges of the x-pulses.

The outputs of the registers are combined with each other by means of four logical operators O1, O2, O3 and O4 of the NOR (NOR) type. The operator
O1 combines the outputs P11 and P20 and delivers a logic signal P16 = P1 @ + P20 = P11. P20.

The operator O2 combines the signals P11 and P16 and delivers a signal
P18a = P11 + P16 = P11. P16 = P11. (P11 + P20) = P11 P20.

The operator O3 combines the signals P20 and P16 and delivers a signal
P18 = P16 + P20 = P20. P11.

The operator O4 combines the signals P18a and P18 and delivers a signal
P17 = P18a + P18 = P11. P20 + P20. P11.

 The set of four operators O1, O2, O3 and O4 constitutes a logic coincidence gate XOR gate which combines the signals P11 and P20 and which delivers a signal P17 high if the signals P11 and P20 coincide, that is to say are both at the same time equal to 1, or both at the same time equal to 0.

 The signal P17 is returned to the register E1 so that the register is looped on itself through this coincidence gate.

 The upper part of Figure 3 shows the RAZ conductor used for resetting the registers. This conductor is connected to the power supply terminal S2 through a resistor Rg.

 I1 is connected to the output terminal S3 of the comparator 11 through a diode D4.

 Whenever the voltage S3 drops to zero the diode D4 is conductive and the registers E1 to E6 are reset.

The circuit of FIG. 3 further comprises two logic gates AND
G1 and G2 and a logic gate NAND (NAND) HI. The logic gate G1 combines the outputs P11 and P12 and performs the logic function P11. P12.

 Similarly, the gate G2 performs the function P15. P20. The logic gate H1 combines the outputs of the gates G1 and G2 and delivers a high logic signal equal to P11 + P12 + P15 + P 20. Whenever the output of the gate Hi is at the low level, that is to say when simultaneously P11, P12, P15 and P20 are equal to 1 ,. diode D5 is conductive, all registers E1 to E6 are reset and a new cycle starts again.

By constructing the truth table of the signals P11 to P20, it can be seen that each of these signals cyclically takes binary values I and O which succeed one another within each cycle according to sequences of O and I which are irregular and pseudo -aléatoires. For example, the following table gives the first positions from a reset of the register.

<Tb>

<SEP> Pl7 <SEP> Pii <SEP> P12 <SEP> P13 <SEP> P14 <SEP> P15 <SEP> P20 <SEP> P17
<tb> RESET <SEP> RESET <SEP> O <SEP><SEP><SEP><SEP>
<tb> Offset <SEP> I <SEP> O <SEP> o <SEP> I <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0
<tb><SEP> Offset <SEP> 2 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP>
<tb><SEP> Offset <SEP> 3 <SEP> 0 <SEP> X <SEP> I <SEP>><SEP> 0 <SEP> I <SEP><SEP><SEP>
<tb><SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0
<tb> Offset <SEP> 50 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1
<Tb>
It can be seen that the fiftieth shift brings the outputs P11. P12
P15 and P20 at Level I, causing all registers and a new cycle to be reset.

 Figures 4 and 5 show another part of the generator 5.

 The terminals P13, P11, P12 are shown on the left of FIG. 4 and on the right are the terminals P15, P14 and P20 which are connected to the register outputs of FIG.

FIG. 4 represents a scale of resistors810 to R15 which are associated on the left with logic gates NO OR K1 to K6 and with diodes
D4 to Dg and on the right to logic gates NOT and LI to L6 and diodes
D10 to Dols.

 At the top of Figure 4 is the terminal Sg which is connected to the output of the circuit of Figure 5. The terminal Sg is connected to the two inputs of a logic gate NO OR Jl.

 The presence of a positive voltage on the terminal S5, inverted by the gate J1, causes a positive output of all the doors L1 to L6 and thus the diodes D10 to D15 which are reverse biased are blocked.

 Conversely, a positive voltage at S5 validates one or more of the gates K1 to K6 according to the states of the outputs P11 to P13.

 The output terminal S6, located at the bottom of FIG. 4, is connected to the circuit of FIG. 5. It can be seen in FIG. 5 that the voltage at S6 charges a capacitor C7 through a resistor R16.

 The voltage across the capacitor C7 is transmitted to the following circuits by a transistor M1. The output voltage of the transistor Mi taken from the transmitter is connected to the input of a window comparator NI.

When the voltage S6 exceeds the upper threshold of the comparator, the output S5 of the comparator becomes negative and, at that moment, all the doors
K1 to K6 are closed and one or more gates LI to L6 open so that the capacitor C7 discharges through one of the diodes D10 to D15.

 The operation is as follows.

 When the voltage at the input of the comparator NI reaches the lower threshold, the output S5 becomes high and the rising edge causes the transfer of the states of each register E1 to E6 to the following, hence a change in the states of the outputs P11 to P20.

One or more of the outputs P11, P12 and P13 are negative and some diodes D4 to Dg are conductive. The capacitor C7 is charged through the diode D4 to Dg located lowest in the chain and the resistors
R10 to 15 corresponding, so that the charging time constant of the capacitor C7 depends on the resistances in circuit and the time required for the load of the capacitor C7 to reach the upper threshold of the comparator N1 varies during successive charges.

When the upper threshold of the comparator N1 is reached, S5 becomes negative and the capacitor C7 discharges through that of the turkeys D10 to
D15 which is conductive and which is the lowest in the chain. The time constant of the discharge circuit therefore depends on the resistances R10 to R15 which are incorporated in the discharge circuit and the time required for the charge of the capacitor C7 to reach the lower threshold of the comparator N1 therefore also varies during successive discharges.

 It can therefore be seen that at the output of the comparator NI a voltage Ss is obtained which varies between two high and low logic values and the duration of the slots depends on the time constants of the charging and discharging circuits of the capacitor C7. Cycles of 50 slots follow each other and, during each cycle, the rate, that is to say the duration of the successive slots, depends on the successive states of the outputs P11 to P20 of the shift register and the logical combinations made by doors K1 to K6 and L1 to L6. The voltage on the emitter of MI varies between the two thresholds of the comparator NI, according to arcs of exponential of variable slope. This voltage is transmitted through a resistor R18 on the negative polarity input terminal of an operational amplifier. P1 mounted in adder circuit with a feedback loop having a resistor Rlg.

 The positive input terminal of the operational amplifier P1 receives, through a resistor 23, a second voltage of constant value which is delivered by a voltage divider. This divider is composed of four resistors R20, R21, R22, and A3, two diodes D16 and D17 polarized in opposite direction and an AND logic gate Q1 whose two inputs are connected to the output terminal P17 of Figure 3 .

Depending on whether output P17 is in state O or state 1, the potentiometric network varies
If P17 = 1, D16 drives and bypasses R20. If P17 = 0, D17 leads and bypasses A3.

 It can thus be seen that the amplifier P1 superimposes on the variable voltage that is present on the emitter of MI a voltage step taken from two possible steps. This gives two ranges of frequencies.

 Finally, on the output terminal S7 of P1, a voltage is obtained which is analogous to the voltage across C7 but inverted to which a voltage step is added or subtracted.

 FIG. 5 shows a terminal S8 which makes it possible to add to the input voltage of P1 another constant voltage which saturates the amplifier P1. The role of this terminal Sg will be explained later.

FIG. 6 represents the circuits of the oscillator I of FIG.
This is composed of a window comparator R1, associated with a capacitor Cg. The input terminal S7 is connected to a terminal of the comparator R1 which makes it possible to adjust the level of the two thresholds of the comparator R1.

The comparator RI comprises a second terminal Slo, whose source and function will be seen later. When the terminal Slo is positive, shortly after powering up the apparatus, the output S11 of the circuit R1 is positive, the capacitor C8 is charged through R25. When the voltage across C8 exceeds the upper threshold of the comparator R1, the output S11 becomes negative and C8 is rapidly discharged through D18 and R26 until the voltage across C8 reaches the lower threshold of the comparator
R1. The output S11 then becomes positive again and the charge and discharge cycles of C8 follow one another. Thus, the assembly formed by the window comparator R1, the capacitor C8, the resistors R25 and R26 and the diode D18 constitutes an oscillator .

 The discharge durations C8 of the C8 condensate, which depend on the values of the resistors R25 and R26, are very asymmetrical, with R25 having a much higher resistance than R26. The frequency of the oscillations depends on the values of the maximum and minimum thresholds which are fixed by the voltage S7 which, as we have seen, evolves in sawtooth following arcs of exponential between two limit levels, which two levels can take two values different.

 The potentiometric divider R20, R21, R22, A3 which makes it possible to adjust the two levels between which the voltage S7 varies is set so that a first page of frequency of approximately 18 KHz to 30 Hz is obtained. second frequency range from about 25Khz to 40Khz. We thus obtain two frequency ranges which. partially overlap, which are scanned in ascending and descending order and at varying speeds depending on the slope of the exponential arcs.

The output terminal S11 of the comparator R1 is: connected to the input of a flip-flop S1 having two Q and Q output terminals of opposite polarity which are respectively connected to the positive poles of two comparator amplifiers T and U whose negative terminal is connected to a reference voltage. The falling edges of the voltage S11 switch S1
The flip-flop S1 has the function of routing the signal 51 either to the circuit T or to the circuit U thus making it possible to make the opposing half-waves of the signals S12 and S13 symmetrical. This switching takes place during the blocking of the signal transmission S12, S13 via the diodes D20 and D21. The signals S12 and S13 only appear when the signal emitted by S1 exceeds the value of the voltage of the signal. reference and that D20 and D21 are blocked
The two diodes D20 and D21 are conductive whenever the signal S14 is low in accordance with the signal S1.

 With the circuits described above, the signals S12 and S13 make it possible to generate a fixed frequency in the sound range audible by the man.

 FIG. 7 represents the power amplifier 3 and the transducer (s) 4.

 According to a characteristic of the invention, the power amplifier is composed of four transistors W X Y Z mounted in bridge and the transducers 4 are incorporated in a diagonal of the bridge. This particular amplifier is powered by the SI terminal (see Figure 1).

 The four transistors operate in a saturated blocked switching regime. The signals S12 and S13 are three-state signals, that is to say formed of high and low slots, separated by a zero level bearing which corresponds to the discharge phases of the capacitor Cg. The shape of these signals is shown in FIG.

When S12 is high, W is saturated, X is blocked. At the same time
S13 is low so Y is blocked and Z leads. A voltage is applied to the transducer 4 through W and Z.

 When on the contrary S12 is low and S13 is high, X and Y are conductive while W and Z are blocked and a reverse voltage of the previous one is applied on the transducer 4 through Y and X.

When S12 and S13 are simultaneously at the zero level, all the transducers W, X, Y and Z are blocked and the transducer does not emit, which saves the energy consumed without harming the efficiency of the apparatus,
Indeed, relatively high switching frequencies (between 18 kHz and 40 kHz) the transistors do not instantly reach their state of saturation or blockage.

 If the transistors in the diagonal opposite those which were conducting were saturated immediately, a large current could flow directly through the transistors without passing through the transducer which could cause heating and deterioration of the transistors. Zero level bearings of signals S12 and S13 eliminate this risk. At the terminals of the transducer 4, a periodic signal is obtained whose peak value is twice the supply voltage if the losses are neglected.

 Fig. 8 shows the circuits 8 of Fig. 1, i.e. the commissioning and test circuits.

 Since the ultrasonic power emitted is large and can be dangerous, it is advisable, during the commissioning of the device, to delay the emission of ultrasound to allow the operator to leave the emission field and then to emit an audible signal before the beginning of the ultrasound emission.

 The output terminal S3 of circuit II of FIG. 2 is connected to the input terminal of a flip-flop B2. At commissioning before, that the output S3 has become positive, the flip-flop B2 has taken a determined position.

The Q output of B2, which is connected to a terminal S16, becomes zero, and the Q output, which is connected to the output terminal Sg, goes high.

 This terminal Sg is connected to an input of the amplifier P1 (see FIG. 5) and saturates it by preventing the transmission of the variations of the voltage across C7 to the oscillator.

 The Q output of flip-flop B2 is connected to an input of an AND gate G3 whose second input is connected to terminal P12 of the shift register.

 At commissioning of the device all registers E1 to E6 are at zero level. The output P12 is therefore low and the output of the gate G3 is low. This output is connected through D23 and R42 to an input of an AND gate G4 whose other input is connected to a reference voltage.

The output S1O of the gate G4 is therefore at the low level. This output S10 is connected to a validation terminal of the comparator R1 (see FIG. 6) and it blocks it completely. It is necessary to wait for the second change of state of the sequence generator so that the output P12 becomes high and the output S10 becomes positive. At this moment the comparator R1 is unblocked and oscillates at a sound frequency, the state of the output S8 always saturating the amplifier P1.

 At the next state change, P13 becomes positive. P13 is connected on the basis of a transistor T2 which becomes conductive B2 flip-flop, S8 becomes low and S16 becomes high.

 Sg becoming low, the amplifier P1 is no longer saturated the voltage of the terminal S7 follows the fluctuations of the voltage across C7 and the oscillator emits variable frequencies.

 Terminal S16 is connected through R27, A4 and D1g to capacitor C8 (see FIG. 6) and adds a constant current to the charging current of C8. The charging time of C8 decreases, so the frequency of the oscillator increases and goes from a sound frequency to variable ultrasonic frequencies.

In addition, terminal Q of flip-flop B2 is connected through R41 and
D24 on the same input of the gate G4 as the output of the G3 ee the signal from the output Q of B2 replaces the signal from G3 which is closed until the next reset of the device switched on after disjunction.

We have seen so far the circuits which allow to vary the ultrasonic frequency in two frequency ranges
FIG. 8 also shows the circuit makes discontinuous emission possible by chopping it into intermittent pulses of non-uniform duration. This circuit works on the principle of majority logic.

 Various terminals P16, P18, P19 of the sequence generator are connected to the input terminals of P2 through the diodes D26, D27 and the resistors R37, R38, R39 and R40. During successive offsets of the registers E1 to E6, the output of P2 is sometimes positive, sometimes negative.

 The output of P2 is connected to the input of the gate G4 so that it allows or blocks the transmission of the signal coming from the output Q of B2 and makes the voltage in i sometimes positive, sometimes zero, thus blocking or releasing the 'oscillator.

 The S1O signal also disappears in the event of a trip that makes the diode D25 conductive.

 A test button T5 transmits through D28 a test voltage S15 which forces the gate G4 to become high and the voltage S10 then controls the operation of the oscillator R1.

 It can be seen in FIG. 6 that the test voltage SIs is connected through R28 on the basis of a transistor V which drifts the current arriving by SIs, R27 and A4 so that the signal emitted by the oscillator becomes an audible signal that testifies to the proper functioning of the device.

 Of course, without departing from the scope of the invention, the various components of the circuits which have just been described by way of example may be replaced by equivalent circuits fulfilling the same functions.

Claims (9)

1 - - Ultrasonic generator apparatus for removing animals  harmful substances comprising an electronic oscillator which delivers a voltage  periodic having a controllable frequency between 18Khz and 40Khz,  a power amplifier (3), one or more electro transducers  acoustic devices (4) which are excited by said amplified periodic voltage  (3), a door (2) interposed between the oscillator and the transducers  which ax the emission and means (5) to vary the frequency of the  said oscillator and for controlling said gate, characterized in that  said means (5) comprise a generator of pseudo-random sequences  (5) having a shift register (E1 to E6) whose last stage  (E6) is looped back on the first through a coincidence gate  (01, 02, 3, O4) whose inputs are connected to the outputs of  several floors of the register, so that each floor  of the register cyclically takes binary values that follow one another  within each cycle in an irregular and pseudo-random program order 2 - Apparatus according to claim 1, characterized in that said general  of semi-random sequences includes a capacitor (7)  associated with a window comparator (@ 1) and with a scale of resistances  (R10 to R15) which are alternately incorporated in the tank circuit  and discharging said capacitor (C7) by two series of lo  whose inputs are connected to the different stages (E1 to E6)  said shift register, which series of gates each have a  input which is connected to the output of said window comparator and which  validates alternately a surie then the other each time one of the two  thresholds of the comparator is reached, so that the voltage at  terminals of said capacitor (C 7) oscillates the sawtooths according to  exponential arcs whose slope is variable. 3 - Apparatus according to claim 2, characterized in that the output of said  NI window comparator is connected to the control terminal (S5) of the  shift of the registers (E1 to E6). 4 - Apparatus according to claim 3, characterized in that said means  (5) furthermore include a summing amplifier P1 having a terminal  connected to said capacitor (C7) and of which another terminal is connected  on a variable voltage divider bridge (R20, R21, R22 - A3) which  allows to add to the voltage across said capacitor (C7) den:  voltage steps of different value. 5 - Apparatus according to claim 6, characterized in that said oscillator  (13 includes a capacitor (Cun-) associated with a window comparator  (RI) with adjustable thresholds and the output of said totalizer amplifier  (P1) is connected to a terminal (S7) for adjusting the thresholds of said  tor. 6 - Apparatus according to claim 5, characterized in that said oscilla  tor (1) further comprises a flip-flop (S1) which is connected to the output  of said window comparator (R1) and whose two outputs (Q and Q)  are connected to the positive terminals of two amplifiers compared  (T and U). 7 - Apparatus according to claim 6, characterized in that said amplifi  power controller (3) consists of a bridge of four transistors  (W X Y and Z) mounted in switches whose bases are connected  two by two on the outputs of said amplifiers (T and U) and said  transducers (4) are interposed in a diagonal of said bridge. 8 - Apparatus according to claim 5, characterized in that said compara  window (RI) has a blocking terminal (6) and said  sitive comprises a logic set formed of logic gates (C3, C4, P2)  whose inputs are connected to different stages (P12, P13, P16, P18,  P19) of said shift register and whose output is connected to the  said blocking terminal (SIt) of the comparator (R1). 9 - Apparatus according to claim 5, characterized in that it comprises  means for incorporating into the charging circuit of said capacitor (C8)  a constant voltage step after a start-up period of such  so that said oscillator transmits on a sound frequency before transmitting  an ultrasonic frequency. Apparatus according to any one of claims I to 8, including  DC power supply circuits, characterized in that the  said circuits comprise a first capacitor Cl, at the terminals Sl of which  ispreluvée the supply voltage of the power amplifier  (3), a second capacitor C2, which is connected to the terminals of the first  through a diode D1, at the terminals S2 from which the voltage is taken  supply of electronic circuits and a comparator (il) which  compares a fraction of the voltage across the second capacitor  C2 at a fraction of the charge voltage of a third capacitor  C3 which is charging through a resistor Hi and the voltage at the terminal  output S3 of said comparator controls the prepositioning of cir  control of said generator of pseudo-random sequences and  blocks them in case of a short circuit.