FR2465381A1 - Vertical deflection frame sweep circuit - has reverse counter filled with successive binary words which triggers each sweep at end of count down to zero from each number - Google Patents

Abstract

The switched mode sweep circuit has a saw-tooth waveform generator (2) which derives the saw-tooth waveform from the linesweep return signal at a line transformer secondary and applied it to a vertical deflection coil load (1). The generator includes a parallel diode and thyristor (D,TH,) opposition and in series with the secondary. The thyristor is triggered immediately before the start of each line sweep return by a signal from a flip flop (D) triggered by a control signal (S) from a reverse counter. The control signal is generated when the counter counts down to zero from a preset binary number fed into the counter. The binary numbers are successively fed at the rate of the line return pulses from a dead memory which is programmable by a calculator and image sensor to provide an improved image.

Description

The present invention relates to a frame scanning circuit in switched mode and with digital control, used in particular: pt
In the television receivers.

 Such a weft scanning circuit is responsible for supplying the vertical deflection coils, or weft scanning coil, of a cathode ray tube, with a sawtooth current at the weft frequency. In the case of the French standard, this current has a period of 20 ms and a frame scan return duration of less than 1 ms.

According to the prior art, this current was first generated by circuits comprising a bir oscillator stage, which is synchronized at the frame frequency, an impedance matching link stage and an output stage, such as '' a class A polarized power amplifier or a class AB polarized complementary amplifier, then in a second step by switching circuits from the line return signal which appears at the terminals of the horizontal deflection coil or line scanning, of the cathode ray
These chopping circuits are generally, according to the prior art provided with two active switches such as thyristors, one ensuring the vertical scanning of the upper half of the screen of the cathode ray tube by charging a capacitor in parallel
stele with 1 "vertical deflection winding by pulses of voltage of decreasing durations in time and of polarity donations, and the other ensuring the sweeping of the lower half by swapping this capacitor by pulses of increasing durations in time and opposite polarity to the previous one.

The discharge of this capacitor in fact causes the flow of a sawtooth current through the vertical deflection winding.

 The French patent application filed under the number 78/22266 on July 27, 1978, in the name of the plaintiff, unlike previous devices with two monodirectional current channels, each in a different direction, a device with a single single channel, that is to say a single active switch mono directionnJ in voltage and bidirectional in current.

In fact, in this patent application, the vertical deflector is connected in series with a measurement resistor and a connecting capacitor whose value is sufficiently high for the voltage across the terminals of the assembly thus formed to keep the same polarity whatever or the direction of the current flowing through the vertical deflector. This set behaves sometimes in general
rator, sometimes as a receiver and is connected to the circuit to a single
switch active in switched mode, generator of endents signal
saw from the line scan return signal.

 The line sweep return signal is split using the active switch, bidirectional in current and unidirectional in voltage, connected in series with a winding of the line transformer as well as with an inductor not coupled to the line transformer, the assembly being mounted in parallel with a filtering capacitor, and the active switch being controlled by a pulse signal.

Each pulse of this signal occurs once in each period of the line scan return signal with a variable delay with respect to the line scan return pulse.

 This delay which is a function on the one hand of the characteristics of the receiver and on the other hand of the number of the line concerned in the image, will make it possible by acting on the opening and closing times of the active switch to generate a sawtooth signal with a shape suitable for good vertical scanning.

The present invention proposes to develop a digital control circuit generating such a signal.

In fact, the raster scan circuit in switched mode according to the invention comprising a circuit generating a sawtooth signal from the line scan return signal, to an active unidirectional switch in voltage and bidirectional and bidirectional in current, connected to the terminals of a load, comprising the vertical deflector, and having a voltage of predetermined polarity whatever the direction of the current passing through the deflector, and controlled by a control circuit, is characterized in that the control circuit comprises on the one hand, a binary downcounting circuit from a predetermined binary word displayed on its parallel inputs and at the rate of a predetermined clock frequency, the holding output of this downcounting circuit providing a signal for controlling the switch active at the end of the countdown, and therefore a stage generating a series of binary words, each being applied one after the other to the inputs pa of the downcount circuit at the rate of the line return pulses.

Other characteristics and advantages of the invention will emerge from the following description given by way of nonlimiting example and illustrated by the appended figures which represent
- Figure 1, a frame scan circuit in switched mode with digital control according to the invention;
- Figure 2, a block diagram of a digital control circuit of the scanning circuit according to the invention;
In FIG. 1, a charging circuit 1, comprising the vertical deflector Dy. Protected by a parallel resistor R, a connecting capacitor C and a current measurement resistor
L
Rm, is connected to the terminals of a circuit 2 generating a sawtooth signal.

 The vertical deflector Du comprises an inductor LU in series with a resistance Rv.

Circuit 2 generates in this vertical deflector DU a sawtooth signal from the line scan return signals coming from a secondary winding S1 of the line transformer
TL.

 The sawtooth current is obtained by cutting the periodic alternating signal at the line frequency generated in the secondary winding S1 of the line transformer TL.

 This cutting is carried out using an active bidirectional current and monodirectional voltage switch, connected in series with the winding S1 as well as with an inductance L5 not coupled to the line transformer, the assembly being mounted in parallel with a filtering capacitor CF.

The capacitor CF is of sufficiently high value to
that the alternating part of the voltage across its terminals is very
weak compared to the signal at the terminals of the winding S1, and therefore negligible.

 The active switch includes a diode D1 connected head to tail with a thyristor TH1, the cathode of which is connected to ground.

When a sufficient signal is injected on the trigger of the thyristor TH1, it closes, and the active switch thus formed can then be traversed by currents of opposite directions.

When the thyri-stor TH1 is open, the active switch has at its terminals a voltage of a determined polarity corresponding to the reverse voltage of the diode D1.

 During the frame sweep, the winding S1 of the line transformer TL delivers line return pulses of almost sinusodal shape. The capacitor CF constitutes with the inductance LU of the vertical deflector Du, a low pass filter very effective with respect to the line frequency, and the current passing through the deflector is practically equal to the average value of the current passing through the inductance LS.

 When the thyristor TH1 is kept open, the voltage across the inductor L5 is equal to the voltage across the secondary winding 51 minus the DC voltage across the capacitor CF as long as the diode is traversed by a direct current ; the voltage at its terminals being almost zero.

When diode D1 is blocked, this voltage across L5 is zero.

The current in the inductance L5 increases as long as the voltage across its terminals is positive, then decreases linearly until it reaches a zero value when it becomes negative.

The current passing through the deflector is equal to the average current passing through L5 always positive in the case where the thyristor
TH1 is kept open.

If the thyristor TH1 is closed at an instant preceding the start of line scan return start, the diode D1 which was blocked is then short-circuited.

The voltage across the inductor L5 is then equal to the line return voltage across the winding S minus the positive DC voltage across the capacitor CF.

The voltage across the inductor L5 is therefore constant and negative until the start of line return, where it begins to grow following a sinusoidal shape similar to that of the tensi-on across the winding.
After a positive maximum in the middle of the line scan return, this voltage decreases to a negative value at the time of the end of the line scan return, a value which it retains until the current in the circuit is canceled. , i.e. until the current in the inductor L5 is canceled.

The current in L5 and therefore the current in the vertical deflector decreases linearly to a negative -minimum, the instant of this minimum corresponding to the instant when the voltage across L5 vanishes before becoming positive. After this instant the current in the inductance L5 and therefore the current in the deflector increases, is canceled at the moment when the voltage across the terminals of
L5 is maximum and reaches a positive maximum, at the moment when the voltage becomes zero before becoming negative again. After this instant the current decreases linearly until it is canceled.

As the shape of the current in the inductor L5 depends on the instant of closure of the thyristor TH1, and the current in the vertical deflector being equal to the average current of the inductor L5, the sawtooth current suitable for weft scanning can be obtained by acting on the instant of closure of the thyristor TH
The more this is triggered at an instant ahead of the line return start instant, the more the average current in the inductor L5 decreases compared to its maximum value corresponding to the case where the thyristor TH1 is kept blocked.

 The thyristor TH1 is controlled by a digital control circuit according to the invention connected to the trigger of this.

thyristor TH1.

This digital control circuit includes a prepositionable binary downcounter circuit C01 which can for example be a binary prepositionable binary up-down counter logic circuit with two clock inputs, or several of these circuits cascaded so as to have a large number available. of entries.

 One of the clock inputs E2 of these integrated circuits makes it possible to control the countdown, the other (not shown) making it possible to control the counting.

This down-counter circuit can start the down-counting by drawing the binary word displayed on its inputs 1o> Ij, j representing the number of inputs depending on the number of bits of the binary word to be displayed. A prepositioning input E1 makes it possible to position the outputs Bo, B1 ... B j in the state of the corresponding inputs I, I1 ... Ij before the countdown begins on the basis of the binary digit which was displayed on the inputs Io ,
I I ..

1 ... d
The down-counting takes place at the rate of the frequency of the clock H connected to the clock input E2 of the down-counter circuit C01.

A holding output S supplies a pulse whose width is equal to the width of a pulse of the clock H when at the end of the countdown, the outputs Bo, B1 ... B j take a zero value.

 The prepositioning input E1 is connected to the output L of a shaping circuit 3.

An auxiliary secondary winding S2 of the line transformer provides line return pulses at the input of the shaping circuit 3 comprising a resistor R3 and two series diodes D2 and D3.

The signal available at output L, obtained by clipping the line return signal available at the terminals of the winding, provides on its rising edge a reference instant for the downcounter circuit C01.

 The holding output S is connected to the PR input of a flip-flop D. This PR input is a forcing input, when a high logic level is applied to the PR input, the Q output is also at the high logic level. The flip-flop D also has an input CL for resetting output 4 to zero.

 This output Q of the flip-flop D is connected through a divider bridge comprising the resistors R1 and R2, to the trigger of the thyristor TH1.

At the reference instant provided by the rising edge of the signal available at output L of the shaping circuit 3, the flip-flop D is at zero, and a binary word is applied to the in parallel tres Io, I1 ... I ., down counter C01. From this
J reference time the down counter counts down to the rhythm of the clock signal H applied to its input E2.

 At the end of the countdown, when the outputs Bo, B1 ... B j, arrive at the binary word zero, a pulse appears at the holding output S of the circuit Col. This pulse forces flip-flop D to a logic at output Q. The thyristor which, without signal in its trigger circuit was open, will then close. Indeed, the logic at output Q, adapted to the electrical characteristics of thyristor TH1 by resistors R1 and R2, will trigger this thyristor TH1.

The instant of closing of the thyristor TH1 with respect to the reference instant provided by the rising edge of the signal at output L is therefore dependent on the one hand on the value of the binary word displayed on the parallel inputs Io, I1 ... Ij, from the down counter
C01 and on the other hand the clock frequency H.

 If one chooses a determined clock frequency H, greater than the line frequency, the instant of closure of the thyristor TH1 with respect to the reference instant then depends only on the binary word displayed on the parallel inputs Io 'I1 ...

Ij.

 The instant of closing of the thyristor TH1 before each line return signal conditioning the shape of the frame deflection current, it is therefore possible to control the shape of this frame current by displaying on the parallel inputs a predetermined series of binary words. Each binary word of this sequence is displayed at the reference time determined by a rising edge of the signal at output L, this signal having for frequency, the line frequency.

 FIG. 2 represents a block diagram of a control circuit according to the invention.

 In this case, the downcounter circuit C01 whose input E2 is connected to the clock H and the output S to the flip-flop D, has its parallel inputs Io, I1 ... 1j connected to a generator stage of a series of binary words adapted to control the thyristor TH1, that is to say adapted to the shape of the frame scanning current necessary for good frame deviation.

Input 'E1 of circuit C01 is connected as shown
1 1 felt in FIG. 1, at the output L of the shaping circuit 3 and the output Q of the flip-flop D at the trigger of the thyristor TH1 through the resistance bridge R1, R2.

 This generator stage of the series of binary words comprises a counter circuit C02 whose clock input controlling the counting is connected to the output L of the shaping circuit 3-.

This counter C02, therefore counts at the rate of the output signal
L, i.e. at the rate of the line frequency.

 If this counter C02 is set to zero at the start of each image, the state of its outputs Q0, Q1 ... Qk 'k representing the number of outputs of this counter C02, is representative of the number of the line in progress. Each line of an image is thus numbered.

The outputs Q0, .. ... Qk of the counter C02 are respectively connected to the address inputs Ao, A1 ... A k of a read-only memory M.

 This read-only memory contains the series of predetermined binary words, its address position for example n containing the binary word relating to line n of the image.

 The outputs Do, D1 ... D j of this memory are connected to the inputs Io, Il ..> Ij of the down-counter C0l.

For example, for a line n of the image, the binary word contained in address position n in the read-only memory M will be displayed as inputs Io, Il ... Ij of the downcounter CO1. This one will start its countdown and arriving at zero will force the D flip-flop to one, thus triggering the thyristor TH1. For line n + l, the binary word contained in address position n + l in the read-only memory
M is displayed at the inputs Io, Il Iî. .1 d of the down counter C01, which begins to count down again, but from this new binary word, and arriving at zero, triggers the thyristor TH1, this cycle reproducing on each line.

 The memory M can be programmed by a computer associated with an image sensor. Indeed, the computer determines the series of binary words giving the image of better quality, then proceeds to the programming of each binary word at its address position.

 This digitally controlled switched mode frame scanning circuit is mainly used in solid state television receivers.

Claims (7)

R E V E N D I C A T I û N S  1. Weft scanning circuit in switched mode comprising a circuit generating (2) a sawtooth signal from the line scanning return signal, to an active switch unidirectional in voltage and bidirectional in current, connected to the terminals d '' a load (1), comprising the vertical deflector (Dv), and having a voltage of predetermined polarity whatever the direction of the current passing through the deflector (Dv), and controlled by a control circuit, characterized in that this circuit control comprises, on the one hand a downcounting circuit (C01) from a predetermined binary word displayed on its parallel inputs (I I1 .... Ij) and at the rate of a clock frequency (H), the output  J for retaining (S) this downcounting circuit providing a control signal from the active switch at the end of the downcount, and on the other hand a stage generating a series of binary words, each of these words being applied to the following one another on the parallel inputs (Io, Il ... I.) of the downcounting circuit J (C01) at the rate of the line return pulses. 2. frame scanning circuit according to claim 1, characterized in that the holding output (S) of the downcounting circuit is connected to the forcing input (PR) at a high logic level, of an electronic flip-flop (D), whose output (Q) is connected through a resistance bridge (R1, R2) to the control electrode of the active switch.  3. Frame scanning circuit according to one of claims 1 or 2, characterized in that the generator stage of a series of binary words comprises on the one hand a counting circuit (C02) at line frequency and on the other hand a read only memory (M), the 'counting circuit having its outputs (Q0, Ql ... Qk) connected to the address inputs (Ao, A1 ... Ak) of the memory (M) and providing for each line an address number, each address number corresponding to a preprogrammed binary word in the read only memory (M), so that for a given line the corresponding binary word in memory is displayed on the parallel inputs ( Io, He ... Ij) of the downcounting circuit (C0l).  4. Frame scanning circuit according to claim 3, characterized in that the read only memory (M) is programmed by an electronic computer associated with an image sensor, the computer determining the series of binary words providing the best image.  5. Frame scanning circuit according to one of claims 1 or 3, characterized in that the downcounting (C01) and counting (C02) circuits are synchronized at line frequency by a signal from a setting circuit. form (3) of the line return signal from a secondary winding (S2) of the line transformer (TL). 6. Frame scanning circuit according to claim 5, characterized in that the line return signal is clipped by the shaping circuit (3) which comprises two series diodes (D2> D3) and an input resistor (R3 ).  7. Video frequency receiver characterized in that it comprises a frame scanning circuit according to one of claims 1 to 6.