FR2463555A1 - Digital graphic information display using telephone line - uses memory storing full TV screen image with access inhibited during sweep portion to enable display - Google Patents

Abstract

The device for displaying on a t.v. screen and transmitting on a telephone line graphical information of a sketch or outline comprises a microprocessor (8) which receives from a phone line or graphic table digital information representing hand-traced co-ordinates of the sketch and stores it in a memory (1) in an address process effected by an address block (7). A sweep generator (6) produces a t.v. synchronisation signal and address signals which enable the block (7) to read the memory and store the contents in a register (4). The synchronisation signal of the generator is combined in an interface (5) with the register output signal (a luminance signal) to form a composite video signal displayed on the t.v. screen (502). The microprocessor registers the digital information in a RAM of the memory (9) for treatment according to a ROM stored programme. The treated information is then transmitted on a phone line (301) to a remote device for display.

Description

The invention relates to an apparatus for ins
write or erase, display and transmit a
graphic information.

We have described in the French patent application filed
on October 9, 1978 under No. 78 29463 by the Applicant for
"Device for registration and computer translation of a
drawn by capacitive effect between the tip of a ballpoint pen and
a network of conductive bars sequentially excited a "graphic tablet" on which a user executes by hand, by means of a pen with a conductive tip, a drawing or a
any inscription. This tablet is equipped with the circuit for converting the route into electrical signals representative of the coordinates of each of its points. Several operating modes are provided: continuous route; trace in cursor mode in which a block indicates the position; track in eraser mode in which the section of track covered by a pad is erased; Finally, an "erase" mode makes it possible to erase the entire trace already displayed.

The present invention relates to a device, intended to cooperate with a graphic tablet of the aforementioned kind or
with a similar device, for permanent display
diat of the trace on the screen of a commercial television receiver in the form or it occurs in writing, of its instantaneous transmission on a public telephone line and of
the receipt, on this same line, of a route executed at dis
tance on another graphics tablet, the plots executed lo
at a distance and overlapping on the screen.

The solutions provided so far to this kind of pro
pale are only partial and do not lead to the realization of a compact device, relatively inexpensive and allows
both a permanent display of the complete image on a television screen of the "general public" type, while allowing the display
simultaneous of the trace made locally and of another trace exe
cut from a distance.

The device according to the invention is mainly
characterized in that said memory is organized to have
sufficient capacity to hold graphic information
corresponding to a complete television picture covering
the whole screen of a consumer type receiver, addressing
memory being carried out in such a way that there is a one-to-one correspondence between the locations of the memory and the points of the trace and that said means comprise a microprocessor, interfaces between the microprocessor, the recording apparatus and a modem associates with the telephone line, a scanning member capable of permanently generating a television signal, the useful information of which is supplied by reading said memory and means for prohibiting access to memory by the microprocessor during predetermined fractions of the duration of each television line, sufficient for the memory access by the scanning member during said fractions to permanently display the graphic information on said screen.

 According to a preferred embodiment, the memory is orangled in at least one plane comprising three pages of 16 K bytes each, bytes O to 95 of each television line being distributed between the three pages, in order O, 3, 6.93 for the first, 1, 4, 7..94 for the second and 2, 5, 8..95 for the third, the scanning unit performing the reading in pa allele of three bytes at a time in the three respective pages while the microprocessor performs selective reading of the memory page by page and, in each of the pages of the memory, the television lines O to 511 being distributed in the order O, 2, 4, 6 - 1, 3, 5, 7 - 8, 10, 12, 14 ... i.e. so that a group of four lines of successive odd numbers always succeeds a group of four lines of numbers intercalary peers.

 Other characteristics, as well as the advantages of the invention, will become clear with the aid of the description below.

In the accompanying drawing:
Figure 1 is a general block diagram of a device according to the invention;
FIG. 2 schematically represents the signals generated by the synchronization member that includes such a device;
Figure 3 is a more detailed diagram of a part of the device of Figure 1, comprising in particular, the memory, the video register and the multiplexing and arbitration bodies;
Figures 4 and 5 show the signals (POUB, DAP,
MR, CYMI) of arbitration between the microprocessor and the scanning member, respectively when the request for access from the microprocessor to memory (DAP) occurs during a positive slot of the POUB segment and during a negative slot;
FIG. 6 represents the signals (RAS and CAS) for refreshing the rows and columns of the image memory;
FIG. 7 represents the decoder of the addresses provided by the microprocessor;
FIG. 8 represents the organization of the address space of the microprocessor;
Figure 9 shows the detail of the arbitration circuit;
FIG. 10 represents the clock generator that the scanning member comprises;
Figure 11 shows the sweep generator;
FIG. 12 represents the signals corresponding to a television line;
FIG. 13 represents the INVERSION signal and the HLC and HL clock signals used in the sweep generator; and
Figure 14 shows a line doubling circuit.

In FIG. 1, there is shown - a memory 1 intended to contain a graphical image supplied,
either by a graphic writing tablet, through
diary of an interface 2 having an input 201 connected to the ta
chard, either by a modem, via an interface 3
which is used both for transmission (line 301) and for reception
(line 302) - a register 4, the input of which is connected to an output of the
memory 1 and whose output is connected to an interface of
video output 5, itself connects to a TV monitor
502 by a line 501.

- a television scanning signal generator
and clock 6 connected, on the one hand to the output interface
5 (link 620), on the other hand to a block 7 playing the role
control unit and address multiplexing of the
image memory 1 (connection 61).

- a central microprocessor 8, connected by a data bus 801
to memory 1, to program and data memory 9 and
to interfaces 2 and 3 and 1 by an 802 address bus, to the block
7, memory 9 and an address decoder 10. The latter
is connected to blocks 2, 3, 7 and 9 and allows their addressing.

- an error detector circuit 11 and a trans buffer block
mission 12, interspersed on the data bus between the process
sor 8 and interface 3.

 The processor 8 acquires coordinates XY of points (accompanied by an order for registration or erasure), coming either from the -tablette, or from a telephone line and writes them (or erases them) in the memory d image 1 after an addressing process performed by block 7.

 The content of the picture memory is permanently displayed on the television monitor.

To this end, block 6 generates, as will be explained below, a television synchronization signal (waveform A in FIG. 2), address signals Ao ... An, then
An + 1 ... A2n etc (symbolized in B) which allow reading, by block 7, of the image memory. The content thus read (link 100) is stored in register-4, where it is serialized under the command of block 6 ("HPOINT" signals).

 The output signal from register 4, shown by way of example in C, constitutes the luminance signal.

 The interface 5 superimposes signals A and C, to give a "video-composite" signal D ~ D allowing the control of the television monitor.

 The microprocessor also records the data in a part of the RAM type of the memory 9, for subsequent processing carried out according to a program contained in a part of the ROM type of said memory.

 After appropriate processing, the data originating from the tablet is also transmitted over the telephone line 301 for a remote display by a device identical to that of FIG. 1.

 The speed of arrival of the graphic information (XY coordinates) being very high (for example 1000 points per sec.) It is necessary, before their transmission on the line, whose transmission capacity is low, on the one hand to compact them (which is done by the processor 8 using a program contained in the memory 9), on the other hand to pass them through the buffer 12, as will be explained below.

 On reception, the information passes through the buffer 12 in the other direction and is effectively acquired only after examination by a block 11 which invalidates them when their structure does not conform to that which should normally result from the operation of compaction. This consists in making a certain selection of the points whose coordinates will be effectively transmitted, by applying a determined algorithm, which is not part of the invention.

 From the moment when block 11 detects an error and until the arrival of new coded information corresponding to the indication that the pen has ceased to be in contact with the tablet (end of line), the information is no longer displayed. This process avoids the display of outliers.

 It will be noted that the memory 1 has, according to a particular feature of the device described, a sufficient capacity to contain the information corresponding to a complete television image covering the entire screen of a consumer monitor. In practice, we will preferably adopt a display capacity corresponding to 768 points X 512 lines.

 FIG. 3 represents the organization of memory 1.

The information to display corresponds to 48 K bytes (K = 1024). Memory 1 is broken down into three pages 101-102-103 of 16 K bytes each. Each page has 16 K words and the corresponding bytes of a television picture broken down into lines numbered from 0 to 511 have been represented in successive words, each line being itself broken down into bytes numbered from 0 to 95 .

 We see that the bytes of line 0 are distributed as follows on page 101: bytes 0, 3, 6, 9 ... 93; page 102: bytes 1, 4, 7 ...

94; page 103: bytes 2, 5, 8 etc..95. The lines are themselves distributed as follows: 0, 2, 4, 6; 1, 3, 5, 7; 8, 10, 12, 14; 9, 11, 13, 15 etc. The advantage of this distribution will be explained below.

The video register (4 figure 1) is broken down into three registers 401, 402, 403 (figure 3) respectively linked to pages 101, 102, 103 and allowing the reading in parallel of three bytes in the three respective pages, followed by their serialization by 24 H POINT clock strokes supplied by block 6,
As will be explained below, the registers 401-402-403 also receive loading signals CHGRV.

 Furthermore, pages 101, 102, 103 are respectively linked to three locking registers 104, 105, 106 which allow selective reading page by page of the bytes under the control of the microprocessor. For this purpose, their control inputs 1040, 1050 and 1060 are connected to outputs 1041, 1051 and 1061 respectively1 of the decoder 10. The loading of these registers with locking by the content of the memory is carried out under the command of signals CHGP developed by an arbitration circuit 721 as will be seen below.

 Block 7 (FIG. 1) comprises a multiplexer 70 which switches in parallel to the three pages 101-102-103 (bus 71) of the addresses coming either from the processor 8 (bus 802) or from the scanning device 6 (bus 61 ). This multiplexer is controlled by a POUB signal ("processor or scanning") supplied by a line counter 62 which is part of block 6 and will be described below.

 The data bus 801 is connected (at 8010-8011-8012) to the inputs on pages 101 to 103 for recording data in memory. Registration is selective and validated, page by page, by three signals WRITE P1, WRITE P2 and WRITE P3 supplied to outputs 1001, 1002 and 1003 of detector 10.

 The signals on the six outputs of the decoder 10 are generated following a decoding of the fourteen addresses supplied through the bus 802 by the microprocessor.

 The write signals WRITE P1, WRITE P2, WRITE P3 are validated by a first auxiliary signal (R / W: read-write) supplied by the microprocessor and by a second auxiliary signal CYMI supplied by the arbitration circuit 72 which is part of the block 7. The circuit 72 is itself controlled by a DAP signal supplied by the decoder 10 and interpreted as a request for access from the processor to the image memory. The circuit 72 also receives the POUB signal and provides an MR signal (temporary shutdown of the microprocessor), as will be explained below.

A clock 6300, which is part of block 6, excites the line counter 62 which generates, in addition to the signal A above on its output 620, the signal POUB (FIGS. 4 and 5f composed of slots of equal duration (l / 80th TV line for example pie) alternately positive and negative
The positive slots are assigned to access the scanning system in the image memory for reading and refreshing the latter, while the negative slots # are assigned to microprocessor access 8 Nevertheless, the DAP signal can arrive at any time.

When the DAP signal arrives, the circuit 72 generates an MR signal which blocks the action of the microprocessor until the arrival of the next negative slot of the POUB signal. At this time, the circuit 72 launches an image memory cycle (CYMI3, the disappearance of which, in turn, leads to that of the signal M, therefore the thawing of the microprocessor. Memory 1 is produced with integrated circuits of the dynamic memory type and must so be refreshed periodically
To this end, a decoder circuit 73 which is part of the block 7 performs an appropriate logical combination of the states of the intermediate stages of the counter 62 and thus generates two slots RAS and CAS (FIG. 6), whose rising edges coincide with those of the POUB signal. and whose durations are respectively 1/4 and 3/8 of the duration of the slots of the POUB signal.

These signals are used #respectively for refreshing the rows and columns of the memory 10 The circuit 73 also provides an FCM signal (end of memory cycle: FIG. 6), as will be seen below.
The multiplexer 70 receives the 802 addresses on 14 bits and transmits them to the memory 1 on a 7 bit bus 71 (the memory having only seven address entries) by means of a time sequencing ensured by the signal value RAS.

 When RAS = 1 the multiplexer transmits the seven least significant bits of the addresses When RAS = 0, the multiplexer transmits the seven most significant bits of the addresses.

 The advantage of constituting the memory 1 in three pages is to be able to read three words at the same time in parallel, which space in time the accesses to the memory of the scanning member, therefore to give the microprocessor access to the memory in the interval of free time between two accesses of the scanning device without for this, altering the displayed image. (The usual access time of a byte in a memory of this kind is of the order of 500 ns, which corresponds substantially to the time allocated to the display of eight points of the television image).

 Viewed from the side of the scanning device, the image memory is thus organized in 24-bit words, while, seen from the side of the microprocessor (selective addressing), it is organized in 8-bit words. We have seen, with reference to FIG. 3, that each page of the memory is organized into 128 sub-pages, each comprising four blocks of 32 words. Each block of 32 words corresponds to a third of a television line. In each subpage are represented four successive even or odd lines. This nested organization of the memory is justified by the need to refresh the dynamic memories with which the memory 1 is produced, on the 7 least significant bits (128 positions of memory at least every 2 ms, a result which is obtained automatically, since the duration of a television line is approximately 64 microseconds (4 x 64 = 256 Ss (2mus).

In FIG. 7, the decoder 10 is shown in more detail in the case where three colors V (green) are used,
B (blue) and R (red) for constituting an image.

 A first stage 1100 detects the microprocessor access intention in one of the three pages of the memory 1 and processes the selection signals of various organs, such as the 2-3-10 interfaces (signals synbolized by an output 1101) and a signal for selecting a control register 730 which is part of block 7. In this register, the microprocessor writes (signal R / W) that of the planes of the image memory in which it wishes to display. In fact, the memory 1 is then produced in several planes each comprising three pages organized as described above. In the example considered, there will be three planes corresponding to the three RBV colors. The RBY information supplied by the register 730 is applied to a second stage 1110 of the decoder, which also receives the R / W CYMI and page selection signals. (P1, P2, P3) and elaborates, for each memory plane, write selection signals, which correspond to the signals supplied on outputs 1001 to 1003 in FIG. 3, and selection signals in read of the locking registers , which correspond to outputs 1041, 1051 and 1061 in FIG. 3, it being understood that, in the device of FIG. 7, three groups of signs are provided, for example 1001 R, 1001 V, 1001 B, corresponding to the three respective colors. Stage 1110 also processes the DAP signal already mentioned, whether P1, P2 or P3 are active.

 The register 730 also receives from the microprocessor, via the bus 801, an order to erase the image memory and transmits it to stage 1110. The activation of this signal EFF causes the validation in parallel, in writing, of all signals of type 1001, 1002, 1003, which allows, for the erasure of the image memory, the recording of the erasure information (writing of zeros), in parallel in the three pages. The erasing time thus corresponds to the duration of 16 K cycles alone lied in place of 48 K.

In FIG. 8, the organization of the microprocessor address space has been represented with three RGB image memory plans each consisting of three pages 101, 102, 103 of 16 K words. Note that the microprocessor, whose addressing capacity is 64 K words of 8 bits, can access in the color planes of the image memory (after selection by the command register) as in its own space addressing
RAM - ROM.

 In FIG. 9, there is shown in detail a preferred embodiment of the arbitration circuit 72 of FIG. 3. It comprises three flip-flops type D 721 - 722 - 723, two inverting amplifiers 724 and 725 and two OR gates 726 and 727.

 The flip-flop 721 samples the request for access to the DAP processor at the rate of the microprocessor's clock HP. The Q output of this flip-flop sets the MR output of flip-flop 723 to zero and, via gate 726, presents a signal 1 at input D of flip-flop 722. The Q output of the latter is initially in state 0. The arrival of a negative edge of the POUB signal causes the output Q of the flip-flop 722 to go up to state 1 and signifies the launching of an image memory cycle for the processor. subsequent arrival (for example, 600 nanoseconds later) of the FCM signal, the duration of which is very short (for example 100 nanoseconds) allows, via the gate 727 and the inverter 725, on the one hand, the reset to 1 of the output Q of flip-flop 723, (return to initial condition of MR) on the other hand, return to initial condition (0) of the output Q of flip-flop 722.

The CHGP signal from gate 727 is applied to registers 104 to 106 (Figure 3) to sample the data presented by the image memory for later output
on the data bus. The duration of this signal depends on the transit time in organs 723 and 727.

The nesting of bytes and lines in the image memory, as defined above with reference to FIG. 3, is obtained in the following manner
The 14-bit addresses (from the sweep generator or the microprocessor) are matched to the input of the multiplexer 70, the output addresses (distributed as indicated above, in two sequences of seven addresses) images in the image memory, with the following correspondence table
0-0; 1-1; 2-2; 3-3; 4-4; 5-7; 6-5; 7-6; 8-8; 9-9; 10-10; 11-11; 12-13 and 13-13, the first digit representing the entry address and the second, the exit address.

We will now describe, with reference to FIG. 10, the clock generator 6300 that comprises the block 6 of FIG. 1. A standard signal of 30 MHz is applied to three flip-flops type JK 64 and 63-65 which respectively provide frequencies of 15 MHz and 10 MHz. The 15 MHz frequency is used as the HPOINT clock signals (Figure 3). The frequency of 10 MHz, obtained at the output of flip-flop 65, is the frequency
HBA (figure 3), which is used in the line counter 62 (figures 3 and 5) which provides, in particular, as will be explained below, signals CPO, CP1, CP2 and POUB whose coincidence is produced by a gate AND 66. The output of gate 66 is applied to a NAND gate 67 whose other input is connected to the output of a NAND gate 68 which receives the signal QO coming from the flip-flop 63 and the signal HBAL. The output of gate 67 is, after inversion at 69, applied to the input of a NAND gate 690 which also receives the HBAL signal. The output of door 690 is connected to the input of flip-flop 64.

 At the exit of gate 67, the signal CHGRV is obtained (FIG. 3). The organs 67, 69 and 690 ensure the phase calibration of HPOINT on HBAL.

 Note that. you could also use w to get the HPOINT signals, the HBAL output. In this case, the television line will have 512 points instead of 768.

We will now describe, with reference to FIG. 11, the scanning generator that comprises the block 6 of FIG. 1. We see that the counter designated by the number 62 in FIG. 3 receives signals HBAL and LOADL, which are also applied to a counter 621; counters 62 and 621 are synchronous and connected in series
The counter 62 operates as a divider by 64 and its six division stages respectively supply signals CP0,
CP1, CP2, POUB, ADB0 and ADB1.The counter 621 functions as a divider by 10 and its four stages respectively supply signals ADB2, ADB3, ADB4 and PL The signals ADB0 to ADB4 constitute the GiNq first least significant addresses of the bytes in the picture memory, corresponding to the thirty two bytes of a television line
If we consider the outputs ADB0 to PL inclusive, we define forty states 0 to 39 which are represented in FIG. 12, on the first line. The decoder 622, advantageously produced using a programmable memory, allows the synthesis, from these states, of the complete signals corresponding to a television line
ALL line ignition (reading and display time
memory contents chage
line)
TOP L: line top (signal of period 64 s, having
4.8 s negative slots
TOP EG: equalization top ("pre" and "post": signal
period 32 # s corresponding to
half a line and having
2.4 s negative slots
TOP DT: 32 s period signal with slots
4.8 # s.

 These signals, shown in FIG. 12, are applied to a multiplexer 629. As will be explained below, this allows, by their adequate time multiplexing, the production of a complete synchronization signal (SYNC COMP). A flip-flop 630 is used for the elimination of hazards.

 The signals TOP EG and PL are applied to the respective inputs CK and D of a flip-flop D 623 which generates, at its output, a square signal HLC.

The multiplexer 629 receives two signals VALEG and VALDT supplied by a decoder 624, advantageously produced in the form of a programmable memory and receiving seven of the outputs (ie ADB 6 to ADB 12), from a binary counter 625 operating as a divider by 512. The 624 decoder also provides an output
INVERSION applied to an input of an AND gate 632, the output of which is applied to an input of an exclusive OR gate 631, the other input of which receives the HLC signal. The output of the gate 631 is connected, on the one hand to an additional input of the decoder 624, on the other hand, to an input of a divider by two 626 and finally, to the clock input of the counter 625.

 A LOAD signal T is applied to a loading input of the counter 625 and to the counter 626. A reset output of the decoder 624 is connected to a reset input of the counter 625. The output of the counter 626 provides an ADB5 signal applied to the other entrance to door 632.

 The LOAD L and LOAD T signals (Figures 10 and 11) are supplied by an external circuit allowing the device's scanning generator to be controlled by - an external television signal, by forcing the counters to adequate values .

The outputs ADB 5 to ADB 12 constitute the "most significant" part of the scanning addresses, the display of the memory content being carried out only on 256 lines, which correspond to the lines visible on the screen. To produce a television picture, it is necessary to divide by 625, corresponding to the two even and odd fields, each of 312.5 lines. This division is obtained by means of the counter 625 which defines 313 states and whose clock input circuit 631 allows, by an adequate inversion of the HLC signal, the counting of 313 line periods, followed by the counting of only 312 periods, although, in both cases, the counter goes through its 313 states.Just do this by reversing the HLC phase, then bringing it back to the initial value, as shown in Figure 13, in which we see that, over a duration corresponding for example to fourteen pulses each having the duration of a television line, the clock HL having undergone phase fiddling supplies fifteen pulses.

The phase inversion controlled by the INVERSION signal from the decoder 624 and by the ADB signal 5 indicating the presence of a frame of even or odd number: the beginning and the end of the signal
INVERSION must take place outside the display period of the useful lines and outside the post and pre-equalization pulses specific to the television signal.

The VALEG signal corresponds over time to the pre and post-equalization pulses, during which the multi plexer 629 transmits the TOP EG signal at its output. The signal
VALDT corresponds to the frame pulses, during which the multiplexer 629 transmits at its output the signal TOP DT corresponding to the synchronization pulse in the frame.

 It will be noted that by writing the contents of the programmable memories 622 and 624 differently it is possible to produce signals corresponding to different television standards.

 It will also be observed that the phase-matching described above makes it possible to produce the frame counter by means of a single decoder.

 The described scanning device allows permanent refreshment of the dynamic memories which make up the image memory, even during the durations corresponding to the lines not viewed and the permanent display, with cyclic refresh of the image on the screen. .

 FIG. 11 shows that the last output of the counter 625 is connected to an input V of the decoder 624. This makes it possible to activate the decoder 624 only during the display of 256 lines per frame, which reduces the size of the decoder.

 In FIG. 14, a circuit has been shown which makes it possible to simultaneously display two (or more) contiguous points of the same line in order to produce lines of variable width for a single point written in the memory. This circuit is part of the video interface 5 (Figure 1). It comprises a flip-flop D 50 which receives, on a clock input, the signal HPOINT already defined and, on an input D, the signal coming from the video register 4 (luminance). An OR gate 51 provides at its output a double width pulse.

 To avoid flickering of a displayed line, each point to display is lit simultaneously on the line considered and on the following line: each point is therefore displayed on an even and odd frame. This is achieved by suitable programming.

 We have seen, with reference to FIG. 1, that the information passes through a buffer 12 before being transmitted on the line. The speed of information arriving in the buffer is much higher than the speed of transmission. When the microprocessor gives the order to erase all the image memory, it is erased almost instantaneously locally, but, at a distance only after a delay which can be inconvenient, as a result of the late transmission of the order of erasure.

To overcome this defect, the program is arranged so that, as soon as an image erasure order is prepared, it is immediately transmitted over the telephone line, the information preceding it being canceled.

 It goes without saying that various modifications can be made to the assembly described and shown, without departing from the spirit of the invention.

Claims (14)

 1- Device for displaying and transmitting graphical information generated by an automatic recording and numbering device for a plot which provides digital data comprising the coordinates of the points successively plotted manually by an operator, said device comprising a memory intended to contain said graphic information and means for displaying said graphic information on the screen of a television receiver and for transmitting said graphic information on a telephone line, characterized in that said memory is organized to have a sufficient capacity to contain the graphical information corresponding to a complete television image covering the entire screen of a consumer type receiver, the memory being addressed so that there is a one-to-one correspondence between the memory locations and trace points and that said means includes a microprocessor, interfaces these between the microprocessor, the recording device and a modem associated with the telephone line, a scanning member capable of permanently generating a television signal, the useful information of which is provided by reading said memory and means of prohibit access to the memory by the microprocessor for predetermined fractions of the duration of each television line, sufficient for the memory access by the scanning member during said fractions to make it possible to permanently display the information graphic on said screen without alteration due to microprocessor access.  2- Device according to claim 1, characterized in that its display capacity corresponds to 512 lines of 768 points or 512 lines of 512 points.  3- Device according to claim 2, characterized in that said memory is organized in at least one plane comprising three pages of 16 K bytes each, bytes O to 95 of each television line being distributed between the three pages, in the order 0, 3, 6 ... 93 for the first, 1, 4, 7 ... 94 for the second and 2, 5, 8 ... 95 for the third, the scanning member performing the reading in parallel three bytes at a time in the three respective pages, while the microprocessor performs the selective reading of the memory page by page.  4- Device according to claim 3, characterized in that in each of the pages of the memory, the television lines O to 511 are distributed in the order 0, 2, 4, 6 - li 3, 5, 7 - 8, 10, 12, 14 ...., that is to say so that a group of four lines of successive odd numbers always succeeds a group of four lines of interspersed even numbers,  5- Device according to one of claims 1 to 4, characterized in that said means of periodically prohibiting access to memory by the microprocessor comprises means of generating a first signal (POUB) formed of positive slots and alternating negative slots each having the duration of an eightieth television line, means of generating, on each arrival of a request for access from the processor to the memory, a second signal (MR) which freezes the action of the microprocessor until the arrival of the next negative slot, during which access to memory will be reserved for the microprocessor and means to launch a memory cycle (CYMI) whose disappearance in turn causes that of said second signal (MR).  6- Device according to claims 4 and 5, charac terse by means of generating a third and a fourth signal in slots whose rising edges coincide with those of said first POUB signal and whose durations are respectively equal to 1/4 and 3 / 8 of the duration of the slots of said first signal, said third and fourth signals respectively serving to refresh the rows and columns of the image memory.  7- Device according to claim 3, characterized in that said scanning member comprises, for # the generation of a first clock signal (HPOINT) which allows the serialization of the three bytes read in parallel and a second signal clock (HBAL) intended to define the cadence of the scanning lines, a first flip-flop which generates a signal of 15 MHz by division by two of a standard frequency of 30 MHz, and a second and a third flip-flops connected in cascade, the third flip-flop supplying a 10 MHz signal and a logic circuit making it possible to perform phase matching between the two signals at 10 and 15 MHz.  8- Device according to one of claims 1 to 7, characterized in that said scanning member comprises: a line counter arranged to supply address signals corresponding to the first five least significant addresses of bytes in the memory of picture ; a first decoder associated with said line counter and arranged to supply the line ignition signals (ALL), the line pulse (TOPL), the equalization pulse (TOP EG) and a pulse (TOP DT) in the frame of a television picture; a multiplexer which performs the time multiplexing of the signals from the first decoder in order to generate a complete synchronization signal (SYNC COMP); a frame counter arranged to provide address signals corresponding to the most significant of the scan addresses; a second decoder associated with said frame counter and supplying said multiplexer with the signals (VALEG and VALDT) necessary for the execution of said time multiplexing and means, associated with said frame counter, which is arranged to define 313 successive states, in view of it allow division by 625 corresponding to two fields, even and odd, of 312.5 lines each.  9- Device according to claim 8, characterized in that said means associated with the frame counter effect the phase inversion of the clock input of said counter and, respectively, the restoration of the initial phase, at the start and at the end of an inversion signal supplied by the second decoder.  10- Device according to claim 9, characterized in that the frame counter and the second decoder are agencies so that the latter is only active for the display of 256 useful lines per frame and that said start and said end of the signal d inversion occurs outside the display period of the useful lines and outside said equalization pulses.  11- Device according to one of claims 8 to 10, characterized in that said first and second decoders are made by means of programmable memories.  12- Device according to one of claims 1 to 11, characterized by means of simultaneously displaying at least two contiguous points of the same line for a single point written in the memory and simultaneously lighting each point to be displayed on the line considered and on the next line.  13- Device according to one of claims 1 to 12,  characterized by a buffer memory interposed between the microprocessor and the modem interface and by means, when the microprocessor gives the command to erase all the image memory, to ensure the immediate transmission of said command on the line phone call and the cancellation of all the information preceding it in the buffer memory.  14- Device according to one of claims 1 to 13, characterized by means of making a certain selection of points whose 'coordinates will be effectively transmitted over the telephone line, for the purpose of compacting the graphic information and by means , between the microprocessor and the modem interface, to invalidate the graphic information received on the telephone line when its structure does not conform to that which should normally result from said compacting, said invalidation means being arranged so that the information is no longer displayed until the arrival of coded information corresponding to an end of line.