FR2337398A1 - Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption - Google Patents

Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption

Info

Publication number
FR2337398A1
FR2337398A1 FR7540418A FR7540418A FR2337398A1 FR 2337398 A1 FR2337398 A1 FR 2337398A1 FR 7540418 A FR7540418 A FR 7540418A FR 7540418 A FR7540418 A FR 7540418A FR 2337398 A1 FR2337398 A1 FR 2337398A1
Authority
FR
France
Prior art keywords
flops
flip
current consumption
cross coupled
coupled transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7540418A
Other languages
French (fr)
Other versions
FR2337398B1 (en
Inventor
Bernard Denis
Jean-Francois Joudinaud
Jean-Paul Rousseau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
Original Assignee
Compagnie IBM France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS filed Critical Compagnie IBM France SAS
Priority to FR7540418A priority Critical patent/FR2337398A1/en
Priority to DE19762654460 priority patent/DE2654460A1/en
Publication of FR2337398A1 publication Critical patent/FR2337398A1/en
Application granted granted Critical
Publication of FR2337398B1 publication Critical patent/FR2337398B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Circuitry is provided for diode-coupled, cross-connected bipolar transistor memories to minimise the current consumption and improve the speed of response during the monitoring process. The facility enables a greater number of flip-flops to be used in parallel. The memory cell consists of two cross-connected inverters over diodes and coupled load transistor. Schottky diodes are coupled into bit lines connected to AND gates. When write in occurs, a select pulse is applied and a transistor switches to allow the word line level to go low. A further transistor switches off. The AND gates are enabled to allow data to be entered into the memory cell.
FR7540418A 1975-12-30 1975-12-30 Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption Granted FR2337398A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR7540418A FR2337398A1 (en) 1975-12-30 1975-12-30 Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption
DE19762654460 DE2654460A1 (en) 1975-12-30 1976-12-01 CIRCUIT TO INCREASE THE WRITING SPEED FOR MEMORY CELLS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7540418A FR2337398A1 (en) 1975-12-30 1975-12-30 Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption

Publications (2)

Publication Number Publication Date
FR2337398A1 true FR2337398A1 (en) 1977-07-29
FR2337398B1 FR2337398B1 (en) 1980-05-30

Family

ID=9164452

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7540418A Granted FR2337398A1 (en) 1975-12-30 1975-12-30 Write response circuit for flip-flops - has gate providing quick response of cross coupled transistor flip-flops and reduced current consumption

Country Status (2)

Country Link
DE (1) DE2654460A1 (en)
FR (1) FR2337398A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021143A2 (en) * 1979-06-28 1981-01-07 International Business Machines Corporation Method and circuit for selection and for discharging bit lines capacitances in a highly integrated semi-conductor memory

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570993A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Memory circuit
SE9002558D0 (en) * 1990-08-02 1990-08-02 Carlstedt Elektronik Ab PROCESSOR

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021143A2 (en) * 1979-06-28 1981-01-07 International Business Machines Corporation Method and circuit for selection and for discharging bit lines capacitances in a highly integrated semi-conductor memory
EP0021143A3 (en) * 1979-06-28 1981-01-14 International Business Machines Corporation Method and circuit for discharging bit lines capacitances in an integrated semi-conductor memory, especially for the mtl technique

Also Published As

Publication number Publication date
FR2337398B1 (en) 1980-05-30
DE2654460A1 (en) 1977-07-07

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Legal Events

Date Code Title Description
ST Notification of lapse