FR2170438A5 - - Google Patents

Info

Publication number
FR2170438A5
FR2170438A5 FR7244246A FR7244246A FR2170438A5 FR 2170438 A5 FR2170438 A5 FR 2170438A5 FR 7244246 A FR7244246 A FR 7244246A FR 7244246 A FR7244246 A FR 7244246A FR 2170438 A5 FR2170438 A5 FR 2170438A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7244246A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR2170438A5 publication Critical patent/FR2170438A5/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7244246A 1971-12-23 1972-12-04 Expired FR2170438A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21162071A 1971-12-23 1971-12-23

Publications (1)

Publication Number Publication Date
FR2170438A5 true FR2170438A5 (fr) 1973-09-14

Family

ID=22787680

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7244246A Expired FR2170438A5 (fr) 1971-12-23 1972-12-04

Country Status (5)

Country Link
US (1) US3764996A (fr)
JP (1) JPS5236658B2 (fr)
DE (1) DE2260353C2 (fr)
FR (1) FR2170438A5 (fr)
GB (1) GB1353311A (fr)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
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US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
JPS532296B2 (fr) * 1973-03-19 1978-01-26
US3942155A (en) * 1973-12-03 1976-03-02 International Business Machines Corporation System for packing page frames with segments
FR122199A (fr) * 1973-12-17
US4087852A (en) * 1974-01-02 1978-05-02 Xerox Corporation Microprocessor for an automatic word-processing system
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
JPS5615066B2 (fr) * 1974-06-13 1981-04-08
US3958222A (en) * 1974-06-27 1976-05-18 Ibm Corporation Reconfigurable decoding scheme for memory address signals that uses an associative memory table
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4020470A (en) * 1975-06-06 1977-04-26 Ibm Corporation Simultaneous addressing of different locations in a storage unit
US4099230A (en) * 1975-08-04 1978-07-04 California Institute Of Technology High level control processor
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
US4128882A (en) * 1976-08-19 1978-12-05 Massachusetts Institute Of Technology Packet memory system with hierarchical structure
US4084225A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4084227A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4070703A (en) * 1976-09-27 1978-01-24 Honeywell Information Systems Inc. Control store organization in a microprogrammed data processing system
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
GB2008821B (en) * 1977-11-04 1982-01-13 Sperry Rand Corp Digital computers
DE2842288A1 (de) * 1978-09-28 1980-04-17 Siemens Ag Datentransferschalter mit assoziativer adressauswahl in einem virtuellen speicher
US4251860A (en) * 1978-10-23 1981-02-17 International Business Machines Corporation Virtual addressing apparatus employing separate data paths for segment and offset portions of a virtual address and utilizing only the offset portion to calculate virtual address
FR2445988A1 (fr) * 1979-01-02 1980-08-01 Honeywell Inf Systems Dispositif d'adressage perfectionne d'un systeme de traitement de donnees
US4280177A (en) * 1979-06-29 1981-07-21 International Business Machines Corporation Implicit address structure and method for accessing an associative memory device
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4393443A (en) * 1980-05-20 1983-07-12 Tektronix, Inc. Memory mapping system
JPS5734251A (en) * 1980-08-07 1982-02-24 Toshiba Corp Address conversion and generating system
EP0066083B1 (fr) * 1981-06-01 1986-07-16 International Business Machines Corporation Dispositif de substitution d'adresse
DE3138973A1 (de) * 1981-09-30 1983-04-21 Siemens AG, 1000 Berlin und 8000 München Vlsi-gerechter onchip mikroprozessorcachespeicher und verfahren zu seinem betrieb
US4654777A (en) * 1982-05-25 1987-03-31 Tokyo Shibaura Denki Kabushiki Kaisha Segmented one and two level paging address translation system
JPS59157887A (ja) * 1983-02-28 1984-09-07 Hitachi Ltd 情報処理装置
US4587610A (en) * 1984-02-10 1986-05-06 Prime Computer, Inc. Address translation systems for high speed computer memories
JPH0652511B2 (ja) * 1984-12-14 1994-07-06 株式会社日立製作所 情報処理装置のアドレス変換方式
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5317717A (en) * 1987-07-01 1994-05-31 Digital Equipment Corp. Apparatus and method for main memory unit protection using access and fault logic signals
JPH01154261A (ja) * 1987-12-11 1989-06-16 Toshiba Corp 情報処理装置
US5257395A (en) * 1988-05-13 1993-10-26 International Business Machines Corporation Methods and circuit for implementing and arbitrary graph on a polymorphic mesh
US5450558A (en) * 1992-05-27 1995-09-12 Hewlett-Packard Company System for translating virtual address to real address by duplicating mask information in real page number corresponds to block entry of virtual page number
US5535351A (en) * 1994-04-04 1996-07-09 Motorola, Inc. Address translator with by-pass circuit and method of operation
US5530822A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translator and method of operation
US5530824A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translation circuit
EP0690386A1 (fr) * 1994-04-04 1996-01-03 International Business Machines Corporation Traducteur d'adresse et procédé de fonctionnement
AU3536499A (en) 1998-05-01 1999-11-23 Matsushita Electric Industrial Co., Ltd. Data processing device and method
US9792221B2 (en) * 2013-11-22 2017-10-17 Swarm64 As System and method for improving performance of read/write operations from a persistent memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3533075A (en) * 1967-10-19 1970-10-06 Ibm Dynamic address translation unit with look-ahead
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
US3618040A (en) * 1968-09-18 1971-11-02 Hitachi Ltd Memory control apparatus in multiprocessor system
US3761881A (en) * 1971-06-30 1973-09-25 Ibm Translation storage scheme for virtual memory system

Also Published As

Publication number Publication date
US3764996A (en) 1973-10-09
JPS5236658B2 (fr) 1977-09-17
DE2260353A1 (de) 1973-06-28
DE2260353C2 (de) 1982-02-25
GB1353311A (en) 1974-05-15
JPS4874126A (fr) 1973-10-05

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Legal Events

Date Code Title Description
ST Notification of lapse