FI91923C - Procedure for controlling a display in a display system and display system and display - Google Patents

Description

91923

The invention relates to a method for controlling a display device in a display system in both a display system and a display device. In the method, information about the display device is transferred from the display device to the display control member, and image control information is transferred from the display control member to the display device 10 to control the image displayed by the display device. The display system according to the invention comprises a display device and display means for controlling the display device, which are connected to the display device via at least one signal line for controlling the display of the display device 15, and possibly at least one more display device. The display device according to the invention is in accordance with the preamble of appended claim 17.

The display control means send vide-20 information as serial data to the display device in time, combined with the synchronization signals. The display device receives the serial video information and displays it on the screen at the location defined by the synchronization signals.

The most common display devices are CRT monitors with a single deflection mode of .25, which have already been pre-manufactured at the factory (eg on-screen image positioning). The latest display devices are able to synchronize to several deflection frequencies in a certain display device-specific frequency range (so-called multisync-monito-30 rit). The oldest display devices and display drivers in the PC environment (EGA, CGA, MDA, HGC) use only TTL-level signals for video information transmission, but newer devices (VGA, 8514 / A, XGA) have switched to analog video transmission. in order to be able to create more color / grayscale and to reduce the number of signal 91923 2 conductors. The synchronization signals are most often still transmitted in TTL level or combined with each other or combined with video signals (composite video). Three signals R (red), G (green) and B (blue) are generally used in analog transmission. In black-and-white environments, only the G signal is used. The levels of the analog video signals directly indicate the intensity of the corresponding displayed color point on the screen. By combining the levels of R, G, and B analog signals, an innumerable number of different colors can be produced for the 10 display devices.

To identify current monitors, the latest PC hardware uses separate identification signals (ID signals), most commonly 3 (IBM PS / 2 analog Monitors), which allows the identification of eight different monitors. At present, however, VGA-type video cards do not use ID signal recognition at all, but only identify the black-and-white and color display devices from each other based on the different voltage levels of these video signals. In the Mus-20 standard and color display devices, the levels of video signals differ due to the different matching (termination or termination) of the video signals in the display device.

In high-resolution and higher-quality display devices, 25 so-called BNC video connectors, in which case the identification signal connection must be made in the signal cable to achieve compatibility. The display device then most commonly uses the R, G and B signals (synchronization signal combined with the G signal) and possibly a separate combined horizontal / vertical deflection signal or separate horizontal and vertical deflection signals.

In order for the display device to be used in different display modes, a certain preselected video parameter table-35 must be used in the microcomputer (display controller) to describe the different display modes. In this case, the user must be able to select the correct option from the display device selections in the video driver installation program and indicate it. for a program that selects from the tables parameters corresponding to the display mode. The right choice is greatly hampered by uncertainty about the mutual compatibility of different display devices; graphics cards generally only support certain of the most commonly used display devices, and the user encounters problems if his or her display device does not include the video driver installer in the monitor-10 range. In order for a microcomputer to be able to support a large number of different display devices, a large number of different video parameter locks must be created along the display controller, which require a large amount of memory to store and thus incur additional costs.

15 The identification of a display device is also complicated by the use of only three ID signals in the signal cable, which makes it possible to identify only eight different display devices. Despite the ID signals defined by IBM, a large number of display device manufacturers use ID signal combinations that deviate from these 20 specifications, or the signals are not used at all (these signal lines are unconnected). This greatly complicates the reliability of programmatic display device identification. The use of defined ID-signal combinations also does not provide additional information on the other 25 so-called ID-signal combinations. additional features of the compatible display device (eg frequency range, resolution, etc.).

Another disadvantage of current display systems is that the execution of the factory output of the display device, which has to be performed when the display device enters production, is in practice carried out entirely by hand on the basis of a test image. The yields are made either by changing the default software values with microprocessor-based control or by changing the values of the components, e.g. yield benefits. Factors to be performed include e.g. the position of the image on the screen, the size of the image 35, etc. When there are several display modes, and when some of the settings are still interdependent, there is a suitable "compromise content" to be found, making adjustments takes a lot of time and thus also costs.

The cost is also due to the maintenance of the display device, which almost always requires a visit by the service personnel, and often also to the transfer of the display device to the service location, whereby the device may be in unproductive use for several days. For example, making new adjustments usually requires opening the display device, which must be done at a service location where the necessary equipment is located.

The object of the present invention is to overcome the above-mentioned drawbacks and to provide a user-friendly system in which the features of both the display controller 15 and the display device can be utilized as accurately as possible without the user having to know what is required. costs can be significantly reduced. This is achieved by a method according to the present invention, characterized in that a bidirectional communication path is formed between the display device and the means for controlling it, such that at least one signal line is used as the transmission path to be used. to identify the display device. The display system and display device according to the invention are in turn characterized by the features described in the characterizing parts of the appended claims 15, 16 and 17.

The basic idea according to the invention is to create a two-way communication path between the display device and the means for controlling it (microcomputer and its display controller) so that no dedicated signal lines are required for communication, but communication between existing signals or signal lines. those which are otherwise used (in addition to the data transmission mode) for controlling the image displayed by the display device or, for example, for identifying the display device. Thanks to the solution, the display device and the microcomputer can communicate with each other in such a way that each of them can recognize each other, and yet it is possible to adhere as well as possible to existing and known device environments.

When the display device and the microcomputer recognize each other, the above-mentioned operating problems are eliminated, because the display device 10 can inform the display driver and the program controlling it about its compatibility. In this way, the capabilities of both the display device and the display controller can always be used accurately without the user having to have knowledge of the device's features. The program (which can be supplied on a floppy disk with the display device) allows the microcomputer user to, for example, adjust the size and brightness or brightness of the displayed image and adjust the image, in which case no separate controls are required in the display device. In this way, a more advantageous mechanical structure of the display device as well as a more advantageous electronic solution are achieved.

Significant cost savings are achieved in the execution of factory defaults by reducing manual work, as the yields can be made by a system based on a test image and a camera by transmitting the transmission information via the data transmission-.25 road. This means that a separate connection between the display device and the microcomputer is also not required at the factory, which reduces costs.

Maintenance procedures are speeded up and simplified because the microcomputer can be equipped with a test program that asks the display device to provide, for example, its own ID (e.g., type number), production version, or fault message. When the user drives the the test program gets the service person-lostd an accurate picture of the situation already on the phone, which even-35 helps to correct the situation on the spot. When performing tests / settings 6 91923, it is not necessary to open the housing of the display device, because the test / setting information is sent along the communication path.

The solution according to the invention also offers the possibility to reduce the power consumption of the display device and its radiation values (especially cathode ray-based display devices), because the microcomputer can control the display device to different power saving modes.

A preferred and thus also general principle of implementation of the invention is to use solutions that have become as useful as possible in order to minimize additional costs and to maintain full compatibility with "de facto" standards, such as VGA standards. In the embodiment of the invention described below 15, for example, no new device components (switching changes) are required on the display controller (microcomputer) side,

The invention will now be described in more detail with reference to the examples according to the accompanying drawing, in which Fig. shows a first embodiment of the level control circuit shown in Fig. 30 for transferring data from a display device to a microcomputer; how the synchronization signals place the image on the screen in the normal display mode, Fig. 5a is a horizontal timing diagram no. In the display mode 5, Fig. 5b is a horizontal timing diagram in the communication mode according to the invention, Fig. 6 is a timing diagram showing the timing of the communication periods with respect to the other control signal logs, and Fig. 7 shows the different steps of the method according to the invention.

Figure 1 shows a computer system whose display system may be in accordance with the invention. The road-15 computer system comprises a central processing unit (CPU) 1, to which a keyboard 2 is connected, as well as a mouse controller 3 and a display system with display devices 4. The display system includes 7, which contains information about the displayed image. The video controller 5 generates a video signal VIDEO (which, as will be shown below, may consist of several different physical signals), which is input to control the display device 4.

Figure 2 shows in more detail the communication solution between a standard VGA-type display controller 5 and a display device 4 compatible therewith. The display controller 5 is connected to the display device 4 via an intermediate cable 9. The signal sequence of the display device connector of the VGA controller is in accordance with the standard:

SIGNAL NAME DESCRIPTION

1 R Red analog control signal. For use with color display only.

91923 8

SIGNAL NAME DESCRIPTION

2 G Green or black and white analog control signal. Black and white control is used only with the black and white display.

3 B Blue analog control signal. For use with color display only.

4 ID2 Display identification signal 5 Reserved Busy (ground) 5 6 R_Return Ground of the red analog signal (pin 1). For use with color display only.

7 G_Return Ground green or black and white signal.

8 B_Return Blue ground. For use with color display only.

9 Key Coding (connector pin hole blocked.

10 GND Grounding digital signals.

10 11 IDO Display device identification signal 12 ID1 Display device identification signal 13 HSYNC Display device horizontal deflection signal 14 VSYNC Display device vertical deflection signal 15 Reserved Reserved .15 Of these signals, the signal lines 20 and 15 of the horizontal and vertical offset signals HSYNC and VSYNC, and in addition signal lines 16-18 of the identification signals ID0 to ID2. The remaining signal lines are omitted because they are not related to this example solution.

At the end of the video controller 5, the solution 91923 9 shown in Fig. 2 corresponds to a standard VGA solution, in which the analog signals (R, G, B) used for image information transmission are controlled by the VGA controller circuit 10, the image information memory 7 (not shown in Fig. 2) and the RAMDAC 5 circuit, color palette, Color Look-Up Table, CLUT) 19. In the VGA controller, analog signals are also known to be used to identify black and white and color display devices from each other. This identification is based on the power supply feature of the RAMDAC circuit, the level detectors 20, 21 and 22 of the analog signals in the display controller, and the different matching (termination 31, 32) of the R, G and B signals in the black and white and color display device. Only the G signal is connected to the black and white display device, and all three of the above analog signals are connected to the color display device.

15 Due to the different line matching of the black and white and color display device, they can be distinguished from each other by supplying a certain amount of current to all analog signal lines by means of a RAMDAC circuit. This causes different voltage levels in the R and B signals compared to the G signal with black and white and 20 color displays. Here, the voltage levels of the analog signals are indicated by level indicators 20-22, whereby information is obtained as to whether a black and white or color display device is connected to the display controller.

Since the video card 5 shown in Fig. 2 corresponds to a VGA card conforming to the full-.25 standard, its operation will not be described further in this connection. More detailed information on the structure and operation of the card can be found, for example, in reference [1] (the list of references is at the end of the explanatory section).

The solution shown in Figure 2 at the end of the display device 4 (which in this example is a color-30 display) corresponds otherwise to a standard display device solution, but the following two additional components have been added to provide a bidirectional communication bus according to the invention. First, a signal level control circuit 35 23 is connected to the G line 12, which causes a change in the level of the G signal, which 91923 10 can be detected by a level detector 21 connected to the G line on the display controller side. a level detector 24 which detects changes in the signal level 5 in the G signal controlled by the RAMDAC circuit 19. The output of the level detector 24 is connected to the serial input 25a of the microcontroller 25 of the display device, and the signal level control circuit is in turn controlled through the serial output 25b of the microcontroller. The circuit 25 can in practice be any microcontroller or 10 processor, for example an 8051 type (e.g. Intel) controller.

Figures 3a and 3b show two alternative implementations for the signal level control circuit 23. In the alternative of Figure 3a, the control circuit consists of a termination parallel connection 15 comprising a termination impedance 27 and a switch 28 by which the termination impedance is connected in parallel with the G-line termination resistor 31. In this way, the termination of the G-line is temporarily changed, which in turn temporarily changes the voltage level of the G-signal. In the alternative of Fig. 3b 20, the signal level control circuit 23 in turn consists of a current generator 29 which, under the control of the microcontroller 25, supplies current control to the G line 12. The current control changes the G signal voltage level, and the change can be detected on the display controller level by the level detector 21. The current is easily implemented in the current generator. .With FET and a few resistors.

The following describes in more detail the data transmission event according to the invention in the apparatus according to Fig. 2, in which the termination level according to Fig. 3a 30 is used as the signal level control circuit 23. Thus, the starting point is a situation in which the color display device 4 is controlled by a standard VGA display controller 5 of a microcomputer. The following addresses and registers used in the description are thus I / O registers of a standard VGA display controller: 35 3C2 bit 4 = level indicator output 30 inverted, 91923 read only register 3C2 bits 7 and 6 = polarities of VSYNC and HSYNC signals, write register 3CC bits 7 and 6 = polarities of VSYNC and HSYNC signals, read register 3C6 = RAMDAC pixel data masking 3C7 = RAMDAC read address 3C8 = RAMDAC write address 3C9 - RAMDAC data 10 3BA or 3DA bit 0 = Display enable, read register.

These and other registers of the VGA video card are described in more detail in references [2] and [3]. The operating principle and programming of the standard RAM-DAC circuit (digital-to-analog conversion circuit, CLUT) is explained in reference [15]. In Figure 2, all signals have the same reference numerals as in reference [4].

Since the present invention relates only to the communication between the PC and the display device, it is assumed that the starting point is a situation in which the display controller 5 is initialized 20 and the display device 4 is identified as a backup display device. However, in the example of Figure 2, only the G signal is used for data transmission. Of the R, G, and B signals, the G signal is the only one that can be used for communication with both the black-and-white color display device because only the G-signal is used in the black-and-white display device.

The transition from the normal display mode to the communication mode, the actual communication, and the transition from the communication mode back to the display mode are performed step by step as follows.

30 1. Saving the Mode Mode Status

The communication program of the microcomputer stores the status of the video card 5 before changing the mode. The contents of the RAMDAC circuit 19 and the VGA controller, as well as the contents of the display memory, must be stored in order to be able to safely return to the display mode again after the communication mode.

12 91923 2. Clarification of RAMDAC bypass parameters Because this is a standard! VGA display controller, the contents of the RAMDAC circuit memory (RAM address 5 (registration address 5 3C9) for each "color" may vary between the values Oh and 3Fh (h means hexadecimal value) (cf. reference [4]). The value Oh controls the minimum intensity, and a value of 3Fh to its maximum. Due to the inaccuracies in the termination resistors (resistors 31 and 32 in Figure 2) 10 in the displays and controllers, it is safest to first find the G signal control parameter x that causes the output signal 30 of the display controller level detector 21 to change when the value of the y register of the RAMDAC is changed. The status of the level detector output can be read from the above-mentioned address 3C2, bit 4. The change point of the level detector output is determined as follows: a. The contents of RAMDAC (Oh) are stored (RAMDAC address Oh is easiest to use because the address data mask ) is always assigned 20 addresses OhD of RAMDAC), b. the auxiliary variable x is given a value x = 0h, c. write to address 3C6 the value Oh to mask the pixel data, d. write to address 3C8 as the address value Oh, 25 e. write to the address 3C9 of the R-register of the RAMDAC the value Oh, g. writing the value x to address 3C9 of the RAMDAC G-register, h. writing the value Oh, i. to the RAMDAC B-register address 30 3C9; x = x + l j. waiting until the image is inactive (3 DA, bit 0), k. waiting until the image is active (3 DA, bit 35 0), 91923 13 l. reading the output of the level detector y = 3C2 during the active image, m. for y, the value y = 10h and y, that is, the other bits are masked, except for bit 4, 5 n. giving x the value x = x + z, i.e. adding a margin to increase the reliability of the data transmission. The value of the auxiliary variable z depends on the implementation of the termination parallel connection 23, 10 p. The contents of RAMDAC (0h) are returned.

The above procedure thus finds out the value of x that can be used in the solution according to Fig. 2, in which the level of the G signal is controlled from the display controller side by changing the contents of the RAHDAC circuit. Knowing the value of 15x makes it possible for the RAMDAC circuit to supply a bias current which causes the voltage level of the G signal to rise higher than the reference voltage levels of the level detectors 21 and 24. By reducing the terminating impedance of the G signal of the display device, the voltage level 20 generated by the current can be reduced, which in turn can be detected by the level controller of the display controller, i.e. the output of the level indicator 21 of the display controller changes

Step 2 is not necessary, but it is preferable to perform it due to the inaccuracies mentioned above.

3. Switch to communication mode

The transition to the communication mode 30 according to the invention takes place from the normal display mode, in which the synchronization signals place the image on the screen of the display device according to Fig. 4. Horizontal deflection period HPER means the period during which one horizontal line is swiped from left to right and returned to the beginning of the next horizontal line.

35 The HPER consists of an active display period Hactiv., Which 91523 14 defines a horizontal active image area on the screen and during which the image data read from the image memory is displayed, and a shutdown period HBLANK comprising at least a front stage HFP, a deflection pulse HSYNC and a rear pulse HSYNC. During the shutdown-5 period HBLANK, e.g. return of the cathode ray tube electron beam to the beginning of the next line. Correspondingly, a vertical deflection period VPER consists of a display period Vactlva and a shutdown period VBLANK, which includes at least a front stage VFP, a vertical deflection pulse VSYNC and a rear stage 10 VBP. The display periods Haotive and Vactlve together determine the active image area, denoted by B. in the figure. HBLANK and VBLANK together form the time intervals during which the BLANK signal is active. The vertical deflection control periods consist of the horizontal deflection period multipliers, the number of which is determined by programmable control parameters.

When switching from the display mode to the communication mode, the frequencies, polarities and pulse lengths of the HSYNC and VSYNC signals are changed so that the display device 20 understands that the microcomputer wants to communicate. In addition, a value OOh is written to the I / O address 3C6 of the video controller, which causes that regardless of the control of signals P0-P7 (Pixel address) to the RAMDAC circuit, the output of the RAMDAC circuit depends only on the contents of the RAMDAC circuit at address 25 Oh, when the BLANK signal control for RAMDAC is not active. In addition, RAMDAC (Oh) is set to G register x and R and B registers Oh to generate the bias current required for communication. To avoid having to worry about controlling the BLANK signal to the RAMDAC-30 during data transfer, the location of the BLANK signal is programmed so that it is not active during data transfer (if the BLANK signal controlling RAMDAC is active, the R-, G- and B signal levels at a minimum). Figures 5a and 5b show the changes caused by the transition in the horizontal timing diagram. The situation in Figure 5a is

II

91923 15 modes (cf. Fig. 4), wherein the image is shown in an area A1 where the BLANK signal is not active. In Fig. 5b, the communication mode is switched, whereby the length of the active part A2 of the BLANK signal (the BLANK signal is active when it is in the "down" or logical O state) is minimized, and it is shifted away from the HSYNC pulses.

For VGA graphics cards, the locations of the BLANK, VSYNC and HSYNC signals can be programmed relatively freely, but for those graphics cards where the BLANK signal cannot be programmed, care must be taken to ensure that the output (s) of the level detector (s) are read only. during the active image.

4. Data transmission 4.1. The display device detects the communication mode by examining the VSYNC and HSYNC signals. By means of the level detector 24, the display device also detects that the display controller 5 controls the G signal. The monitor interrupts the flow of R, G, and B signals to minimize interference to the video amplifier screen.

20 4.2. The display device waits for the next VSYNC cycle and acknowledges that it has detected a communication mode. This is done by the microcontroller 25 activating the switch 28, whereby the termination impedance 27 is connected in parallel with the termination resistor 31. This causes a change in the voltage level of the G signal .25 (the level falls below the reference level of the level indicator 21).

4.3. The microcomputer waits for the VSYNC signal (because the display device acknowledgment is synchronized to the VSYNC signal) and reads the status of the output of the display controller level indicator 21.

30 If the microcomputer detects that the output status has changed, it knows that the display device is capable of communicating. Due to the fact that the display device does not activate the parallel connection indiscriminately (the display device needs a few VSYNC cycles to identify the communication mode), the microcomputer 35 has to check several times whether the display device 16 9 '1923 is capable of communication. If the display device is capable of data transfer, proceed from section 4.4, otherwise proceed from section 4.9.

4.4. The display device waits for a VSYNC signal (in this 5 steps, 2 VSYNC pulses have elapsed since the activation of the G signal parallel connection, so the microcomputer has one complete field period to detect the display device acknowledgment) and opens the switch 28 in parallel with the display.

10 4.5. The microcomputer is waiting to clear the acknowledgment.

4.6. The microcomputer writes either a value of x or a value of Oh to the G-register of the RAM-DAC (0h) of the display controller, synchronized with HSYNC pulses, however, so that the first control is Oh, which is also the start bit for the display device. The display device reads the controls of the display controller in sync with the HSYNC pulses using its own level detector 24 (the reading takes place in the horizontal timing diagram in the areas marked A3 in Fig. 5b). How the controls are interpreted and how long the controls are allowed in one field period depends on how the communication protocol is defined and what communication mode is set. As previously mentioned, data transmission cannot be performed while the BLANK signal is active.

Figure 6 shows how the data transmission takes place in areas A4 interrupted during the shutdown periods HBLANK and VBLANK.

Acknowledgment and response are as follows.

4.7 The microcomputer writes the x display driver to the RAMDAC (Oh) G-register.

30 4.8 The display device waits for the VSYNC signal and time to control the termination in parallel with the HSYNC signal, causing voltage fluctuations in the G signal accordingly. This is detected by the level controller 21 of the display controller. First, the start-35 bit (0) is transferred again, followed by the other bits.

91923 17

The microcomputer reads the output of the display controller level indicator 21 synchronized with the HSYNC signal and interprets the received message. Data transfer direction changes can be defined using the protocol used in the transfer.

5 4.9a. When all the controls / commands have been transmitted, the communication is terminated by the display controller restoring the display mode by returning the VGA and RAMDAC registers to the state stored in the display memory in step 1, i.e. to the state they were in just before the transition to the communication mode.

4.9b. Based on the changed frequencies, polarities, and pulse lengths of the HSYNC and VSYNC signals, the display device detects that the mode has changed, returning to the normal display mode of Fig. 4.

Fig. 7 shows the steps described above as a timing diagram, in which the data transmission in step 4.6 is additionally applied. Because the data is transmitted synchronized with HSYNC pulses, one byte consisting of a start bit, eight data bits D0-D7, a parity bit P, and two stop bits can be transmitted during the 12 horizontal lines. In this way, the data rate of the transmission path according to the invention is made to correspond to the data rate of the high-speed modem.

The above example describes the method according to the invention, the so-called in half duplex mode, where the .25 donation takes place alternately in opposite transmission directions. The method can also be easily changed so-called. to full duplex mode, where data transmission takes place simultaneously in both transmission directions. The following describes the changes required to transition from half-duplex mode to full-duplex mode.

The main difference between the full duplex mode and the half duplex mode is that two signal lines are used simultaneously for data transmission. In this case, the common reference level of the level 20s 22-22 differs from the reference level of the level 35 landscape 24. The common reference level of the level detectors 20-22 18 is still VGA compliant, but the reference level of the level detector 24 differs substantially therefrom by being either lower or higher than the reference level of the level detectors 20-22. In the following, it is assumed that G and R lines are used for data transmission, and that the reference level of the level detector 24 is lower than the reference level of the level detectors 20-22. When the G-line signal is controlled, the level detector 24 thus sends a voltage change signal to the serial input 25a of the microcontroller 25 as early as 10 when the level detector 21 does not yet detect the voltage level. The RAMDAC circuit of the video controller maintains the R-bias level of the video signal throughout the communication phase, and the microcontroller 25 controls the R-signal on the signal-level control circuit 23. Since the G-signal control levels are clearly lower than the R-signal control levels, G signal variations are not caused. in the output signal 30 of the level detectors 20-22. Only the variations of the R signal controlled by the microcontroller control circuit 23 cause changes in the output signal 30.

20 In other respects, the full duplex mode substantially corresponds to the half duplex mode described above. Only the RAMDAC circuit control parameters should be selected (due to the differences described above) on different grounds. When operating in full duplex mode, the communication protocol does not require .25 to take care of the communication direction, as in half duplex mode, but its application is best suited for operation only with the color monitor, since the black screen monitor has only one video signal line. For this reason, the half duplex mode is more common 30 than the full duplex mode.

Although in full duplex mode it is most advantageous to use signal lines used as video lines for the transmission of video information, the two signal lines used can in principle also be selected more generally from the following groups, either from the same group or from different groups: 91923 19 - , 12 and 13, - signal lines 14 and 15 of the deflection signals HSYNC and VSYNC, 5 - other signal lines used to control the image displayed by the display device (such as dotclk, display_enab-le, etc.), and - signal lines 16-18 of the identification signals IDO, ID1 and ID2 .

The solution according to the invention can be used with any display device controlled by a video signal. Such a display can be, for example, a cathode ray tube display, a liquid crystal display, an electroluminescent display, a plasma display, etc. Restrictions are also not imposed by, for example, connections with different signal-15 sequences, different connectors or different signals used in the connections.

A simple embodiment of the method according to the invention based on the excitation / response procedure is suitable for a display device without "intelligence" (no microcontroller or processor). In this embodiment, the display control means send a predetermined deviation signal control (excitation) to the display device, which identifies the predetermined deviation signal control (excitation). control and returns a notification (response) identification. The deflection signal control is set to .25 in pre-set frequencies, pulse lengths, polarities, etc., and different control can be defined for different display devices.

If, as in the previous example, it is desired to use one or more video signal lines 30 as a data transmission path, the control the line or lines from the display driver side in other ways than by changing the contents of the RAMDAC circuit memory. Alternatively, the control can be performed, for example, by changing the contents of the image information memory 7, by controlling the video signal directly to the video controller silicon (10) using or utilizing the overlay function in some RAM-91923 20 DAC circuits.

Outside the communication mode, the signals used to control the image displayed by the display device can also be used for communication, e.g., a deflection signal-5 le and HSYNC and VSYNC, which are controlled directly by the display controller input multiplexed to the display controller circuit signals. The display device also directly controls the deflection signals, which are read on the display controller side in a program-like manner. Because standard video controller solutions directly control 10 pedaling signals by Volda, this solution requires a change to the monitor, and is therefore not such a low-cost solution as the exemplary solution described above, which requires a standard display controller.

15 In analog communication, the analog and signaling signals used for the transmission of the actual image data are also possible to use the mold outside the communication mode with the signals used to control the image displayed by the display device, such as. The use of a video clock signal could be considered in particular in portable microcomputers which do not have a CRT display. However, these solutions also require changes to existing video drivers.

.25 If identification signals are used instead for communication, they, as well as deflection signals, shall be controlled directly by the video controller circuit or multiplexed to the signals of the video controller circuit. The display device also directly controls the identification signals, which are read programmatically on the display-30 toner controller side. Since not all signal control solutions have connection signals connected, this solution is not as advantageous as the example solution described above.

All the signals described above can also be combined in the most suitable way for the respective application 91923 21.

Any suitable communication protocol can also be used between the microcomputer and the display device. However, such a procedure requires a more complex structure from the display device 5, because the protocol requires an intelligent drive from the display device. The solution can be implemented with a microprocessor, microcontroller or logic connection.

In time, the communication can also be carried out in connection with the normal use of the microcomputer 10, so that the user does not perceive it in any way. Communication should then be performed outside the screen area. In-use identification signals can be communicated during the active image area without the user perceiving it in any way.

Thus, although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified in many ways within the scope of the inventive idea set forth above and in the appended claims.

Reference list s [1]. Programmer's Guide to PC & PS / 2 Video Systems, 25 Richard Wilton, Microsoft Press, 1987.

[2]. IBM Personal System / 2 "Display Adapter, Technical Reference, 68X2251, S68X-2251-0, April 1987.

[3], IBM Personal System / 2 "Model 80, Technical Reference.

30 [4]. IMS GI71 High performance CMOS color look-up table, The Graphics Databook, Inmos, June 1990.

Claims (20)

1. Procedure for controlling a display (4) in a display system with the aid of display control means (5, 1), 5. which system - information about the display Overfors from the display (4) to the display control means (5, 1), and from the display control means (5, 1) to the display (4) to control the image shown by the display, characterized in that a bi-directional data path is formed between the display (4) and the means (5, 1) which control it. at least one such signal line (12; G) used alongside the data transfer state for controlling the image shown by the display (4). The method of claim 1, wherein the at least one signal line (11, 12, 13) used in the transmission of video information is used as a data wave. 3. A method according to claim 2, c h a r a c t e r i z e d in that said video signal line is controlled from the display control means (5, 1) by seconding the contents of the memory of a digital-analog conversion circuit (RAMDAC) (19). 4. A method according to claim 2, c h a r a c t e r i z e d in that said video signal line is controlled from the display control means (5, 1) directly by using a display control circuit (10). 5. A method according to claim 2, characterized in that said video signal line is controlled from the display control means (5, 1) by the second contained in an image information memory (7). 6. A method according to claim 2, characterized in that sanding and / or receiving of data is synchronized with the aid of at least one deflection signal (HSYNC, VSYNC). 91923 7. A method according to claim 1 or 2, characterized in that at least two signal lines are used as a data path, and that data can be transmitted simultaneously in both directions. 8. A method as claimed in claim 1, characterized in that from normal display state, it is switched to the data transfer state by giving the display (4) an impulse by at least one deflection signal (HSYNC, VSYNC) parameters such as frequency, polarity and pulse input. , others to the predetermined value. 9. A method according to claim 8, characterized in that the entire data transfer is forwarded as a simple identification procedure by means of said impulse and the response given by the display (4). 10. A method according to claim 1, characterized in that during the data transfer state, at least the property and condition information of the display (4) is transmitted from the display (4) to the display control means (5, 1). 11. A method according to claim 1, characterized in that during the data transfer state, at least test / control information is transmitted from the display control means (5, 1) to the display (4). 12. A method for controlling a display (4) in a display system with the aid of display control means (5, 1), in which method - information about the display is transmitted from the display 30 (4) to the display control means (5, 1), and - image control information OverfOrs from the display control means (5, 1) to the display (4) for controlling the image shown by the display, characterized in that for controlling the display (4) there is formed between the display and the means (5, 1) which control it a bidirectional data path, so for example, at least one such 91 ^ 23 signal line (16 - 18) is used as a data scag which, in addition to the data transfer state, is used for identification of the display (4). Method according to claim 12, characterized in that at least two signal lines are used as a data path, and that the data transmission takes place simultaneously in both directions. 14. A method according to claim 12, characterized in that said signal line (16 - 18) is controlled from the display control means (5, 1) directly by the use of a display control circuit (10). A display system comprising a display (4) and display control means (5, 1) which control the display and which are connected to the display (4) via at least one signal line (12) intended for controlling the image shown in the display, characterized in that a bi-directional data path is formed between the display (4) and the display control means (5, 1), which consists of at least one signal line (12) for controlling the image shown by the display (4). A display system comprising a display (4) and display control means (5, 1) which control the display and which are connected to the display (4) via at least one signal line (12) intended for controlling the image shown in the display, and via at least one signal line 25 (16-18) used for identification of the display, characterized in that a bi-directional data path consisting of at least one of said signal lines (16 - 18) is formed between the display (4) and the display control means (5, 1). ) used to identify the display (4). A display (4) comprising a display frame for displaying the user visual information, and at least one signal line (12) received from the display control means (5, 1) used for transmitting image information, characterized in that the display comprises 1 91923 means. (23) for breathing the signal level of this signal line (12). The display according to claim 17, characterized in that the means (23) for breathing the signal level comprise means (27, 28) for temporarily breathing the termination of this signal line (12). The display according to claim 17, characterized in that the means (23) for breathing the signal level comprise means (29) for supplying current control to this signal line (12). The display according to claim 17, characterized in that it further comprises a level detector (24) coupled to the incoming signal line (12).