FI91696C - Method for making a rate adjustment decision at a node in a digital data communication system - Google Patents

Description

91696

Method for obtaining equalization at a node in a digital communication system

The invention relates to a method according to the preamble of appended claim 1 for providing an equalization solution at a node of a digital communication system.

At the nodes of a digital transmission network, part of the transmission capacity is branched to that station as the remaining 10 continue to the next transmission path. Implemented with the current technique, the channels of the transmission frame are decoupled at the node level to the level of branching capacity, and the branching and patching are typically implemented by cabling the desired channels in parallel from one transmission device to another. Thus, for each channel, each transmission device has its own interface at the node, which is typically in accordance with the G.703 standard. Implemented this way, there is a lot of connection and cabling in the nodes, which makes such a solution expensive. This problem has been overcome in the repeater station disclosed in FI patent application 904833, in which unbranched channels are not disassembled in parallel, but are passed in series from one transmission device to another along the repeater. The latter repeater station is therefore a preferred application of the present invention, although the invention can be used in the repeater station described above in myOs, where both branching and patching are performed in parallel, as well as at any other node where equalization is buffered by buffering.

The repeater's repeater's transmission device locks into the frame coming from the transmission path and decrypts the channels into flexible buffer memories as many as there are channels in the transmission frame. Vista flexible buffer memories data read-in lahetyspuolen frame counter at pace, and multi-multiplexed into a new 35 transmission frames.

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Since the frame coming from the transmission path has mybs other bits (so-called frame bits) in addition to the actual data, e.g. bits of the frame lock signal and the service telephone signal, the flexible buffer memories are not written or read at a different rate, but in the data write or read time. long "gaps" caused by female frame bits.

The difference in the speed of the channels of the bit stream entering and leaving the buffer memory is matched to the so-called tasauk-10 with. The equalization method can be either positive or negative. (Positive smoothing in Example S is used in this description, unless otherwise stated.) If the read speed from the buffer memory is higher than the speed of the incoming channel, additional 15 information bits without information are added to the outgoing signal, so-called. equalization bits, to remove the tamdn difference (positive equalization). If the read speed from the buffer memory is lower than the speed of the incoming channel (write speed to the buffer memory), a data bit (negative-20 equalization) is normally used in place of the empty equalization bit. The equalization is usually performed once in a frame, and the use of the equalization is indicated by the equalization indication bit. In the future, positive equalization will be used as an example.

In commonly used devices today, the need for equalization is determined based on the degree of filling of the buffer memory by • comparing the filling base with a fixed equalization limit. However, with both bit streams as apertures as described above, the fixed equalization path limit to the buffer fill level causes large sudden oscillations that appear as a timing variation when the bit stream is decomposed into channels. The problem can be alleviated by performing a read or write to the buffer memory with a gapless signal, but the taild has to eliminate gaps caused by bitstream frame bits by reading a 3,91696 clock in the buffer memory 35 with a phase locked oscillator controlled by a phase detector.

It is therefore an object of the present invention to provide a method in which the problems caused by the timing vSrinå can be mitigated, no matter the phase-locked loops described above. This is achieved by a method according to the invention, which is characterized by what is described in the characterizing part of the appended claim 1.

The basic idea according to the invention is to equalize on the basis of the buffer filling level as before, but to change the values which are compared with each other in the equalization comparison (equalization limit or filling level value) so that the average or 15 hew of the buffer memory is obtained. In this way, the equalization pairs are created as evenly as possible, so that the Varina due to the equalization is at such a high frequency that it is filtered out when the channel is discharged thanks to the loop filter of the flexible buffer.

The invention will now be described in more detail with reference to the examples according to the accompanying drawings, in which Fig. 1 shows a digital transmission network repeater station using the method according to the invention, Fig. 2 shows a solution according to a first embodiment of the invention in the repeater station according to Fig. 1, Fig. 3 shows Fig. 4 shows the phase usage of the flexible buffer memory when a known fixed equalization limit is used while the transmission and reception frames are in phase, Fig. 4 shows and the reception direction frames are at different stages from each other, Fig. 6 shows the determination of equalization limits and the phase behavior of the flexible buffer memory with the dynamic equalization limit according to the invention ηΰη transmission and reception direction frame n is in phase, Fig. 7 shows the phase operation of the flexible buffer memory at the dynamic equalization limit according to the invention with the transmission and reception direction frames at different stages, and Fig. 8 shows a solution according to the second embodiment of the invention in the repeater according to Fig. 1.

Figure 1 shows a repeater station serving as a node of a digital communication system using the method according to the invention. The repeater station has two transmission paths, in this case radio paths A and B, silent transmission devices 11 and 12, which in this case are radio links, the antennas of which are marked with reference signals 11a and 12a. Transmission paths A and B provide the repeater station with e.g. TDMA (Time Division Multiple Access) time multiplexed channels, from which the branch channels C are decompressed from the data transmission frames S & n by demultiplexing them to the hierarchical level of the 25 branch channels. The branched channels C are then wired, e.g. via a conventional G.703 interface, to the transmission device (not shown) of the branch of the communication network to which said channels are intended.

Unbranched channels, i.e. directly from the transmission path A, the channels moving to the transmission path B (or vice versa) are fed from the transmission device 11 (or from the transmission device 12, respectively) in series to the transmission device 12 (or to the transmission device 11, respectively) along the repeater line 13.

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A repeater station serving as a node in a digital transmission network of 5,91696 TS is described in the aforementioned FI patent application 904833, which is referred to for a more detailed description.

Fig. 2 shows an implementation of a first embodiment of the method according to the invention at the repeater station according to Fig. 1, in which the transmission frame is passed along the repeater slot 13 as such in series from the transmission device 11 to the transmission device 12. Only the transmission direction is checked from left to right; the second direction of transmission is similar in function. The channel-common frame controller unit 18 at the input of the transfer device 12 locks into the incoming frame, equalizes, and decompresses the frame channels into the flexible buffer memories 20 of the channel-specific buffer units 15. The buffer units thus have as many channels as there are transmission links. Channels coming from transmission path A are not required to be synchronous, but may be plesiochronous. Each buffer unit, except the flexible buffer memory 20, has an associated write counter 19 which controls write to the buffer memory and a read counter 22 which controls a read from the buffer memory. Whenever a bit of a particular channel is in turn in frame S, the bit is written to the flexible buffer memory 20 of that channel's buffer unit 20 at the position indicated by the write counter 19 and the write counter is allowed to step one step forward. Reply accordingly lahetyspuolen frame counter 26 is read pace da-TAA elastic buffer memory 20 read counter 22 from ADDRESS-tamasta. Whenever bit-30 ti is read from the buffer memory, the multiplexer 21 selects the read and write counters of that channel for the adder 23, which calculates the difference E of the write counter and the read counter, i.e. the phase margin at the respective moments. This phase margin E is compared by a comparator 24 to a predetermined equalization limit L, 35 obtained from the equalization limit memory 25. The result of the comparison 6 91696 is fed to a frame and set counter 26 which controls the frame multiplexer 27 based on the comparison. If, for example, the phase margin E is smaller than the equalization decision limit, an equalization decision is made, i.e. at the next equalization bit of the channel in question, 5 bits from the buffer memory 20 are not read to the frame multiplexer 27, increasing the phase margin by one bit (positive equalization). Equalization pairs are not necessarily made every time the buffer memory is read. The write and read counters rotate around when the flexible buffer-10 memory runs out. The frames of the frame counters 19 and 26 need not be the same, but the capacity may change at the repeater station. The frame output to the transmission path B is assembled in a frame multiplexer 27, the inputs of which read data from channel-specific buffer memories 20.

Returning to Figure 2 further, the verse of the description of Figure 6 is shown.

Figure 3 shows the structure of a transmission frame. The example is a frame used in a transmission device (radio link) with a capacity of 2 * 2 Mbit / s.

20 The example corresponds in principle to the otherwise usable situation, but for the sake of simplicity and clarity, the length of the frame has been shortened. The whole frame is divided into N pieces in the so-called sets shown in the figure below.

In this case, N = 8, and the sets are numbered from zero to 25 to seven. The sequence number of the set is shown in the left column of Figure 3. The channel data is denoted by numbers (1 or 2) and the frame bits by the reference character K. The channel data is consecutive so that the data denoted by one belongs to the first 2 Mbit / s system (the first 30 channels) and the data denoted by the second to the second 2 Mbit / s. system (second channel). Each set has an equal number of data bits, but the number of frame bits K at the beginning of the set varies from zero to eight.

Figure 4 shows the phase margin of the flexible buffer memory 35, i.e. the filling level for one frame in a known

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7 91696 in the case where both the write to the buffer memory that the reading from there takes place with an aperture clock and the equalization limit is fixed at 5 bits. Figures 4 to 7 are drawn using the frame of Figure 3 as an example, and are patched on either of the two channels in the frame. The time is shown on the horizontal axis so that one scale step corresponds to one set. The sequence numbers of the sets of the frame according to Figure 3 are marked on the horizontal axis. On the vertical axis, the phase margin E is represented such that one scale step corresponds to 10 equal bits. In this case, the upper Kayra WR corresponds to the writing to the buffer memory, and the lower Kayra RD corresponds to the reading from there. The area of the curves marked by the arrows F is the phase margin of the buffer at each instant.

Figure 4 starts at the point where the frames of the transmission and reception directions are in the same phase and the phase margin E of the buffer is 5 bits. Since the frames are in the same phase, the gaps in the chapter and the writing always hit the same places and the phase margin remains at 20 reference bits at all times. Figures 3 and 4 show how the phase always changes for the frame bits. For example, in the set zero comes three frame bits per channel, and in the set three four frame bits (Fig. 3), whereby a correspondingly large change in phase takes place (Fig. 4).

25 the transmitting and receiving side frame counters function as different clocks, instead of the bells need to be to one another with respect to synchronous. Due to this, the frames of the transmission and reception direction slide relative to each other. Figure 5 shows a situation where there is still a fixed 30 equalization limit 5 bits, but the frames have slipped slightly relative to each other. Since the justification decision limit is 5 bits, keeping tasausjarjestelma concerns that the phase margin Get access to less than five bits. It can be seen from Figure 5 that the average phase margin of the buffer has increased considerably, and myOs equalizations occur several times in a row.

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As the frames slide relative to each other, the average phase margin of the buffer varies considerably, and no equalization is created evenly, but the equalization is repeated several times in succession and the equalization is seldom equal.

Figure 6 shows a corresponding situation implemented with a dynamic equalization end boundary according to the invention. According to a first embodiment of the invention, the equalization limit is changed according to the phase of the frame to be transmitted on the transmission path by monitoring which set of frames is in each transmission. Figure 6 shows by way of example a situation where the set zero equalization limit 5 bits, the set one equalization limit 4 bits, the set two equalization limit three bits, the set three equalization limit six bits, the set 15 equalization limit five bits and the set five bits , a set of six equalizers with a limit of four bits, and a set of seven equalizers with a limit of three bits. The equalization decision limits shown in the example are obtained by adding a solid 2-bit Lisa margin to the phase margin measured from the line 60 drawn through the end points of the 20 phase curves RD representing the number from the buffer memory, and the result is rounded up. Thus, for example, 2 bits have been added to the phase margin x = 2.5 bits measured at zero in the set, and the result 4.5 bits has been rounded to 5 25 bits. Correspondingly, for example, three phase (3.5 + 2) bits are obtained for the set, i.e. 6 bits rounded.

In the device structure shown in Fig. 2, the set reading of the frame and set counter 26 serves as an address for the equalization paus memory 25, the address 0 of which thus has an equalization limit L = 5 in the present case 30, address 1 a equalization limit L = 4, address 2 an equalization limit L = 3, • ♦ etc, and at address 7 equalization paatsO limit L = 3.

Equalization limits L can be defined for any transmission frame, respectively. Since the positions of the frame bits in the frame 35 are known, the phase utilization of the read counter li 9 91696 corresponding to it is obtained, i.e. the curve RD, from which the equalization limits can be determined accordingly.

Fig. 7 shows a situation otherwise similar to Fig. 6, but now the transmission and reception frames slide relative to each other. The dynamic justification decision tassåkin border shall concern the case that the average phase margin remains constant so tasauspaatOksia generated evenly.

Although the invention has been described above with reference to the examples of the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified in many ways within the scope of the inventive idea set forth above and in the appended claims. Although, for example, the foregoing invention is applied in conjunction with a chapter from buffer memory 15, it is equally applicable to write to myOs memory or both.

Claims (2)

91696 A method for initiating equalization at a node of a digital communication system, wherein the data is stored in at least one buffer memory (20), the execution rate of which is monitored and the execution of the equalization rate is determined by the equalization of the equalization rate (E). (L), characterized in that the equalization end limit 10 (L) is changed according to the lie of the frame of the transmitted signal. A method according to claim 1, characterized in that the equalization end boundary (L) is changed according to the phase of the frame leaving the node. 15 91 696