FI76232C - Signal processing circuit for automatic bias control system in picture tubes - Google Patents

Description

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The present invention relates to a signal processing-5 arrangement used in a system for automatically adjusting the current level of a video image display device representing a black image, such as a television picture tube. The invention further relates to an arrangement for compensating for impedance variations 10 at a sensing point from which a signal representing a black current is obtained, so that such impedance variations do not affect the operation of the subsequent control circuits to which the sensing point is connected.

Televisions sometimes use 15 automatic picture tube bias (AKB) control systems to automatically provide the correct levels of black picture current for each picture tube electron gun. As a result of this operation, the image reproducing images of the picture tube is prevented from having a detrimental effect on the operating parameter of the picture tube (i.e., due to the effect of aging and temperature). One type of AKB system is disclosed in U.S. Patent 4,263,622 to Werner Hinn entitled "Automatic Kinescope Biasing System."

The AKB system typically operates during image sampling times, with the picture tube conducting a small black level representing the extinction current in response to a reference voltage representing the information in the black video signal. This current is monitored by the AKB system to generate a picture tube bias correction voltage that represents the difference between the detected black current level and the desired black current level.

The correction voltage is applied to the picture tube, such as through the video signal processing circuits preceding the picture tube, for the purpose of reducing the difference. Typically, the correction voltage is applied to the bias control output terminal of a DC-connected CRT 2 76232 amplifier, the control amplifier supplies video output signals at a level suitable for directly controlling the CRT cathode intensity control electrode. The correction voltage changes the bias output of the control amplifier, thus changing the cathode bias voltage, resulting in the desired level of cathode black current.

In an AKB system of the type described in the aforementioned Hinn patent, the control circuits respond periodically to a signal obtained having a magnitude representative of the black current level of the cathode. The resulting signal has a non-zero level as described above when the black current level is correct and has different levels (i.e., more or less positive) when the black current ta-15 so is too high or too low. The obtained signal is generated at a sensing point connected to the control circuits comprising level lock and color synchronization circuits for generating a picture tube bias correction signal according to the magnitude of the received signal. For example, the received signal 20 can be level-locked by a level-locking amplifier which charges or discharges the charge capacitor according to the level of the received signal. The bias correction signal increases or decreases as desired to maintain the correct black current level. It should be noted here that the control circuits to which the sensing point is connected can adversely affect when the sensing point from which the signal representing the black current is obtained displays impedance changes as a function of the level of the picture tube control bias. Accordingly, there is provided an apparatus for nullifying the effect of such impedance changes 30 on control circuits with makeup completely. The disclosed device also advantageously increases the insensitivity of the level locking circuit associated with the control circuits to interference signals, including locally generated interference, which could otherwise interfere with or confuse the bias voltage correction signal.

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When the bias correction signal is obtained from the charge capacitor, it takes the form of a bias correction voltage.

The bias correction signal received from the charge capacitor should remain unchanged when the level of the received signal in the form of a voltage pulse represents the correct level of black current. This requires that the output current from the level-lock amplifier does not charge or discharge the charge capacitor when the level of the voltage pulse represents a clever level of black current. In more detail, in Hinn's patent for an image-type AKB system, this requires that the level-lock amplifier does not supply current to the charge capacitor when the correct black tube current of the picture tube is indicated by a corresponding voltage pulse having a predetermined magnitude of non-zero. This result can be achieved by setting aside the bias voltage of the level-locking amplifier, such as by means of a pre-set, mechanically adjustable potentiometer connected to an appropriate bias voltage control point of the amplifier.

20 It should further be noted that such manual presets are detrimental to any other type of automatic signal control system. In addition, such manual setups are detrimentally time consuming and associated potentiometers undesirably increase the cost of the system.

It should also be noted that the signal processing technique used by some AKB systems can cause a setting error if the boundary voltages and signal gains of the private CRTs are not identical, for example due to CRT manufacturing tolerances. In such a case, there may be an error in the black current level provided by the AKB system, which can be compensated by pre-set manually adjustable potentiometers. The arrangement 35 shown preferably facilitates the design of AKB signal processing circuits that do not require manually adjustable controls to compensate for such layout errors.

The present invention relates to a system for processing a video signal, in which a signal obtained representing a black current level conducted by an image display device has a certain non-zero amplitude when the black current level is correct. The obtained representative signal is applied via the input signal switching path to a level locking amplifier, which supplies 10 output currents for charging and discharging the charging device according to the amplitude of the signal obtained. According to the principle of the present invention, the additional signal is applied in the magnitude and direction of the input signal switching path such that it nullifies the amplitude of the received signal at the input of the amplifier 15 when the amplitude of the obtained signal represents the correct black current level. Correspondingly, the conductivity of the level amplifier remains unchanged when the amplitude of the received pulse corresponds to the correct level of the black current and the voltage on the charging device remains unchanged.

According to a feature of the invention, the magnitude of the additional signal is proportional to the magnitude of the limit potential of the cathode of the picture tube developed during the AKB interval.

According to another feature of the invention, the input of the level-locking amplifier is locked to a reference voltage during a level-25 locking time interval preceding the color synchronization time interval of the signal. The obtained signal representing the black level is generated during the level lock interval so that the reference voltage to which the amplifier input is locked during the level lock interval is a function of the magnitude of the received signal, and an additional signal is generated during the next color synchronization interval. The auxiliary signal has a magnitude and direction to keep the input voltage of the amplifier approximately constant when the magnitude of the received signal corresponds to the correct black current level.

According to a further feature of the invention, the input of the amplifier 5 76232 is locked to the reference voltage during the level lock interval, and the obtained signal and the additional signal are generated during the level lock interval.

In addition, according to the present invention, the automatic 5-tube bias voltage regulating device comprises a capacitor for coupling the received signal corresponding to the black current level of the picture tube and an additional signal having the above-described magnitude and direction to the input of the level lock amplifier. The source of the resulting signal has an adjustable output impedance that is proportional to the magnitude of the picture tube bias voltage. The resulting representative signal is applied from the adjustable impedance output of the obtained signal source via a switching impedance to a capacitor. The switching impedance is large in relation to the adjustable output impedance, which considerably reduces the impedance variations caused by the output of the obtained signal source to the additional signal source.

According to another feature of the invention, a switching capacitor is included in the level locking circuit. In addition, the switching impedance 20 increases the insensitivity of the level locking circuit in response to interference signals.

In the drawing, Fig. 1 shows a part of a color television receiver comprising an AKB system and an associated signal color synchronization circuit, incorporating the principles of the present invention; Fig. 2 shows signal waveforms related to system operation in Fig. 1; Fig. 3 illustrates alternative signal waveforms shown in Fig. 2. version, Fig. 4 shows details of the level locking circuit of Fig. 1, and Fig. 5 shows details of a timing signal generator associated with the system of Fig. 1.

In Figure 1, the television signal processing circuit 10 provides the separate 6 76232 luminance (Y) and chrominance (C) components of a color television complete signal to a luminance-si-chrominance signal processing circuit 12. The processor 12 includes luminance and chrominance amplifier control circuits, DC level setting circuits (i.e. comprising keyed 5 black level level locking circuits), color demodulators ry, 9 ~ Y and by for generating color difference signals and matrix amplifiers for combining the latter signals with processed luminance signals to provide low level color image signals r, g 10 and b. is otherwise processed by circuits in the video output signal processing circuits 14a, 14b and 14c, respectively, which supply high level amplified color image signals R, G, B to the respective cathode control electrodes 16, 15b and 16c of the color image tube 15.

Circuits 14a, 14b, and 14c also perform functions related to AKB operations, as will be described. The image tube 15 is of the self-aligning, directly coupled cannon with a jointly fed lattice 18, 2Q associated with each electron cannon containing cathode electrodes 16a, 16b and 16c.

Since the output signal processors 14a, 14b and 14c are similar in this embodiment, the following description of the operation of the processor 14a also applies to the processors 14b 25 and 14c.

Processor 14a includes a picture tube control stage comprising an input common emitter transistor 20 which receives a video signal r from processor 12 via input resistor 21 and a high voltage common terminal transistor 22 which, together with transistor 20, forms a cascaded video control amplifier. A high level video signal R suitable for controlling the cathode 16a of the picture tube is generated across the load resistor 24 in the collector output circuit of the transistor 22. The supply voltage for the operation 35 of the amplifier 20, 22 is provided by a large DC voltage source.

7 76232 B + (i.e. +230 volts). Negative DC feedback to controller 20, 22 is provided by response 25. The signal gain of the cascade amplifier 20, 22 is initially determined by the ratio of the values of the feedback resistor 25 and the input resistor 21. The feedback circuit provides a suitable small amplifier output impedance and helps to stabilize the DC operating level at the amplifier output.

The sensing resistor 30 DC-connected with the collector-emitter paths of the transistors 20, 22 in series and between them 10 operates to generate a voltage at a relatively low-waste point A representing the black current level of the cathode of the picture tube conducted during the picture tube blanking intervals. Resistor 30 operates in conjunction with the receiver's AKB system, which will now be described.

The timing signal generator 40, comprising logic control circuits, responds to periodic horizontal synchronization signals (H) and periodic vertical synchronization signals (V), both obtained from the receiver deflection circuits, to generate a timing signal νβ, Vg, Vc, Vp and V1, activities of the AKB function during the intervals. Each AKB time slot begins immediately after the end of the vertical deflection interval during the vertical blanking interval and includes a plurality of horizontal line slots also during the vertical blanking interval and during which there is no image information of the video signal. These timing signals are shown in waveforms in Figure 2.

Referring now to Figure 2, the timing signal Vn,

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deon extinguishing signal, comprising a positive pulse generated shortly after the end of the vertical return interval at 30-30 hours indicated by reference to signal waveform V. The extinguishing signal νβ occurs during the AKB interval and is applied to the luminance chrominance processor 12 -ver-35 tail level, corresponding to the absence of a video signal. This can be accomplished by reducing the signal gain of the processor 12 to approximately zero by the gain control circuits of the processor 12 in response to the signal Vg and by changing the DC level of the video signal processing path using the DC level control circuits of the processor 12 to provide a black picture reference level at the signal output of the processor 12. . The timing signal VG, a positive gate control pulse, contains three horizontal line intervals during the vertical shutdown interval. The timing signal Vc controls the operation of the level lock-10 circuit associated with the color synchronization operation of the AKB system signal. The timing signal Vg, the color synchronization control signal, occurs after Vc and acts to timing the operation of the color synchronization and holding circuits of the circuits which generate the DC bias control signal to control the black current level of the cathode of the picture tube. The signal Vg includes a color synchronization time slot, the beginning of which is slightly delayed relative to the end of the level lock time slot containing the signal Vc and which ends approximately simultaneously with the end of the AKB time slot 20. The additional negative direction pulse Vp, the operation of which will be described in more detail later, is simultaneous with the color synchronization interval. The signal timing delay TQ shown in Figure 2 is of the order of 200 nanoseconds.

Referring again to Figure 1, during the AKB interval, a positive pulse VG (i.e., on the order of +10 volts) biases the image tube gate 18, thereby causing the electron gun comprising the cathode 16a and the gate 18 to increase its conductivity. At times other than the AKB time slots 30, the signal VG provides a normal less positive bias voltage to the gate 18. In response to the positive gate pulse VQ, a phased positive current pulse occurs at the cathode 16a during the gate pulse time slot. The amplitude of the cathode output current pulse thus developed is ver-35 in line with the level of cathode black current conductivity (typically a few microamperes).

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The induced positive cathode output pulse occurs on the collector of transistor 22 and is applied to the base input of transistor 20 through resistor 25, causing the current conductivity of transistor 20 to increase proportionally when a cathode pulse is present. The increased current conducted by the transistor 20 causes a voltage to develop across the sensing resistor 30. This voltage is in the form of a negative parallel voltage change occurring at the sensing point A, which is proportional to the magnitude of the output pulse of the cathode representing 10 black currents.

The magnitude of the voltage change at point A is determined as the product of the value of resistor 30 and the magnitude of the current flowing through resistor 30.

The voltage change at point A is applied through a small resistor 31 to a point B where a voltage change develops, substantially corresponding to the voltage change at point A. Point B is connected to a bias control voltage processing circuit 50. The circuit 50 includes an input switching capacitor 51, an input level lock and a color synchronization (i.e., the steepness operation amplifier-20) connected to a feedback switch 54 responsive to the level lock timing signal V 1 and a charge capacitor 56 coupled to a switch 55 responsive to the color synchronization timing signal V 1. The voltage generated by the capacitor 56 is used to supply the picture tube 25 through the bias correction signal circuit 58 and the resistor circuits 60, 62, 64 to the picture tube controller via the bias control input at the base of the transistor 20. Circuit 58 includes signal transmission and buffer circuits for biasing the voltage to supply a voltage at a suitable level in accordance with the bias control input requirements of the low impedance transistor 20.

The operation of the system of Figure 1 will now be discussed with particular reference to the waveforms of Figure 2. The additional signal Vp is applied to point B of the circuit in Fig. 1 via dio-35 din 35 and through a voltage-converting impedance circuit comprising resistors 32 and 34, i. with values of 220 kilo-ohms and 270 kilo-ohms respectively. The signal Vp has a positive DC level of about +8.0 volts at all times except during the AKB color synchronization interval, to keep the diode 5 35 conductive so that the normal DC bias voltage develops at point B. When the positive DC component of the signal Vp is present, the junction of resistors 32 and 34 is level-locked to a voltage equal to the voltage across the positive DC component mii-10 of the signal Vp diode 35. The signal Vp indicates a negative, less positive fixed-amplitude pulse component during the AKB color synchronization interval. Diode 35 is considered to be a non-conductive response to a negative pulse Vp which causes both resistors 32 32 and 34 to switch between point B and ground. Resistor 31 does not cause significant attenuation for the voltage change that develops at point A relative to the corresponding voltage change (vp that develops at point B because the value of resistor 31 (200 ohms) is small relative to the values of resistors 32 and 34.

Before the level lock interval, but during the AKB interval, the pre-existing DC nominal voltage at point B (vNQf ^ charges the positive terminal of capacitor 51. During the level lock interval, when the gate control pulse VQ is generated, the voltage at point A decreases in response to pulse VQ black current This causes the voltage at point B to drop to a level approximately equal to the level vNqm ~ V1 * during the lockout interval, timing signal V1, causing the level lock switch 54 to close (i.e., conduct), causing the amplifier 52 to invert (-) the signal input is applied to its output, thus forming a unit gain tracking amplifier from amplifier 52. At present, the charge capacitor 56 is disconnected from amplifier 52 by means of a non-conductive switch 55. As a result, a fixed DC reference signal 7 6 2 3 2 ^ - (i.e. +5 volts) applied to the non-inverting input (+) of the amplifier 52 KL · !?, the source switches remote feedback operation to the inverting signal input of the amplifier 52 through the output of the amplifier 52 and the conductive switch 5.

Thus, during the level lock interval, the voltage across the capacitor 51 is a function of the reference set voltage determined by the voltage V -, ^ - from the negative terminal of the capacitor 51, and the voltage at the positive terminal of the capacitor 51 corresponds to the preset DC nominal level (VN0M ) the difference between the voltage change developed at point B and at point B during the time-lock interval. Thus, the voltage across the capacitor 51 during the level lock reference interval is a function of the level of the voltage change Vj representing the black current, which may vary. Voltage V, can be expressed in the form (V „T ^ -

j NOM

Vl) “VREF * Immediately during the next color synchronization interval, there is no positive gate control pulse, causing the voltage at point B to increase positively to the pre-existing DC nominal level that occurs before the level lock interval. At the same time, a negative pulse Vp occurs in the blocking direction, biasing the diode 35 and interfering (i.e., momentarily changing) the normal voltage transfer and switching operation of the resistors 32, 34 25 so that the voltage at point B decreases by V2 / as shown in Fig. 2. the color synchronization switch 55 closes (conducts) in response to the signal Vg, whereby the charge capacitor 56 30 is connected to the output of the amplifier 52.

During the color synchronization interval, the input voltage applied to the input (-) of the inverting signal of the amplifier 52 is equal to the difference between the voltage 35 across the voltage capacitor 51 at the point B. The input voltage applied to the amplifier 52 is a function of the magnitude of the voltage change, which may vary with the changes in the black current level of the picture tube.

The voltage at the output charge capacitor 66 remains unchanged during the color synchronization interval when the magnitude of the voltage change V-j developed during the level lock interval is equal to the magnitude of the voltage change V2 developed during the color synchronization interval. This is because during the color synchronization interval, the voltage-10 change at point B increases in the positive direction (from the reference level of the level-lock setting) when the gate control pulse changes and the voltage change V2 simultaneously causes negative voltage mixing at point B. When the picture tube bias is correct, the positive direction the voltage change and the negative voltage change V2 are equal in magnitude, whereby these voltage changes are canceled out during the color synchronization interval, leaving the voltage at point B unchanged.

When the magnitude of the voltage change is less than the magnitude of the voltage change V2, the amplifier 52 proportionally charges the capacitor 56 in a direction that reduces the black current conductivity of the cathode. Conversely, the amplifier 52 discharges proportionally by the charge capacitor 25 56 to cause a decrease in the black current conductivity of the cathode when the magnitude of the voltage change V1 is greater than the magnitude of the voltage change V2.

In more detail with the waveforms of Figure 2, the voltage change amplitude "A" is assumed to be about 3 millivolts when the cathode black current level is correct and varies in the range of a few millivolts (+ ^.) As the cathode black current level increases and decreases relative to the correct level. operating parameters change. Thus, the reference-35 level lock interval setting voltage across capacitor 51 varies with changes in voltage magnitude when the cathode black current level | 13 76232 is changed. The voltage change V2 at point B has an amplitude "A" of about 3 milli-volts, which corresponds to the amplitude "A" associated with the voltage change V1 when the black current level is correct.

5 Expressed by the waveform V _, _ D in Fig. 2, the voltage at the inverting input of the amplifier 52 remains unchanged during the color synchronization interval when the voltages V1 and V2 are both of amplitude "A". However, as expressed by the waveform V1, the voltage 1Q at the input of the amplifier 52 increases by A when the voltage change has an amplitude "A + A", corresponding to a high level of black current.

Currently, amplifier 52 discharges the output charge capacitor 56 so that the bias control voltage applied to the base of transistor 22 causes the collector voltage of transistor 22 to increase, thereby decreasing the black current of the cathode toward the correct level.

Conversely, and as indicated by the waveforms VT, the input voltage of the amplifier 52 increases by an amount A during the color-synchronization time interval when the voltage change V-1 has an amplitude "A-A" corresponding to a low black current level.

In this case, the amplifier 52 charges the output charge capacitor 56, causing the collector voltage of the transistor 22 to increase, whereby the black current of the cathode increases towards the correct level. In either case, multiple color-25 synchronization time slots may be required to achieve the correct black current level.

The voltage developed at point B during the AKB plane lock-color synchronization interval is a function of the values of resistors 31, 32 and 34 and the value of the output impedance 30 Zq at point A. When the signal Vp indicates a positive DC level (+8 volts) during the level lock interval, the junction of resistors 32 and 34 is voltage locked and the current conducted by resistor 31 from point A to point B is a function of the values of ZQ, resistor 31 and resistor 34. During the next color synchronization time interval-35, when there is no negative pulse component of the signal Vp, the diode 35 is non-conductive and the junction of the resistors 32 and 34 is not locked. At present, the resistor 31 leads the differential current from point A to point B as a function of Ζφίη and, in addition to resistors 31, 34, the value of resistor 32 ar-5. The voltage change V2 developed at point B, in response to the negative-direction pulse component of the signal Vp, is proportional to the difference between these currents.

The impedance ZQ at point A can vary interferingly with the cathode bias level (i.e., the cathode limit voltage level) of the picture tube combined with the desired correct cathode black current level. Resistor 31 compensates for changes in the value of impedance Zq and also helps to increase the insensitivity of the ta-cell and color synchronization circuits of circuit 50 to locally generated interference signals, such as horizontal frequency interference.

Point A can be described as a voltage source in series with the aforementioned impedance ZQ. The value of the impedance ZQ is a function of the value of the sensing resistor 30 divided by the gain of the control loop, which is a function of the operating point of the transistor 20. The operating point of transistor 20 during the AKB interval is proportional to the cathode limit voltage. In practice, it has been found that the impedance ZQ can have nominal and maximum values of mi-25 corresponding to 30 ohms and 50 ohms under the conditions of real black current. Thus, the value of ZQ at point A may vary by 67% of the minimum value.

Resistor 31 compensates for changes in impedance at point A so that changes in impedance do not interfere with the intended operation of the signal source Vp, diode 35, and additional pulse circuit including resistors 32, 34. In this example, the non-critical value of resistor 31 is on the order of 200 ohms. Thus, the total impedance shown at point B from point A comprises a resistor 31 and an impedance ZQ, and varies from 230 ohms to 250 ohms with changes in impedance Zq at point A. Correspondingly, at point B there are acceptably small impedance changes 76232 set under true black current conditions. are less than 10%, which is significantly less than the 67% change in impedance that occurs in the absence of resistor 31. In another way, the impedance at point B varies by only + 4% compared to the nominal value of 40 ohms for the impedance ZQ.

Resistor 31 also advantageously increases the insensitivity of the level lock and color synchronization circuit 50 to interference signals that may interfere with or interfere with the control voltage of bias 10 originally developed by charge capacitor 56. The most important ". The latter signals occur periodically at a horizontal line frequency (about 15.734 Hz) and comprise attenuated oscillator pulse signals with an average of approximately zero. The receiver deflection circuits generate these signals during the horizontal return intervals of the image (i.e., including the ai-20 intervals when the AKB system is operating), and can connect to the AKB system via the power supply terminals and the luminance and chrominance signal processing circuits. Interference signals are particularly embarrassing in the AKB system because they can have magnitudes that are significant compared to the small signals (i.e., on the order of a few millivolts) handled by the AKB system. The effect of interference signals can be reduced by using separate filtering and protection techniques, but these are more complex and costly options.

During the level lock interval, the voltage developed across the lock capacitor 51 (.12 ^ .uf) can be appreciably affected by interference signals, such as "raster rings", having a significantly non-zero amplitude at the end of the level lock interval (i.e. close to the time at which the feedback, £ 76232 16 field switch 54 opens). In the absence of the resistor 31, the capacitor 51 can charge to a voltage equal to 67% of the peak amplitude of the interference signal of the raster ring, causing a level lock reference voltage 5 to develop over the capacitor 51 to present a significant error. This error is greatly reduced in the presence of resistor 31, as follows.

During the level locking interval, the signals 10 containing the signals of the DC component and the alternating current raster ring are applied to the positive terminal of the capacitor 51 via the impedance Z_, (about 240 ohms), which corresponds to the impedance

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sin ZQ at point A and 31 series combinations of resistor. The reference voltage is applied to the negative terminal of the capacitor 51 via a low impedance ZA, which corresponds to a small output impedance of the amplifier 52 which acts as a voltage follower during the level locking interval. The impedance ZA is considerably smaller than the impedance Ζβ. The magnitude of the reactive impedance of the capacitor 51 is about 84 ohms in the presence of horizontal frequency raster ring signals. The AC component of the interference signals through capacitor 51 is attenuated considerably by the ratio of impedance Ζζ, to the sum of impedances ZA, Ζβ and Z ^ so that capacitor 51 can charge to a voltage equal to only about 25% of the peak amplitude of the raster ring-25 signal. Correspondingly, the interlock capacitor 51 corresponds more closely to the average of the signals of point A, and the amplitude peaks of the interference signals have a considerably smaller effect on the reference voltage of the plane interlock generated by the capacitor 51.

The system shown automatically provides a zero output current of the amplifier to the charge capacitor 56 when the amplitude of the voltage change is non-zero, corresponding to the correct black current level. Accordingly, manually preset bias controls are not required to set the conductivity sensitivity of the color synchronization amplifier to provide a zero charge output capacitor of the amplifier 17 76232 when the color synchronization signal has a non-zero magnitude for the correct bias conditions.

The described color synchronization amplifier input signal switching arrangement using the additional pulse Vp is preferred in a system in which the color synchronization amplifier 52 comprises a differential input amplifier, such as an emitter-coupled differential amplifier, which will be described later in connection with Fig. 4. This type of differential amplifier has a symmetric input-output signal transmission response that is non-linear over most of its operating range. The otherwise symmetrical operating range of the differential amplifier may remain asymmetrical if, for example, the amplifier's bias voltage is shifted to the side by means of a manually adjustable preset bias control. In such a case, the amplifier would rather provide an output contaminated with the effects of noise and corresponding interference signals, because a shifted asymmetric amplifier response may result in noise rectification in the nonlinear operating range of the amplifier. As a result, the color synchronization of the output signal and the corresponding voltage that develops for the output charging device would be disturbed or mixed by the effects of the rectified noise.

The described combined pulse color synchronization arrangement also advantageously provides a suitable mechanism for compensating each other for different conductivity (gain) equivalents and different limit voltages of the electron guns of the picture tube, for example due to the manufacturing tolerances of the picture tube. This aspect of the disclosed arrangement is discussed in detail in U.S. Patent Application No. 434,328, entitled "Automatic Kinescope Bias Control System Compensated for Kinescope Electron 35 Gun Conduction Dissimilarities," filed October 14, 1982, which is briefly discussed below.

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When the electron guns of the picture tube are identical and at the same time represent a similar conductivity equivalent, they conduct equal black plane currents and represent equal limit voltages (i.e., gate-cathode-5 voltage). In practice, however, electron guns have different conductivity equivalents. In the latter case, the different currents conducted by the electron guns are considered to be true black level currents, in which case the AKB system should remain unchanged and should not change the picture tube bias voltage, even though the electron guns have different black current levels and different corresponding limit voltages.

This result is obtained by the arrangement shown because the magnitude of the voltage change V2 generated at point B is directly proportional to the DC voltage component present at point A. This DC voltage component is proportional to the cathode limit voltage shown by the DC voltage component During the AKB interval (the effect of the induced cathode output current pulse generated in response to the positive lattice control pulse VQ of any work). Thus, if the three electron guns of the picture tube have different currents and limit voltages, corresponding initially to the black level setting conditions, the voltage change Vg is associated with signal processors 14a, 14b and 14c, respectively, each representing different quantities, although each is obtained from a common signal Vp. The different magnitudes of the voltage changes V2 are the result of different boundary voltages, which are represented by the DC components of the different magnitudes developed in pis-3Q. The different magnitudes of the voltage changes V2 are such that the voltage changes developed at point B for the corresponding AKB control loop and V2 are combined so that each AKB control loop 35 remains unchanged. The AKB control loops remain unchanged when the currents of the black level electron guns initially generated change due to changes in the operating parameters of the picture tube, due to the effects of aging of the picture tube or temperature.

In some AKB systems, it may be desirable to generate a voltage change representing the black current during the color synchronization interval, rather than during the previous level locking interval, as described previously. In such an alternative system, the gate control pulse Vg is timed to occur during the color synchronization interval 10, and the signal timing ratios can be used, as shown in the waveforms of Figure 3. In such a system, the timing of the signals V „, VD, V_ and remains

rl ti o C

unchanged.

The waveforms for the alternative system are shown in Figure 3. The positive gate control pulse V'p and the positive auxiliary pulse V'p are simultaneous during the color synchronization interval. During the initial level lock interval, the "setting reference level" is a function of the DC voltage then present at points A and B. During the next 20 color synchronization intervals, the voltage change V '^ has amplitude "A" when the black current level is correct, amplitude A + Δ when black current the level is low and the amplitude is A -Δ. , when the black current level is high. The voltage change V'1 is summed during the color synchronization time interval 25 with the voltage change V'2 of the amplitude "A".

Thus, when the black current level is correct, the voltage change V '^ is canceled with the voltage change, because both then have the same amplitude "A" but opposite polarity. The voltage then applied to the interlocking capacitor 51 from point B is therefore the same as the reference voltage applied from point B during the previous planar interlock interval, whereby the input voltage of amplifier 52 does not change during the color synchronization interval, as indicated by the VCQR signal waveform condition. Thus, the charging capacitor 56 is not charged or discharged by the output current from the amplifier 52. For this AC system, a voltage change can be generated at point B by selectively controlling the positive pulse V'p, the divided voltage version to point B during the color synchronization interval.

5 The level lock reference level developed during the level lock interval for the low and high black current conditions is the same as the level lock reference level developed when the black current level is correct. However, in the case of a large black current, the voltage changes V '^ and 10 do not completely cancel out during the color synchronization interval, and the input voltage of the amplifier 52 increases by Δ. during the color synchronization interval (waveform V „). Inversely

II

the black current condition results in an incomplete cancellation, whereby the input voltage of the amplifier 52 decreases by 15 A during the color synchronization interval (waveform VL> ·

Fig. 4 shows details of the circuit of the signal level locking and color synchronization network 50 of Fig. 1, in which the corresponding elements are identified by the same reference numeral.

In Fig. 4, the amplifier 52 is shown as a steep operation amplifier in which the output current is provided as a function of the input voltage of the amplifier and the input of the transconductance (gm) of the amplifier. Amplifier 52 includes an emitter 25 coupled to transistors 66, 68 arranged in the form of an input differential amplifier and a current repeater ("mirror") network comprising a diode coupled to transistor 71 and transistor 74 disposed in the collector circuit of transistor 68, as shown.

A first constant current source including a biased transistor 69 and a resistor R provides an operating current I to the transistors 66 and 68. A second constant current source including a biased transistor 75 and a resistor 2R provides an operating current 1/2 to the transistor 354. 74 DC the reference voltage source Vppp is connected to the non-inverting input terminal of the amplifier 52 at the base of the transistor 21 76232 68. The input signal, which is color-synchronized (obtained from point B in Fig. 1), is applied through the input capacitor 51 to the inverting input terminal of the amplifier 52 at the base of the transistor 66.

During the AKB level lock interval, the collector of transistor 68 is connected to input capacitor 51 via diode-coupled transistor 71, transistor 74, and conductive switch 54 to form a negative feedback current path. During this time, the charge capacitor 56 is disconnected from the amplifier 52 by a non-conductive switch 55. The input capacitor 51 is charged by the currents conducted by the transistors 68, 71 and 74 as a function of V

XvCiI? the potential is then applied to the input terminal of the capacitor 51 of Figure 1 from point B. Such charging continues until the carrier voltages of transistors 66 and 68 are approximately equal (i.e., the input differential voltage of amplifier 52 is approximately zero). The current I obtained by the transistor 69 is then divided equally between the transistors 66 and 68, whereby the collector currents of the transistors 68 and 74 20 are equal to the collector current (1/2) conducted by the transistor 75. Therefore, all collector currents conducted by transistor 74 flow as collector current in transistor 75. The described current feedback path enters the zero current state before the end of the level lock-25 interval, with transistor 75 "dropping" all collector currents of transistor 74 and zero feedback current flowing to input transistor 66.

During the next SKB color synchronization interval, switch 54 remains non-conductive and switch 55 leads a charge capacitor 30 to connect the converter 56 to the output terminal of amplifier 52. The initial charge on capacitor 56 remains unchanged unless the input signal applied to capacitor 51 is sufficient to change the balanced base bias voltage of transistors 66, 68 generated during the previous level lock interval 35. Thus, when the voltage change has an amplitude "A" corresponding to the condition of the correct black level current, the input voltage to the transistor 66 remains unchanged, as indicated by the waveform of Fig. 2.

V. Correspondingly, transistors 66, 68 have a balanced COR

The 5 input bias voltage and charge by the output charge capacitor 56 remains unchanged. When the black current level is not correct so that the input voltage to the transistor 66 is increased, as indicated by the waveform VH in Fig. 2, the currents conducted by the transistors 68, 71 and 74 decrease. The charge capacitor 56 is discharged through the transistor 75 by an amount proportional to the reduced conductivity of the transistor 74 in response to the increased input voltage. In this case, the transistor 75 acts as a current sink with respect to the discharging charge capacitor 15. Similarly, a decrease in the input voltage applied to the transistor 66 (shown in Figure 2 as waveform V1) causes a corresponding increase in the collector current of the terminal transistor 74. The charge capacitor 56 is charged through the transistor 74 in response to this increased current conductivity, thereby increasing the voltage at the capacitor 56. In this case, the transistor 74 acts as a power source for the charge capacitor 56.

Fig. 5 shows a block diagram of a logic arrangement for the timing signal generator 40 in Fig. 1. The binary 25 counter 90 includes a TIMER and RESET input terminals responsive to a horizontal signal H and a vertical signal V, respectively. V (see Fig. 2} for the portion of the positive pulse that occurs during the vertical return interval. Thus, the output Q ^ -Q ^ all have a low logic level (0000) when the RESET input is positive during the vertical return interval.

During this time, the counter 90 does not respond to the horizontal frequency timing pulses H.

The combinational logic array 92 (i.e., including a plurality of logic ports) monitors the binary states of the outputs of the counter 90 by means of inputs A-D. At the end of the vertical return time interval, the counter 90 is prevented from operating. The logic states of the outputs of the counter 90 indicate a binary number corresponding to the number of timer pulses H, which occurs due to the end of the vertical return interval.

The logic output F of the array 92 provides a high ("1") logic level during the time interval including the second to eighth timer pulses H by sensing the desired state of the counter outputs Q - ^ - Q ^ during this time-10 interval. This signal is delayed by the delay circuit 93 to provide a delay T 1, whereby the AKB timing signal is generated at the output of the delay circuit 93. The delay provided by circuit 93 may be provided, for example, by a series of logic ports connected in series, each providing a certain delay.

The timing signal V 1, develops at the output terminal G of the group 92 during a time slot containing a third to fifth timer pulse H from the end of the vertical return time slot. This signal is delayed by the amount T1 by the circuit 94 and the ta-20 so is transmitted by the circuit 95 to provide the gate control pulse Vg. A level shifting circuit 95 (i.e., a voltage transfer device) is used to provide a signal V 1, the amplitude of which is suitable to control the gate electrode of the picture tube.

The logic output H of the array 92 provides a high ("1") 25 logic level during a time slot that includes a sixth to eighth thought pulse H from the end of the vertical return time slot. Circuit 96 delays this signal by an amount of Tg to generate a timing signal Vg. The additional pulse Vp is obtained from the signal Vg by means of the plane shift 99 of the signal inverter 98 and 30, the latter being used to produce a pulse amplitude suitable for the application of the resistor circuit 32, 34 of Fig. 1. The output E of the group 92 to the BLOCK input terminal of the control signal counter 90 after the end of the AKB time slot (i.e., in the hand of the ninth timer pulse H al-35) to block the counting process.

Claims (15)

An automatic bias control device in a video signal processing system which includes an image reproducing device responsive to video signals fed to its intensity control electrode, comprising: an impedance means (30) to generate a periodic signal whose pulse level is representative of black current level 10 the intensity control electrode during the video signal image switching interval, which derived signal has a level that differs from noil when said black current level is correct, - an information storage device (56), - a gain means (52) with a signal length 15, and an output coupled to the storage means. modifying the information content of the storage means in accordance with the current state of the gain means in response to input signals supplied, and - a device (58) for supplying a bias correction voltage obtained from the storage means to the image display device for presenting a correct black current level, characterized by - an input signal coupling device (31) for coupling the derived signal to the amplifier input, a device (99) for providing a periodic auxiliary signal (V, V-) for the input signal coupling device P and direction that it substantially cancels the response of the amplifier to the size of the derived signal when the size of the derived signal is representative of a correct black current level. Device according to claim 1, characterized in that an impedance device (32, 34) is coupled to the input signal coupling device to establish a bias voltage for the input signal coupling device in the presence of the derived signal and that the auxiliary signal (V, V5) is applied. to the impedance device for modifying the rectified bias with the intention of achieving the canceling amplifier response. 3. Apparatus according to claim 2, characterized in that the auxiliary signal (V, V +) cancels P ^ the derived signal in the input signal path in order to obtain the canceling amplifier response. 4. Device according to claim 3, characterized in that the derived signal (V 1) and the auxiliary signal (V 2) comprise sensing error pulses of opposite polarity and substantially equal in magnitude when the derived signal is representative of a correct black strömnivA. 5. Device according to claim 1, characterized in that the auxiliary signal (V2) has a size which is proportional to a DC component which is best intended. of the intensity control electrode during the extinguishing interval. Device according to claim 1, characterized by a leveling device (51) connected to the input signal switching device at the amplifier input, - switching devices (54, 55) connected to the amplifier output, to the level reading device and to the storage device (25). 92) to keep the switching devices operating during an initial level reading interval to (1) read the amplifier input at a reference voltage responsive to a reference source connected to the amplifier input during the read interval and (2) disconnect the amplifier output amplifier. the switching devices operating during a subsequent sampling interval to (3) cancel the readout of the amplifier input and (4) copy the amplifier output to the storage device; and 35. which one The amplifier ring is shallow, constitutes another function of the magnitude of the derived signal, and the 5 auxiliary signal (V 7. Device according to claim 6, characterized in that the image detector device is an image tube (15) which includes an electron gun comprising a grating electrode (18) and a cooperating cathode density control electrode (16a), - that the automatic bias control device further includes a device (40) for biasing the image tube electron gun during the level interval to induce a cathode output signal of a size proportional to the cathode black current level, and - said derivative device (30) derives the periodic representative signal from the induced cathode output. 8. Device according to claim 1, characterized by a leveling device (51) connected to the input signal switching device at the amplifier input, - switching devices (54, 55) connected to the amplifier output, to the level reading device and to the storage device, - a device ( 92) to keep the switching devices operating during an initial level reading interval to (1) read the amplifier input at a reference voltage as a response to a reference source connected to the amplifier input during the level reading interval and (2) disconnect the amplifier output and the amplifier output and shelving the switching devices operating during a subsequent sampling interval to (3) cancel the readout of the amplifier ring and (4) to copy the amplifier output to the storage device, and at which the subtracted black current representative signal and the auxiliary signal are interrupted. 9. Device according to claim 6 or 8, characterized in that the level reading device includes a capacitor (51) for coupling signals from the input switching device to the amplifier input and - that the auxiliary signal (Vp, V2) has size and richness. to keep the voltage at the amplifier input substantially unchanged when the magnitude of the derived signal is representative of a correct black current level. 10. Apparatus according to claim 9, characterized in that the image reproducing device is an image tube (15) which includes an electron gun containing a grid electrode and a cooperating cathode intensity control electrode, the automatic bias control device further including a device (40) to bias the image tube electron gun during the sampling interval to induce a cathode output signal of a size proportional to cathode black current level, and - the derivation device (30) derives the periodic representative signal from the induced cathode output signal. Device according to any of the preceding claims, characterized in that the amplifier (52) is a differential amplifier. Device according to claim 1, characterized in that an AC coupling capacitor (51) is coupled to the input of the amplifier (52), the input signal coupling device couples the derived signal to the capacitor to change its charge and - the periodic auxiliary signal is switched on. the capacitor for changing its charge, the auxiliary signal having a size and direction to substantially increase the charge.