FI74575B - KOPPLINGSANORDNING FOER UPPTAGNING OCH VIDARELEDNING AV MED RELATIVT HOEG HASTIGHET UPPTRAEDANDE DATASIGNALER I ETT DATAOEVERFOERINGSNAET. - Google Patents

Abstract

1. Circuit arrangement for receiving data signals which occur at a relatively high speed on high-speed incoming lines (NKan1-NKanx) and forwarding these data signals via high-speed outgoing lines (NKb1-NKabx) in a data switching network which includes at least one t.d.m. data switching system (EDS) and in which each t.d.m. data switching system (EDS) is assigned a separate switching device (K) via which the aforementioned data signals are switched and which for this purpose can be controlled by a control device (UEAS) of the t.d.m. data switching system (EDS) which serves to switch items of signalling information which occur at a relatively low speed in the course of the respective data signal connection, characterised in that the switching device (K) is provided with a switch-through store (DS) with incoming cells (Zz) which are individually assigned to the high-speed incoming lines (NKan1 to NKanx) and into each of which an address of a high-speed outgoing line (e.g. NKab1) to be used for acceptance of data signals can be input by the control device (UEAS) of the associated t.d.m. data switching system (EDS), and that in the course of the switching of data signals which occur at the high speed, only that incoming cell (Zz) within the switch-through store (DS) which is assigned to the relevant high-speed incoming line (e.g. NKan1) is operated, and by making available the address (ADR) contained in the incoming cell (Zz) in question the high-speed outgoing line (NKan1) to be used for acceptance of data signals is actuated.

Description

1 74575

Switching device for receiving and forwarding data signals occurring at a relatively high speed in a data transmission network

The invention relates to a switching device for receiving data signals occurring at a relatively high speed high-speed input line 11a and for forwarding these data signals via high-speed output lines. , through which said data signals are transmitted and which can be controlled for this purpose by means of a control of a time-multiplex communication center, through which signaling information occurring at a relatively low speed in connection with the data signal connection in question is transmitted.

It is already known in connection with the transmission of digital data signals occurring at a relatively high speed (64 kbit / s) [telcom report 3 (1980), booklet 6, pages 439, 44θ] to form an existing pre-duplex communication center connection1 in terms of its equipment and software. so that information channels with bit-period-independent 64-kbit / s-1 switching in the duplex method and additional so-called medium-speed channels for transmitting signaling information are available. The latter channels then operate for the so-called out-slot signaling and end-to-end transmission of control signals, which signals must be exchanged between individual interconnected or newly connected time points. However, it is not known in this context how the communication center must be constructed in order to be able to transmit high-speed data signals and the relevant signaling information.

2 74575

The object of the invention is to show a way in which a switching device of the type mentioned at the beginning must be constructed in order to transmit data signals and signaling information occurring at a high speed in a relatively simple manner.

In order to solve the above-mentioned task, the switching device of the above-mentioned quality is characterized in that the switching device has a through-memory memory provided with individually arranged memory locations for high-speed input lines, in which the relevant time-multi-plex The address of the high-speed output line, and that in connection with the transmission of data signals occurring at a relatively high speed, only the switching memory memory location provided for the respective high-speed input line is controlled, and by setting the address contained in that memory location, the output line is switched on for data signal reception.

The invention has the advantage of a relatively small switching technical input for transmitting both data signals occurring at a relatively high speed and signaling information. The transmission of data signals occurring at a relatively high speed takes place practically without loading the time-multiplex communication center or the corresponding control device, after the addresses necessary for the connections to be produced in said switching memory have been registered from this control unit.

Preferably, the bridging memory is connected to the output of the input encoder to indicate its memory locations, which can output address signals corresponding to the high-speed input lines connected to it on the output input side 1a. The switching memory is then connected on the output side 1a to the input of the output encoder, which enables the connection of the high-speed output lines used for switching the data signals to the addresses assigned from the switching memory on the basis of assignment. This advantageously results in a very small switching technical input for transmitting data signals occurring at a relatively high speed. In this case, switching devices which are conventionally used as code transformers in time-division multiplex communication centers can be advantageously used for the input encoder and the output encoder.

Suitably, the input encoder includes a data signal buffer connected on the output input side 1a directly to the throughput input of the output encoder 1. This advantageously results in a very simple forwarding or transmission of data signals occurring at a relatively high speed.

Preferably, the input encoder is connected to operate on the input side via the decision device only to those high speed input lines used for data signal connections. The advantage of this is that in each case only those high-speed input lines have to be taken into account with the corresponding control, which are actually used for data signal connections, thus avoiding unnecessary control events in a simple manner.

Preferably, the above-mentioned decision device is controlled by a control memory provided with a separate memory device for each high-speed input line, in which only a certain signal signal (1-bit) is recorded when the respective high-speed input line is involved in the data signal connection. This advantageously results in a very small switching technical input for controlling your main device.

The above-mentioned signal signals are conveniently recorded in the control memory while the addresses are recorded in the through-memory. This has the advantage of a very small switching control input.

74575 4

Conveniently, a separate buffer memory is provided at the output of the print encoder. The advantage of this measure is that a time channel conversion can still be performed on the output side of the switching device under consideration, or that the data signals preset there in each case can be retained until it can be further derived for processing reasons.

Suitably, in the case of serial data signal bits, the input encoder is connected to the serial-to-parallel transformer on the input side and the output encoder to the parallel-to-serial transformer on the output side. The advantage of this is that both encoders can be built relatively simply.

The invention will now be described in more detail by means of an exemplary embodiment with reference to the accompanying drawings, in which Figure 1 shows a block diagram of a time multiplex communication center together with a switching device according to the invention, and Figure 2 shows a possible embodiment of the switching device according to Figure 1.

The time multiplex data transmission center EDS schematically shown in Fig. 1 is shown only by the connection connections SAGD1 to SAGDm belonging to the only group of connection connections. These connection connections also work for the reception and transmission of signal groups called shells, which in each case have, for example, 6 + 2 or 8 + 2 bits. Of these bits, 6 or equivalent. The 8 bits form the actual data signal lips, while the other two bits represent the status bit, or sync bit, respectively.

The connection connections SAGD1 - SAGDm are connected on the input and output side to the input / output code converter EACD, which is responsible for e.g. further directs the signals input via the individual interface fields to the actual processing section of the data center EDS or, further, directs the signals transmitted from this processing section via the interface circuits. For this purpose, the input / output code converter EACD is connected by two control lines La, Lb and a signal transmission line Ld to the transmission flow control UEAS of the communication center EDS. This transfer flow control UEAS is in turn connected to a memory unit SE, which in turn is connected to a program control unit PE.

With regard to the data center EDS briefly described above, it should also be noted that in the memory unit SE of this data center, each supply line connected to the connection connections SAGD1 -SAGDm - these are transmission lines with which signals to be transmitted - individually has a so-called supply cell. In connection with the supply line belonging to the supply line of the memory unit SE, a reception address denoting said receiving line is recorded in the line designated as the receiving line - through which the signals supplied from the said supply line must be passed on. If, in connection with an existing connection, signals still have to be routed from the supply line to the desired receiving line, the signal transmission request message is transmitted via the input / output code converter EACD via the control line La to receiving line address. This address is then fed via the signal line Ld together with the control signal on the control line Lb to the input / output code converter EACD, which then connects the connection of said supply line to the relevant reception line. In this case, the signals transmitted from the respective supply line to the respective respective reception line can either be routed directly in a certain sense, i.e. without prior storage in the memory unit 74575 6 SE - or these signals can also be temporarily stored in the memory unit SE before being routed. However, these events are not further addressed here, as they have already been explained in more detail elsewhere (see "Siemens-Zeit-schrift", Booklet 2, 1977, pages 82-87).

In the figure, in addition to the devices described above belonging to the communication center EDS, a separate switching device K is provided, which is connected exclusively to the communication center EDS via the control line Le. The switching device K comprises connection connections SAGK1 to SAGKm, which are connected on the input and output side to the connection control circuit EACK, which in turn is connected via the control line Le to the transmission flow control UEAS of the communication center EDS.

The connection connections SAGK1 to SAGKm are further connected on the input and output side via the transmission channels NK1 to NKm, designated as useful channels, to the multiplexer / demultiplexer devices MD1 to MDm. These multiplexer / demultiplexer devices MD1 to MDm are connected to other inputs or outputs via the transmission channels SK1 to SKm designated as signaling channels to the inputs or outputs of the interface connections SAGD1 to SAGDm belonging to the communication center EDS. Furthermore, the multiplexer / demultiplexer devices MD1 to MDm are connected to separate transmission lines Li to Lm, through which they receive signals which must be passed on to the respective useful signal or vast, signaling channels or vast, through which they further carry signals supplied to them by the respective useful signals. and signaling channels.

With respect to the multiplexer / demultiplexer devices MD1 to MDm, it should also be noted that these can be formed by separate multiplexer devices and demultiplexer devices which receive or transmit signals in each case via separate transmission lines.

This means that, for example, the transmission lines NK1, SK1 and L1 shown in Figure 1 exclusively as individual lines 74575 7 can in each case be formed by two lines, in each case one line is arranged for the signal transmission device. The individual signals present on those transmission lines normally form bits in series. Incidentally, it should be noted at this point that - as can be seen from Figure 1 - each multiplexer / demultiplexer device MD1 - MDm is connected to two interface connections of both groups of interface connections shown in Figure 1. These connections, as will be explained in more detail later, process signals with different speeds. The interface connections SAGK1 to SAGKm included in the switching device K process in detail data signals occurring at a relatively high speed, for example 64 kbit / s; the interface connections SAGD1 to SAGDm included in the communication center EDS process signaling information that occurs at a relatively low speed, for example 2.4 kbit / s.

Fig. 2 shows a possible embodiment of the switching device K shown in Fig. 1. In this case, the connection control circuit EACK and the connection circuit SAGK are shown in more detail.

The connection circuit SAGK shown in Fig. 2 comprises a multiplexer Mul connected on the input side to the transmission lines NKan1 to NKanx, through which data signals having a relatively high speed, for example 64 kbit / s, can be transmitted. This multiplexer Mul, which can be used cyclically, is connected on the output side to the input of the serial-to-parallel converter SPU, which in the present case converts the serial data signal bits input to and output from the multiplexer Mul to a parallel mode.

A parallel device LD is connected to the parallel outputs of the series-parallel transformer SPU, of which only the AND element is shown in Fig. 2. However, this decision device LD comprises at least 74575 8 decision elements corresponding to the number of data signal bits transmitted in parallel from the serial-to-parallel transformer SPU. The decision device LD is connected via a control input to a control memory CSf in which character signals may be recorded, for example in the form of individual bits with respect to the transmission conditions NKan1 to NKanx through which data signals or vasts are used for data signal connections.

On its output side, the decision device LD is connected to the input side of the connection control circuit EACK. In detail, the decision device LD is connected on the output side to the input side of the input encoder ECW included in the connection control circuit EACK, namely via a plurality of wires at least equal to the number of data signal bits output from the serial-to-parallel transformer SPU. Input encoder E CV? It should be noted at this point that this may be practically similar to the EACD input code transformer portion of the input / output code converter included in the communication unit EDS shown in Fig. 1.

The connection control circuit EACK shown in Fig. 2 further comprises an output encoder ACW, which is connected on the output side to the interface circuit SAGK. This print encoder ACW may otherwise be similar to the print code converter portion of the above-mentioned input / output code converter EACD according to Fig. 1.

A buffer memory BS is arranged in the combined input of the connection control circuit EACK of the connection circuit SAGK, which is connected on the output side to the parallel-to-series transformer PSU. Thus, it is possible to convert the data signals input to the connection control circuit EACK from the interface circuit SAGK above in parallel again to the original serial format before those data signals are passed on again. The forwarding of these data signals takes place from the output of the 9 74575 parallel-to-series transformer PSU via a demultiplexer Dem, which is connected on the output side to the transmission lines NKabl to NKabx. These transmission lines NKabl to NKabx form so-called high-speed reception lines, through which data signals occurring at a relatively high speed, for example 64 kbit / s, are transmitted. In contrast, the transmission lines NKan1 -NKanx connected to the input side of the multiplexer Mul form so-called high-speed supply lines, through which data signals occurring at a relatively high rate are transmitted at a relatively high rate.

With respect to the demultiplexer Dem discussed above, it should be further noted at this point that this can operate cyclically like the multiplexer Mul shown in Fig. 2.

On the input side, the input encoder ECW connected to the connection connection SAGK is connected to the assignment input of the through-field memory DS by means of the address output Oa. To said address output Oa, the input encoder ECW in each case outputs the address of the supply line NKan1 to NKanx of the high-speed supply line jin through which the data signal has just been input. By means of this address, which is an internal address, a feed cell individually belonging to the supply line in question, such as the feed cell Zz shown in Fig. 2, is controlled in the switching memory DS. To this end, said address is input to the assignment input Es of this input cell Zz. This input cell Zz contains, in the presence of a data signal connection, an address ADR, which denotes the relevant high-speed reception line for receiving data signals of the reception lines NKabl to NKabx. This address is then output from the address output Aa of the input cell Zz in question and is input to the address input Ia of the respective output code converter ACW. The read operation shown then takes place otherwise indestructibly, so that the address in question ADR still exists in the input cell Zz under consideration.

By means of the address entered at the address input Ia of the print encoder ACW, this print encoder ACW is now able to indicate the receive line of the reception lines NKabl to NKabx shown in Fig. 2 through which the above received data signal must be forwarded. For this purpose, according to Fig. 2, this address can be transmitted together with the data signal from the output encoder ACW via the buffer memory BS and the parallel-to-serial converter PSU to the demultiplexer Dem. If the demultiplexer Dem operates cyclically, then at said address the time at which the relevant data signal is transmitted from the buffer memory BS to this combined parallel-to-serial converter, or the like, can be reserved in a controlled manner.

In order to transmit the data signal in question from the print encoder ACW in the manner described above, the data data in question must be input to the input encoder on the input side. To this end, the output encoder ACW is connected by means of the data signal input Id to the output signal Od of the input encoder ECW. A buffer register Reg may be connected to this data signal output Od of the input encoder ECW, as shown in broken lines in Fig. 2. This buffer register Reg may be cached with the data signal currently fed to the input encoder ECW before it is passed through the output encoder ACW.

In order to perform the above-mentioned assigned forwarding of the data signals on the high-speed supply lines NKan1 to NKanx via the high-speed receiving lines NKabl to NKabx, the switching memory DS in the supply cells belonging to these high-speed supply lines must be registered on the address of the respective high-speed receiving lines. These addresses are in each case fed to the address recording input Ea of the input cell in question via the control line Le, which is also shown in Fig. 1. The input side of the already mentioned control memory CS is also connected to this control line Le according to Fig. 2.

Having now described the structure of the devices shown in the drawings, the operation of the switching device according to the invention will be explained in more detail below. For this purpose, it is assumed that signals are to be fed via the transmission line L1 shown in Fig. 1, which must be passed on via the line Lm. In connection with the establishment of the desired connection, signaling information is first input via the transmission line Li. This signaling information then arrives via the signaling channel SK1 to the interface connection SAGD1 of the communication center EDS. Based on the presence of the selection information in the signaling information, the desired reception line Lm then takes place in the communication center EDS. First, the address of the desired receiving line is recorded in the supply cell belonging to the supply line of the memory unit SE in question. In this case, however, the supply line for the data transmission center EDS is formed on the signaling channel SK1, and the reception line is formed on the signaling channel SKm. The clearing and settlement events in question will not be explained in more detail here, as they have already been explained in the second paragraph mentioned above. After recording said address in the supply cell belonging to the examined supply line, signaling information can then be exchanged via the communication center EDS between the devices connected to the supply line Li and the receiving line Lm (end-to-end signaling).

The above-mentioned address is further transmitted from the communication center EDS via the control line Le to the switching device K. As already mentioned in connection with Fig. 2, this address is recorded in the input cell DS of the switching control circuit EACK of the connection control circuit K of the switching device K. In the case of this supply cell, the switching memory DS is a memory cell which belongs to the same supply line L1, in respect of which a memory cell (supply cell) is already arranged in the memory unit SE. In this case, however, the supply cell arranged in the through-memory DS belongs, precisely, to the assumed case for the payload channel NK1. The address stored in the supply cell of the through-memory DS thus denotes, strictly speaking, the payload channel NKm as the reception line in the assumed case.

74575 12

With the registration of the address in the input cell of the switching memory DS according to Fig. 2, a corresponding registration is also made in the control memory CS according to Fig. 2. This recording in the form of a signal signal or a bit, in this case, determines from which supply line or from which input channel the data signals to be transmitted are to be transmitted. For this purpose, the control memory CS and the multiplexer Mul shown in Fig. 2 are matched in their operating modes.

If the addresses are recorded in the respective input cells of the memory unit SE of the data transmission center EDS and the via memory DS of the switching device K, then the events concerning the transmission of signaling information and data signals take place in principle independently of one another. The transmission of data signals occurring at a relatively high speed via a separate switching device K then takes place in addition to this, without additional loading of the data transmission center EDS. This means that the EDS of this communication center does not have to set up any separate work or response memory cycles for transmitting said data signals, as is otherwise the case when signaling information has to be received or received. This means that in the present case, the data transmission center EDS is not loaded with transmission events interfering with the entire transmission capacity in connection with the transmission of data signals occurring at a relatively high transmission rate. Thus, the EDS data center - which may be part of a data network together with several corresponding data centers - can be used in a simple manner in a service integrated digital long distance network (ISDN) without significantly reducing the transmission capacity of devices normally connected to p.

Claims (8)

13. , 74575 Patent claims A switching device at a relatively high speed for receiving high-speed input lines 11a (NKan1 to NKanx) and for forwarding these data signals via high-speed output lines (NKabl - NKabx) to a data network in at least one time-division multiplexing (EDS) the data transmission center (EDS) comprises a separate switching device (K) through which said data signals are transmitted and which can be controlled for this purpose by a time multiplex data transmission center (EDS) control device (UEAS), through which the data signal connection is transmitted at a relatively low speed signaling information, characterized in that the switching device (K) has a 1-switching memory (DS) provided with memory locations (Zz) individually arranged for the high-speed input lines (NKan1 to NKanx), in which the time-multiplex communication in question can be recorded. the control unit (EDS) of the control panel (UEAS) for the reception of the data signal in question by the high-speed output line in question (e.g. NKabl) address, and that in connection with the transmission of information signals occurring at a relatively high speed, only the memory location (Zz) arranged on the respective high-speed input line (e.g. NKan1) is controlled by the switching memory (DS) and by setting the address (ADR) contained in that memory location the relevant high-speed output line (NKabl) for receiving data signals. Switching device according to Claim 1, characterized in that the bridging memory (DS) is connected to the output (Oa) of the input encoder (ECW) to indicate its memory locations (Zz), which on the output side 1a can output address signals corresponding to the high-speed input lines (NKan1 to NKanx) connected thereto. and that the bridging memory (DS) is connected on the output side 1a (Od) to the input (Id) of the output encoder (ACW), which enables the connection of the output lines (NKabl -NKabx) used for forwarding the data signals to the addresses transmitted from the switching memory (DS). . Switching device according to Claim 2, characterized in that the input encoder (ECW) comprises a data signal buffer (Reg) which is connected on the output side a directly to the switching input (Id) of the output encoder (ACW). Switching device according to Claim 2 or 3, characterized in that the input encoder (ECW) is connected on the input side via the decision device (LD) only to the high-speed input lines n (NKan1 to NKanx) which are used for the data connection i n. Switching device according to Claim 4, characterized in that the decision device (LD) is controlled by a control memory 11a (CS) in which a separate memory location is arranged for each high-speed input line (NKan1 to NKanx), in which only the then determined signal signal (1-bit) is recorded. , when the relevant high-speed input line (eg NKan1) is used for the data signal connection. Switching device according to Claim 5, characterized in that the signal signals are recorded in the control memory (CS) while the addresses (ADR) are stored in the switching memory (DS). Switching device according to one of Claims 2 to 6, characterized in that a separate buffer memory (BS) is arranged at the output of the print encoder (ACW). Switching device according to one of Claims 2 to 7, characterized in that, in the case of serial data signal bits, the input encoder (ECW) is connected on the input side 1a to a serial-to-parallel transformer (SPU) and the input encoder (ACW) is connected to the output input side a parallel. series transformer (PSU). * 15 _, 74575