FI112548B - Arrangements for data transfer - Google Patents

Description

1 112548 System for data transfer

The invention relates to a multiplex system for transmitting data on a data bus between a plurality of transceiver pairs, including a cable having at least one power supply line and at least one line for a data bus, and a plurality of smart connector bases connected to cable wires, each intelligent connector base for data transfer between smart connector bases, as transmitters generate data signal transitions on the transmission bus.

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The present invention can be applied in place of any traditional data transmission protocol, such as the CAN protocol, in an Intelligent Wiring System (IWS) for vehicles as described in the applicant's patent applications WO 99/25585, WO 99/25586, WO 99/26331 , WO 95/15594, WO 97/4901 and PCT / FI98 / 00710. Of course, the invention can also be applied to intelligent wiring systems for real estate automation in homes and offices.

In known systems, a plurality of consecutive signal states "1" or "0" are used to represent the desired binary value data. Conventional bit-based data message transmission is sensitive to EMI interference, which is one of the basic problems when using data transmission systems in the automotive industry. Another problem is an overloaded data bus, where data collisions must be prevented in a system where several dozen load-carrying smart connector bases (smart nodes) 25 need to be communicated with each other and / or the central processing unit via the data bus.

US 4,429,384 discloses a communication system for transmitting digital information over a bus channel using pulses having substantially different pulse lengths for transmitting bits "0" and "1".

In this prior art, the message is also based on the successive signal states "1" and 2 112548 "O", which need to be distinguished and therefore this system suffers from the same problems as described above.

US-A-5,588,023 discloses communication between only one transmitter and one 5 receivers, and no arbitration method by which a plurality of transmitters and receivers can be connected to a bus multiplex system. The teachings of this US publication are not as such applicable to the system of the invention because conventional methods of arbitration of pulse / bit systems are not directly applicable to the multiplex system of the invention.

It is an object of the present invention to provide an improved system for data transmission so that the above problems can be substantially reduced.

This object is achieved by a system having the features of claim 1.

In the following, preferred embodiments of the invention will be illustrated in greater detail with reference to the accompanying drawings, in which the graph illustrates an example of a data bit quartz transmission transmitted by a method of modulating the time delay between successive transitions; Figure 2 illustrates an example of a message transmitted in a plurality of data bit quartets in a packet format, each bit quartet being formed according to the principle of Figure 1; Figure 3 shows a part of an Intelligent Wiring System (IWS) in which the new data transmission method can advantageously be applied; 3, 112548, Figure 4 illustrates an example of a message consisting of a plurality of transition delay modulated bit quartets according to the principle of Figure 1, the message being designed to be applied in the system of Figure 3; Figure 5 shows an example of a driver unit (transceiver) operating according to the new IWS protocol.

Physical Execution and Device (Figure 3 and Figure 5) 10 • Unshielded floating differential two-wire data transmission cable with mixed topology without a terminal • Master junction unit with independent line state monitoring circuit for both data wires 15 • Speed limited phase alternate transmitters with high impedance • differential analog receivers with anti alias filter and window discriminator 20 · digital signal converter for the received analog signal.

At the end of the specification, the transceiver device will be described in more detail with reference to Figure 5.

25 Modulation Method (Figure 1) The IWS data transmission is based on pulse width modulation of bit quartets. Each quartet contains four data bits or represents four data bits. The binary value of each quartet is used to set the vii-30 ve between successive output transitions. The receiver measures the delays between transitions and converts them back to the original data.

112548 4 This modulation method produces fewer transitions and less EMI interference than conventional bit based transmission methods when transmitting arbitrary data at the same average bit rate because each transition on a signal path can carry one quartet (four bits) of data.

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Transitions (Figures 1, 2 and 4)

The modulation method depends on the signal transitions and not the signal transitions. There are no up / down or on / off modes or bits as required in the previous 10 communications implementations for the automotive industry. Transition in the IWS (Intelligent Wiring System) cable is signaled to supplement the electrical charge of the signal wires and then by passively leaving the new charge state or using only a weak output driver to maintain the signal space in the cable.

15 Synchronization (Figures 1, 2 and 4)

A special synchronization model is used to find the beginning and end of each data frame. The synchronization model comprises two successive transitions. The time delay between synchronization transitions is one transmission clock period. Since all other quartets and heart rate signals have a longer delay between transitions, no transmitted signal can interfere with the synchronization signal. This signal can be included and detected at any point in time during data transmission. Each synchronization model starts receiving a new data frame.

25 Supervision

When no data transfer is required, the signal line charge is refreshed by a specific heart rate signal. Each unit is responsible for generating a heart rate signal for specified periods of time.

: 30

The heart rate signal is also used to detect the condition of the transmission line. If for some reason the heart rate signal is not working properly, the monitoring system can immediately notify the user of the failure and change the data transmission protocol to an emergency operation.

In emergency mode, the transmission rate is slower and the data transmitters do not operate in 5 complementary mode as normal. Transitions in emergency operations are energy pulses instead of varying charges.

The master connector unit disconnects all lines that cannot generate a suitable jump signal to enable the rest of the system to function. All control elements are doubled independently of each other. Every single data cable failure is detected and corrected without major malfunction.

Data Collision Prevention 15

If two (or more) transmitters decide to transmit the transition exactly or almost simultaneously, the result is always a simple transition, because both transmitters place the same new electrical charge on the signal cable to develop a new and exactly the same type of transition.

; 20 The transmitter is not allowed to send a new transition immediately when it detects a new transition. This backup delay prevents two or more transmitters from simultaneously placing different charges on the signal cable and causing a real collision situation.

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Due to the method presented, there is no chance of a collision between two or more transmitters. Instead, each transmitter has the ability to send new transitions without the risk of signal degradation in an undefined state.

30 6 112548 Bus Arbitration

Any transmitter can start transmitting when it detects a synchronization signal. If no active transmissions are in progress, the transmitter itself may start transmitting a new synchronization signal. Whenever the active transmitter detects an extra transition in the signal cable at any time, it should stop transmitting immediately. This normally occurs during the first quartets of a data packet. A transmitter with a shorter quartet transmits a quartet transition earlier than transmitters with a longer message. A transmitter with a ly-10 lower quartet may continue uninterrupted and a transmitter with a longer quartet will drop out. An extra transition situation may also occur when a very high priority transmitter breaks the transmission of a low priority transmitter by transmitting a new synchronization pattern in the middle of the low priority data frame.

15 Transmission signal timing (Fig. 1) The transmission signal timing depends on the selected transmission clock frequency. This frequency sets the step value for the transmitter delay unit. The shortest delay, which is one transmission clock period, is reserved for the synchronization signal. Multiple transmission clock periods are used to transmit data quartet transitions. Two periods are used for the first binary data value 0000 (= 0) and three periods are used for the next binary data value 0001 (= 1). Finally, the 17 transmission clock period delay is used before the quartet's decision transition to represent the maximum 25 binary data values 1111 (= 15). Any longer delay between transitions means the heart rate signal and the bus idle state.

Received Signal Timing 30 The receiver uses the receive clock frequency, which is a multiple of the transmit signal frequency. This allows the receiver to more accurately measure the delay between transitions 112548 7 and to perform the initialization of the digital signal before receiving the actual transaction.

After receiving the transition, the receiver evaluates the time delay value measured as the last 5 consecutive transitions and decides how to interpret the received time information. Only narrow time windows are allowed for potential data quartets. Between the allowed signal width windows there are error free areas where false random transitions can be detected. If the measured delay value did not belong to any of the allowed signal windows, it is rejected by the receiver. This procedure effectively prevents random signal patterns from being received accidentally as a valid data packet.

If the receiver detects an illegal transition while actively receiving a message, it may generate an extra synchronization signal to interrupt this transmission and immediately begin retransmission.

Iws message format (Figures 2 and 4)

All messages have the same basic format of 32 data bits distributed to either all: 20 receivers or one receiver with acknowledgment. All unused bit modes (zero-value quartets) are spontaneously optimized for the shortest • '| length during modulation.

: '/ The message contains the following sections: 25 · synchronization from the transmitting unit • priority selection field • data field (8/32 bits) • error checking field • synchronization from the transmitting unit 30 · description field • synchronization from the receiving unit 8 112548

Priority Selection Field (FIGS. 2 and 4) This message section begins with a synchronization signal from the previous message or with a new synchronization signal generated by the transmitter itself. All active transmitters 5 can then start transmitting the selected priority quartz for the message. Possible priority quartet values are 1-15. The zero value is reserved for the acknowledgment field. Many transmitters may have the same message priority. All transmitters start sending their messages simultaneously. During transmission, any transmitter that attempts to transmit a longer quartet of the message than the others is effectively eliminated by the anti-collision mechanism. At the end of the packet, only one transmitter should be actively transmitting.

In the special case where more than one message has exactly the same address and data fields, all these messages will be properly distributed at the same time.

Destination Address Field (Figures 2 and 4) This section of the message contains two quartets that individually select the 20 recipients of the message. If both target quartets have a zero value, then each receiver should receive the sent message. All receivers must have a unique pair of address quartets. This limits the maximum number of receivers to 255 units, leaving one address for transmission.

25 Data Field (Figures 1, 2, and 4) This section of the message contains eight quartets used for the actual data. The maximum number of data bits in a single message packet is 32 bits. The unused space is spontaneously optimized for the shortest length during modulation.

9 1 I z o 4 6

Error Checking Code Field (Figures 2 and 4) This section of the message contains two quartets representing an 8-bit ECC value calculated from the destination address field and the data field. Error Checking can detect 5 unusual errors that have undergone error checking procedures.

Acknowledgment Field (Figures 2 and 4) This message section contains three quartets followed by a synchronization pattern sent by the message receiver. The first quartet is zero and the next two quartets contain the acknowledgment receiver address.

If any of these transitions are missing, the transmitter should immediately send a new synchronization signal to resume sending the message.

15 If the correct acknowledgment is not received after three retries, the transmitter should delay the message and try again later. Messages addressed to all receivers will not be acknowledged.

Error Check 20

The timing quality of the received signal is checked during reception. This quality control is important to prevent random interference signals from being recognized as a good message. No error checking method used for · short messages is reliable enough to reject random 25 signals alone without checking the signal quality.

,:, When transmitting a message, the transmitter compares the transmitted signal with the received signal. If there is any difference between the two signals, the transmitter stops sending the message before it is received.

30: 111548

When receiving a message, the receiver checks the EEC code at the end of the data packet to ensure that the content is logically correct and not tangled during transmission.

5 All of these precautions are taken to ensure that no message can be accidentally misidentified as a result of noise or interference in IWS cabling.

In the event that a particular signal needs very special attention in terms of error checking, the signal may be selected to include a bit pattern that is not near any other bit pattern used. In this way, the possibility of accidentally receiving this individually selected signal is extremely unlikely.

15 Example of a system for applying the method

The system of Figure 3 includes an IWS (Intelligent Wiring System) cable comprising two wires for power supply and two wires for data bus. The system may have multiple cable branches, each starting with [20 master connector units, optional, and may be replaced by a ring cable to connect the cable branches to each other. The master connector block is a data-! in communication with an adapter and monitoring unit through which any outside programming of the system can be performed, which monitors the heart rate signal and error messages from the system, and controls the on-line display to display system 25 operating status. Each cable branch is provided with a plurality of intelligent sockets that control the power supply from the IWS cable to different loads, such as trunk light L1, in response to different input controls, such as closing the trunk lid switch SI, from any system socket. The number of connector sockets in the entire vehicle system is typically in the range of 30-30 to 50, but may vary substantially depending on the application (e.g. buses, ships, homes and offices).

1 1 r A ρ j ^ 1 ^ c

The operation of the system member shown in Figure 3 in the light of Figure 4 follows the steps below.

- the boot lid opens and closes the boot light switch SI

5 - Input pin II engages and wakes up socket 11 CPU - socket 11 initiates evaluation of a new input signal using a vehicle virtual circuit diagram stored in socket memory - socket 11 detects that it does not have all the information on wiring 10 of this signal 11 - socket 11 send priority class 4 message to socket 10 from virtual switch number 51 to number 1 (unused data fields are 00000) - socket 10 receives message and checks error check code 5220 - socket 10 acknowledges with OK message after successful socket 15 from socket 10 - socket 10 evaluating a new input message using a virtual vehicle diagram of the vehicle stored in the connector socket memory - connector socket 10 detects that signal 51 goes to output terminal OI and activates it '·' ': 20 - finally luggage compartment v alo lights up the transceiver device according to Fig. 5 The contents and / or functions of the transceiver blocks AL are as follows: 112548 12 D transmission control logic includes a state machine that controls all transmission logic units E idle delay detector detects long delays required to generate a heart rate signal 5 F steep edge filter uses 2 ps delay line to remove signal noise from G to sync and new to detector H CRC control logic is used for error detection calculation during transmission and reception The 10 L reception line driver contains differential al the I / O filter, the amplifier, and the Schmitt trigger J slant edge filter utilize a 4 ps delay line to remove the signal noise K The pulse width demodulator converts the delayed transitions back to binary 15 quarts L The reception control logic includes a state machine that controls all reception logic units.

Claims (13)

A multiplex system for transmitting data on a data bus between a plurality of transceiver pairs, the system comprising a cable having at least one power supply line 5 and at least one line for the data bus and a plurality of smart connector bases (10,11) connected to cable wires, the transmitter and receiver for data transmission between smart connector bases, the transmitters generating data signal transitions on the transmission bus, characterized in that the transmitting connector bases are arranged to modulate the delay of the modulated delay to receive the modulated delay to and convert each modulated delay back to its original binary value data based on the measured time of the modulated delay, and that any connector base is simultaneously ie transmitting and receiving and comparing the transmitted signal with the received signal and immediately terminating the transmission if it detects a transition that is not transmitted by itself. A system according to claim 1, characterized in that any transmitter is allowed to start a transmission when it detects a synchronization signal that is transmitted by any transmitter, including its own transmit signal, and one or more transmitters may be extended; simultaneous transmission as long as any of the two or more transmitters detects an extra transition that is not the transmitter itself; : 25 transmissions, whereby the latter transmitter, which has detected an extra transition, stops the transmission and one or more transmitters with shorter: modulated delay, continue transmission without interruption until only one transmitter with the shortest modulated delays is sent. : 30 A system according to claim 1 or 2, characterized in that a synchronization pulse of a predetermined length is used to interrupt the transmission of the message in progress. 1125-48 System according to one of Claims 1 to 3, characterized in that each modulated delay is predetermined to represent four data bits, i.e. a bit quartet. A system according to any one of claims 1 to 4, characterized in that a data packet consisting of a plurality of modulated delays is preceded and followed by a short time delay of a predetermined duration between two synchronization transitions, which synchronization transitions are used to find the beginning and end of each data packet. -10 sit or end transit for a data packet. System according to claim 5, characterized in that the time delay between the two synchronization transitions is shorter than any modulated delay. 15 The system of any one of claims 1-6, wherein the transitions are generated on the data bus by varying degrees of electrical charge, characterized in that the charge of the data bus signal lines is refreshed by a synchronous signal when no data transfer is required, with a time delay between: for maximum binary data. Γ A system according to any one of claims 1 to 7, characterized in that *; : modulated delay includes valid time apertures and invalid time apertures v · 'with respect to the occurrence of a modulated delay terminal transition, v: 25 The system of claim 5, characterized in that the first modulated delay within the data packet defined between two synchronization transition pairs is set to represent the priority level of the data packet. 30 is 112 b 4 6 System according to one of Claims 1 to 9, characterized in that two of the modulated delays are assigned to represent the address of the target receiver. System according to one of Claims 1 to 5, characterized in that the receiver 5 uses a receive clock frequency which is several times higher than the frequency of the transmitted signal, which sets a step value for the modulated delay. A system according to any one of claims 1 to 11, characterized in that, after the synchronization transfer terminating the transmission, the receiver transmits an acknowledgment field containing a first transition having a predetermined delay after the synchronization transition and a second and third transition whose delays are adjusted to receiver address. System according to one of Claims 1 to 12, characterized in that each data packet is terminated by an error checking code (ECC) consisting of at least two transition delays having a predetermined duration. ie 112C48