ES2684846A1 - Dispositivo y procedimiento para la identificación unívoca de un circuito integrado - Google Patents

Dispositivo y procedimiento para la identificación unívoca de un circuito integrado Download PDF

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Publication number
ES2684846A1
ES2684846A1 ES201730535A ES201730535A ES2684846A1 ES 2684846 A1 ES2684846 A1 ES 2684846A1 ES 201730535 A ES201730535 A ES 201730535A ES 201730535 A ES201730535 A ES 201730535A ES 2684846 A1 ES2684846 A1 ES 2684846A1
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Spain
Prior art keywords
circuit
output
translation
machine
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES201730535A
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English (en)
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ES2684846B1 (es
Inventor
Luis Alfonso ENTRENA ARRONTES
Honorio MARTÍN GONZÁLEZ
Enrique SAN MILLÁN HEREDIA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universidad Carlos III de Madrid
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Universidad Carlos III de Madrid
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Publication date
Application filed by Universidad Carlos III de Madrid filed Critical Universidad Carlos III de Madrid
Priority to ES201730535A priority Critical patent/ES2684846B1/es
Publication of ES2684846A1 publication Critical patent/ES2684846A1/es
Application granted granted Critical
Publication of ES2684846B1 publication Critical patent/ES2684846B1/es
Active legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/44—Program or device authentication

Abstract

La invención describe un dispositivo (1) que comprende: un primer circuito (2) generador de pulsos transitorios que tiene una entrada (2e) y una salida (2s); un segundo circuito (3) generador de pulsos transitorios, idéntico al primero excepto por las diferencias inherentes al proceso de fabricación, que tiene una entrada (3e) y una salida (3s); un circuito (4) árbitro que tiene unas primera y segunda entradas (4e1, 4e2) conectadas a la salida (2s) y a la salida (3s), y una salida (4s) de circuito árbitro, donde el circuito (4) árbitro está configurado para determinar si una señal de entrada "pregunta" introducida simultáneamente en la entrada (2e) y en la entrada (3e) llega antes como un pulso a la salida (2s) o a la salida (3s) y para emitir un pulso de salida en función de ello a través de la salida (4s) de circuito árbitro.

Description

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Claims (1)

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ES201730535A 2017-03-31 2017-03-31 Dispositivo y procedimiento para la identificación unívoca de un circuito integrado Active ES2684846B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES201730535A ES2684846B1 (es) 2017-03-31 2017-03-31 Dispositivo y procedimiento para la identificación unívoca de un circuito integrado

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES201730535A ES2684846B1 (es) 2017-03-31 2017-03-31 Dispositivo y procedimiento para la identificación unívoca de un circuito integrado

Publications (2)

Publication Number Publication Date
ES2684846A1 true ES2684846A1 (es) 2018-10-04
ES2684846B1 ES2684846B1 (es) 2019-05-10

Family

ID=63683313

Family Applications (1)

Application Number Title Priority Date Filing Date
ES201730535A Active ES2684846B1 (es) 2017-03-31 2017-03-31 Dispositivo y procedimiento para la identificación unívoca de un circuito integrado

Country Status (1)

Country Link
ES (1) ES2684846B1 (es)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030204743A1 (en) * 2002-04-16 2003-10-30 Srinivas Devadas Authentication of integrated circuits
EP2665225A1 (en) * 2011-01-13 2013-11-20 Mitsubishi Electric Corporation Bit generation device and bit generation method
US20140041040A1 (en) * 2012-08-01 2014-02-06 The Regents Of The University Of California Creating secure multiparty communication primitives using transistor delay quantization in public physically unclonable functions
US20140327468A1 (en) * 2013-05-03 2014-11-06 International Business Machines Corporation Physical unclonable function generation and management
CN106470024A (zh) * 2015-08-18 2017-03-01 飞思卡尔半导体公司 使用穆勒c元件的无假信号时钟切换电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030204743A1 (en) * 2002-04-16 2003-10-30 Srinivas Devadas Authentication of integrated circuits
EP2665225A1 (en) * 2011-01-13 2013-11-20 Mitsubishi Electric Corporation Bit generation device and bit generation method
US20140041040A1 (en) * 2012-08-01 2014-02-06 The Regents Of The University Of California Creating secure multiparty communication primitives using transistor delay quantization in public physically unclonable functions
US20140327468A1 (en) * 2013-05-03 2014-11-06 International Business Machines Corporation Physical unclonable function generation and management
CN106470024A (zh) * 2015-08-18 2017-03-01 飞思卡尔半导体公司 使用穆勒c元件的无假信号时钟切换电路

Also Published As

Publication number Publication date
ES2684846B1 (es) 2019-05-10

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